Index: /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 45441)
+++ /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 45442)
@@ -1591,5 +1591,6 @@
         Assert(!(pVCpu->hm.s.vmx.HCPhysVirtApic & 0xfff));              /* Bits 11:0 MBZ. */
         rc  = VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, 0);
-        rc  = VMXWriteVmcs64(VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hm.s.vmx.HCPhysVirtApic);
+        rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hm.s.vmx.HCPhysVirtApic);
+        AssertRCReturn(rc, rc);
 
         val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;         /* CR8 reads from the Virtual-APIC page. */
@@ -1977,5 +1978,4 @@
     RTCCUINTREG uReg = ASMGetCR0();
     int rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR0, uReg);
-    AssertRCReturn(rc, rc);
 
 #ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
@@ -1984,5 +1984,5 @@
     {
         uint64_t uReg = hmR0Get64bitCR3();
-        rc = VMXWriteVmcs64(VMX_VMCS_HOST_CR3, uReg);
+        rc |= VMXWriteVmcs64(VMX_VMCS_HOST_CR3, uReg);
     }
     else
@@ -1990,10 +1990,9 @@
     {
         uReg = ASMGetCR3();
-        rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR3, uReg);
-    }
-    AssertRCReturn(rc, rc);
+        rc |= VMXWriteVmcsHstN(VMX_VMCS_HOST_CR3, uReg);
+    }
 
     uReg = ASMGetCR4();
-    rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR4, uReg);
+    rc |= VMXWriteVmcsHstN(VMX_VMCS_HOST_CR4, uReg);
     AssertRCReturn(rc, rc);
     return rc;
@@ -2223,10 +2222,9 @@
 
     int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, idxHostMsr);
-    AssertRCReturn(rc, rc);
 
     /*
      * Host Sysenter MSRs.
      */
-    rc  = VMXWriteVmcs32(VMX_VMCS32_HOST_SYSENTER_CS,    ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
+    rc |= VMXWriteVmcs32(VMX_VMCS32_HOST_SYSENTER_CS,    ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
 #ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
     if (VMX_IS_64BIT_HOST_MODE())
@@ -2591,5 +2589,4 @@
     rc    |= hmR0VmxLoadGuestRsp(pVM, pVCpu, pCtx);
     rc    |= hmR0VmxLoadGuestRflags(pVM, pVCpu, pCtx);
-    AssertRCReturn(rc, rc);
     return rc;
 }
@@ -2725,5 +2722,5 @@
 
         /* Write VT-x's view of the guest CR0 into the VMCS and update the exception bitmap. */
-        rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_CR0, u64GuestCR0);
+        rc  = VMXWriteVmcsGstN(VMX_VMCS_GUEST_CR0, u64GuestCR0);
         rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap);
         Log2(("VMX_VMCS_GUEST_CR0=%#RX32\n", (uint32_t)u64GuestCR0));
@@ -3002,5 +2999,5 @@
         /* Save the host and load the guest debug registers. This will make the guest debug state active. */
         rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
-        AssertRCReturn(rc, rc);
+        AssertRC(rc);
         Assert(CPUMIsGuestDebugStateActive(pVCpu));
         Assert(fInterceptMovDRx == false);
@@ -3012,5 +3009,5 @@
         /* Save the host and load the hypervisor debug registers. This will make the hyper debug state active. */
         rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
-        AssertRCReturn(rc, rc);
+        AssertRC(rc);
         Assert(CPUMIsHyperDebugStateActive(pVCpu));
         fInterceptMovDRx = true;
@@ -4787,5 +4784,4 @@
     rc    |= hmR0VmxSaveGuestRsp(pVM, pVCpu, pMixedCtx);
     rc    |= hmR0VmxSaveGuestRflags(pVM, pVCpu, pMixedCtx);
-    AssertRCReturn(rc, rc);
     return rc;
 }
@@ -5006,8 +5002,7 @@
     /* Guest CR0. Guest FPU. */
     rc = hmR0VmxSaveGuestCR0(pVM, pVCpu, pMixedCtx);
-    AssertRCReturn(rc, rc);
 
     /* Guest CR4. */
-    rc = hmR0VmxSaveGuestCR4(pVM, pVCpu, pMixedCtx);
+    rc |= hmR0VmxSaveGuestCR4(pVM, pVCpu, pMixedCtx);
     AssertRCReturn(rc, rc);
 
@@ -5019,5 +5014,4 @@
         {
             rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_CR3, &uVal);
-            AssertRCReturn(rc, rc);
             if (pMixedCtx->cr3 != uVal)
             {
@@ -5028,18 +5022,17 @@
 
             /* We require EFER to check PAE mode. */
-            rc = hmR0VmxSaveGuestAutoLoadStoreMsrs(pVM, pVCpu, pMixedCtx);
-            AssertRCReturn(rc, rc);
+            rc |= hmR0VmxSaveGuestAutoLoadStoreMsrs(pVM, pVCpu, pMixedCtx);
 
             /* If the guest is in PAE mode, sync back the PDPE's into the guest state. */
             if (CPUMIsGuestInPAEModeEx(pMixedCtx))  /* Reads CR0, CR4 and EFER MSR. */
             {
-                rc  = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &pVCpu->hm.s.aPdpes[0].u);
+                rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &pVCpu->hm.s.aPdpes[0].u);
                 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &pVCpu->hm.s.aPdpes[1].u);
                 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &pVCpu->hm.s.aPdpes[2].u);
                 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &pVCpu->hm.s.aPdpes[3].u);
-                AssertRCReturn(rc, rc);
                 /* Set the force flag to inform PGM about it when necessary. It is cleared by PGMGstUpdatePaePdpes(). */
                 VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
             }
+            AssertRCReturn(rc, rc);
         }
         pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_CR3;
@@ -5066,18 +5059,19 @@
 {
     uint32_t u32Val = 0;
-    int rc = VMXReadVmcs32(idxSel, &u32Val);         AssertRCReturn(rc, rc);
+    int rc = VMXReadVmcs32(idxSel, &u32Val);
     pSelReg->Sel      = (uint16_t)u32Val;
     pSelReg->ValidSel = (uint16_t)u32Val;
     pSelReg->fFlags   = CPUMSELREG_FLAGS_VALID;
 
-    rc = VMXReadVmcs32(idxLimit, &u32Val);           AssertRCReturn(rc, rc);
+    rc |= VMXReadVmcs32(idxLimit, &u32Val);
     pSelReg->u32Limit = u32Val;
 
     RTGCUINTREG uGCVal = 0;
-    rc = VMXReadVmcsGstN(idxBase, &uGCVal);          AssertRCReturn(rc, rc);
+    rc |= VMXReadVmcsGstN(idxBase, &uGCVal);
     pSelReg->u64Base = uGCVal;
 
-    rc = VMXReadVmcs32(idxAccess, &u32Val);          AssertRCReturn(rc, rc);
+    rc |= VMXReadVmcs32(idxAccess, &u32Val);
     pSelReg->Attr.u  = u32Val;
+    AssertRCReturn(rc, rc);
 
     /*
@@ -5115,7 +5109,6 @@
     {
         rc = hmR0VmxSaveGuestCR0(pVM, pVCpu, pMixedCtx);
-        AssertRCReturn(rc, rc);
-
-        rc  = hmR0VmxReadSegmentReg(VMX_VMCS16_GUEST_FIELD_CS, VMX_VMCS32_GUEST_CS_LIMIT, VMX_VMCS_GUEST_CS_BASE,
+
+        rc |= hmR0VmxReadSegmentReg(VMX_VMCS16_GUEST_FIELD_CS, VMX_VMCS32_GUEST_CS_LIMIT, VMX_VMCS_GUEST_CS_BASE,
                                     VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS, &pMixedCtx->cs);
         rc |= hmR0VmxReadSegmentReg(VMX_VMCS16_GUEST_FIELD_SS, VMX_VMCS32_GUEST_SS_LIMIT, VMX_VMCS_GUEST_SS_BASE,
@@ -5180,13 +5173,12 @@
     {
         rc = hmR0VmxSaveGuestCR0(pVM, pVCpu, pMixedCtx);
-        AssertRCReturn(rc, rc);
 
         /* For real-mode emulation using virtual-8086 mode we have the fake TSS (pRealModeTSS) in TR, don't sync the fake one. */
         if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
         {
-            rc  = hmR0VmxReadSegmentReg(VMX_VMCS16_GUEST_FIELD_TR, VMX_VMCS32_GUEST_TR_LIMIT, VMX_VMCS_GUEST_TR_BASE,
+            rc |= hmR0VmxReadSegmentReg(VMX_VMCS16_GUEST_FIELD_TR, VMX_VMCS32_GUEST_TR_LIMIT, VMX_VMCS_GUEST_TR_BASE,
                                         VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, &pMixedCtx->tr);
-            AssertRCReturn(rc, rc);
-        }
+        }
+        AssertRCReturn(rc, rc);
         pVCpu->hm.s.vmx.fUpdatedGuestState |= VMX_UPDATED_GUEST_TR;
     }
@@ -5347,5 +5339,5 @@
         {
             rc = PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
-            AssertRCReturn(rc, rc);
+            AssertRC(rc);
         }
 
@@ -5884,5 +5876,5 @@
  * @param   uValue      The value to push to the guest stack.
  */
-static int hmR0VmxRealModeGuestStackPush(PVM pVM, PCPUMCTX pMixedCtx, uint16_t uValue)
+DECLINLINE(int) hmR0VmxRealModeGuestStackPush(PVM pVM, PCPUMCTX pMixedCtx, uint16_t uValue)
 {
     /*
@@ -6003,10 +5995,8 @@
                 pMixedCtx->cs.Sel      = selIdtEntry;
                 pMixedCtx->cs.u64Base  = selIdtEntry << cbIdtEntry;
-
                 pVCpu->hm.s.fContextUseFlags |=   HM_CHANGED_GUEST_SEGMENT_REGS
                                                 | HM_CHANGED_GUEST_RIP
                                                 | HM_CHANGED_GUEST_RFLAGS
                                                 | HM_CHANGED_GUEST_RSP;
-                AssertRCReturn(rc, rc);
             }
             Assert(rc == VINF_SUCCESS || rc == VINF_EM_RESET);
@@ -6035,5 +6025,4 @@
     rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
     AssertRCReturn(rc, rc);
-
     return rc;
 }
@@ -7198,7 +7187,5 @@
 {
     VMX_VALIDATE_EXIT_HANDLER_PARAMS();
-    int rc = hmR0VmxInjectXcptUD(pVM, pVCpu, pMixedCtx);
-    AssertRCReturn(rc, rc);
-    return rc;
+    return hmR0VmxInjectXcptUD(pVM, pVCpu, pMixedCtx);
 }
 
@@ -7972,5 +7959,5 @@
         /* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
         rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pMixedCtx, true /* include DR6 */);
-        AssertRCReturn(rc, rc);
+        AssertRC(rc);
         Assert(CPUMIsGuestDebugStateActive(pVCpu));
 
@@ -8045,5 +8032,4 @@
     RTGCPHYS GCPhys = 0;
     rc = VMXReadVmcs64(VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL, &GCPhys);
-    AssertRCReturn(rc, rc);
 
 #if 0
@@ -8051,5 +8037,5 @@
 #else
     /* Aggressive state sync. for now. */
-    rc  = hmR0VmxSaveGuestGprs(pVM, pVCpu, pMixedCtx);
+    rc |= hmR0VmxSaveGuestGprs(pVM, pVCpu, pMixedCtx);
     rc |= hmR0VmxSaveGuestControlRegs(pVM, pVCpu, pMixedCtx);
     rc |= hmR0VmxSaveGuestSegmentRegs(pVM, pVCpu, pMixedCtx);