Index: /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 45418)
+++ /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 45419)
@@ -831,7 +831,4 @@
 {
     /* Setup the main VM exit handlers. */
-    /** @todo I'm told lookup table for function pointers is a bad idea in terms
-     *        of performance. Make these static for now and not do change anything
-     *        at runtime so we can easily switch to a switch-case approach later. */
     AssertCompile(VMX_EXIT_MAX + 1 == RT_ELEMENTS(s_apfnVMExitHandlers));
 #ifdef DEBUG
@@ -1141,5 +1138,4 @@
  *
  * @remarks Called with interrupts disabled.
- * @todo Statistics.
  */
 static DECLCALLBACK(void) hmR0VmxFlushTaggedTlbBoth(PVM pVM, PVMCPU pVCpu)
@@ -1259,5 +1255,4 @@
  *
  * @remarks Called with interrupts disabled.
- * @todo Statistics.
  */
 static DECLCALLBACK(void) hmR0VmxFlushTaggedTlbEpt(PVM pVM, PVMCPU pVCpu)
@@ -1326,5 +1321,4 @@
  *
  * @remarks Called with interrupts disabled.
- * @todo Statistics.
  */
 static DECLCALLBACK(void) hmR0VmxFlushTaggedTlbVpid(PVM pVM, PVMCPU pVCpu)
@@ -2742,6 +2736,6 @@
         uint64_t u64CR0Mask = 0;
         u64CR0Mask =  X86_CR0_PE
-                    | X86_CR0_WP    /** @todo do we need to monitor WP with nested paging? */
-                    | X86_CR0_PG    /** @todo do we need to monitor PG with nested paging? */
+                    | X86_CR0_WP
+                    | X86_CR0_PG
                     | X86_CR0_ET    /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.ET */
                     | X86_CR0_CD    /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.CD */
@@ -2932,7 +2926,7 @@
         uint64_t u64CR4Mask = 0;
         u64CR4Mask =  X86_CR4_VME
-                    | X86_CR4_PAE   /** @todo should we intercept this bit with Nested Paging? */
-                    | X86_CR4_PGE   /** @todo why should we care if guest changes PGE bit or not with Nested Paging? */
-                    | X86_CR4_PSE   /** @todo do we care about page-size extensions in the Nested Paging case? */
+                    | X86_CR4_PAE
+                    | X86_CR4_PGE
+                    | X86_CR4_PSE
                     | X86_CR4_VMXE;
         pVCpu->hm.s.vmx.cr4_mask = u64CR4Mask;
@@ -3063,5 +3057,4 @@
             && !CPUMIsGuestInV86ModeEx(pCtx)))
     {
-        /** @todo DPL checks for CS, SS. */
         /* Protected mode checks */
         /* CS */
@@ -3662,5 +3655,4 @@
  *
  * @remarks No-long-jump zone!!!
- * @todo change this to return void.
  */
 DECLINLINE(int) hmR0VmxSetupVMRunHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
@@ -8151,7 +8143,4 @@
 
     Log(("EPT return to ring-3 rc=%d\n"));
-
-    /* We need to go back to ring-3 to emulate the instruction as we could not handle it correctly, tell TRPM. */
-    /** @todo Shouldn't we update TRPM here?  */
     return rc;
 }
@@ -8238,5 +8227,4 @@
     if (rc == VINF_EM_RAW_GUEST_TRAP)
     {
-        /** @todo revisit this.  */
         /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet. See Intel spec. 27.1 "Architectural State before a VM-Exit". */
         pMixedCtx->dr[6] = uDR6;