Changeset 45305 in vbox
- Timestamp:
- Apr 3, 2013 11:15:02 AM (11 years ago)
- Location:
- trunk
- Files:
-
- 20 edited
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include/VBox/vmm/iom.h (modified) (2 diffs)
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src/VBox/Devices/Bus/DevPCI.cpp (modified) (2 diffs)
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src/VBox/Devices/Graphics/DevVGA.cpp (modified) (2 diffs)
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src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h (modified) (2 diffs)
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src/VBox/VMM/VMMAll/IEMAllCImplStrInstr.cpp.h (modified) (8 diffs)
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src/VBox/VMM/VMMAll/IOMAll.cpp (modified) (21 diffs)
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src/VBox/VMM/VMMAll/IOMAllMMIO.cpp (modified) (75 diffs)
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src/VBox/VMM/VMMR0/HWSVMR0.cpp (modified) (4 diffs)
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src/VBox/VMM/VMMR0/HWVMXR0.cpp (modified) (5 diffs)
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src/VBox/VMM/VMMR3/EMHM.cpp (modified) (4 diffs)
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src/VBox/VMM/VMMR3/EMRaw.cpp (modified) (4 diffs)
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src/VBox/VMM/VMMR3/HM.cpp (modified) (2 diffs)
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src/VBox/VMM/VMMR3/IOM.cpp (modified) (11 diffs)
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src/VBox/VMM/VMMRC/IOMRC.cpp (modified) (1 diff)
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src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp (modified) (1 diff)
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src/VBox/VMM/include/IOMInline.h (modified) (5 diffs)
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src/VBox/VMM/include/IOMInternal.h (modified) (2 diffs)
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src/VBox/VMM/testcase/tstVMStruct.h (modified) (1 diff)
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src/recompiler/VBoxREMWrapper.cpp (modified) (5 diffs)
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src/recompiler/VBoxRecompiler.c (modified) (12 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/include/VBox/vmm/iom.h
r45301 r45305 271 271 typedef FNIOMMMIOFILL *PFNIOMMMIOFILL; 272 272 273 VMMDECL(VBOXSTRICTRC) IOMIOPortRead(PVM pVM, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue);274 VMMDECL(VBOXSTRICTRC) IOMIOPortWrite(PVM pVM, RTIOPORT Port, uint32_t u32Value, size_t cbValue);275 VMMDECL(VBOXSTRICTRC) IOMInterpretOUT(PVM pVM, P CPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu);276 VMMDECL(VBOXSTRICTRC) IOMInterpretIN(PVM pVM, P CPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu);277 VMMDECL(VBOXSTRICTRC) IOMIOPortReadString(PVM pVM, RTIOPORT Port, PRTGCPTR pGCPtrDst, PRTGCUINTREG pcTransfers, unsigned cb);278 VMMDECL(VBOXSTRICTRC) IOMIOPortWriteString(PVM pVM, RTIOPORT Port, PRTGCPTR pGCPtrSrc, PRTGCUINTREG pcTransfers, unsigned cb);279 VMMDECL(VBOXSTRICTRC) IOMInterpretINS(PVM pVM, P CPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu);280 VMMDECL(VBOXSTRICTRC) IOMInterpretINSEx(PVM pVM, P CPUMCTXCORE pRegFrame, uint32_t uPort, uint32_t uPrefix, DISCPUMODE enmAddrMode, uint32_t cbTransfer);281 VMMDECL(VBOXSTRICTRC) IOMInterpretOUTS(PVM pVM, P CPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu);282 VMMDECL(VBOXSTRICTRC) IOMInterpretOUTSEx(PVM pVM, P CPUMCTXCORE pRegFrame, uint32_t uPort, uint32_t uPrefix, DISCPUMODE enmAddrMode, uint32_t cbTransfer);283 VMMDECL(VBOXSTRICTRC) IOMMMIORead(PVM pVM, RTGCPHYS GCPhys, uint32_t *pu32Value, size_t cbValue);284 VMMDECL(VBOXSTRICTRC) IOMMMIOWrite(PVM pVM, RTGCPHYS GCPhys, uint32_t u32Value, size_t cbValue);285 VMMDECL(VBOXSTRICTRC) IOMMMIOPhysHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pCtxCore, RTGCPHYS GCPhysFault);273 VMMDECL(VBOXSTRICTRC) IOMIOPortRead(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue); 274 VMMDECL(VBOXSTRICTRC) IOMIOPortWrite(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, uint32_t u32Value, size_t cbValue); 275 VMMDECL(VBOXSTRICTRC) IOMInterpretOUT(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu); 276 VMMDECL(VBOXSTRICTRC) IOMInterpretIN(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu); 277 VMMDECL(VBOXSTRICTRC) IOMIOPortReadString(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, PRTGCPTR pGCPtrDst, PRTGCUINTREG pcTransfers, unsigned cb); 278 VMMDECL(VBOXSTRICTRC) IOMIOPortWriteString(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, PRTGCPTR pGCPtrSrc, PRTGCUINTREG pcTransfers, unsigned cb); 279 VMMDECL(VBOXSTRICTRC) IOMInterpretINS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu); 280 VMMDECL(VBOXSTRICTRC) IOMInterpretINSEx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uPort, uint32_t uPrefix, DISCPUMODE enmAddrMode, uint32_t cbTransfer); 281 VMMDECL(VBOXSTRICTRC) IOMInterpretOUTS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu); 282 VMMDECL(VBOXSTRICTRC) IOMInterpretOUTSEx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uPort, uint32_t uPrefix, DISCPUMODE enmAddrMode, uint32_t cbTransfer); 283 VMMDECL(VBOXSTRICTRC) IOMMMIORead(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, uint32_t *pu32Value, size_t cbValue); 284 VMMDECL(VBOXSTRICTRC) IOMMMIOWrite(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, uint32_t u32Value, size_t cbValue); 285 VMMDECL(VBOXSTRICTRC) IOMMMIOPhysHandler(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pCtxCore, RTGCPHYS GCPhysFault); 286 286 VMMDECL(VBOXSTRICTRC) IOMInterpretCheckPortIOAccess(PVM pVM, PCPUMCTXCORE pCtxCore, RTIOPORT Port, unsigned cb); 287 287 VMMDECL(int) IOMMMIOMapMMIO2Page(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysRemapped, uint64_t fPageFlags); … … 295 295 * @{ 296 296 */ 297 VMMRCDECL(VBOXSTRICTRC) IOMRCIOPortHandler(PVM pVM, P CPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu);297 VMMRCDECL(VBOXSTRICTRC) IOMRCIOPortHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu); 298 298 /** @} */ 299 299 #endif /* IN_RC */ -
trunk/src/VBox/Devices/Bus/DevPCI.cpp
r45025 r45305 1840 1840 { 1841 1841 unsigned i; 1842 uint8_t elcr[2] = {0, 0};1842 uint8_t elcr[2] = {0, 0}; 1843 1843 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS); 1844 PVM pVM = PDMDevHlpGetVM(pDevIns);1845 Assert(pVM);1844 PVM pVM = PDMDevHlpGetVM(pDevIns); Assert(pVM); 1845 PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns); Assert(pVM); 1846 1846 1847 1847 /* … … 1865 1865 1866 1866 /* Tell to the PIC. */ 1867 VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));1867 VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d0, elcr[0], sizeof(uint8_t)); 1868 1868 if (rcStrict == VINF_SUCCESS) 1869 rcStrict = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));1869 rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d1, elcr[1], sizeof(uint8_t)); 1870 1870 if (rcStrict != VINF_SUCCESS) 1871 1871 { -
trunk/src/VBox/Devices/Graphics/DevVGA.cpp
r45055 r45305 1215 1215 /** @todo only allow read access (doesn't work now) */ 1216 1216 STAM_COUNTER_INC(&pThis->StatMapPage); 1217 IOMMMIOMapMMIO2Page(PDMDevHlpGetVM(pThis->CTX_SUFF(pDevIns)), GCPhys, pThis->GCPhysVRAM + addr, X86_PTE_RW|X86_PTE_P); 1217 IOMMMIOMapMMIO2Page(PDMDevHlpGetVM(pThis->CTX_SUFF(pDevIns)), GCPhys, 1218 pThis->GCPhysVRAM + addr, X86_PTE_RW | X86_PTE_P); 1218 1219 /* Set as dirty as write accesses won't be noticed now. */ 1219 1220 vga_set_dirty(pThis, addr); … … 1297 1298 { 1298 1299 STAM_COUNTER_INC(&pThis->StatMapPage); 1299 IOMMMIOMapMMIO2Page(PDMDevHlpGetVM(pThis->CTX_SUFF(pDevIns)), GCPhys, pThis->GCPhysVRAM + addr, X86_PTE_RW | X86_PTE_P); 1300 IOMMMIOMapMMIO2Page(PDMDevHlpGetVM(pThis->CTX_SUFF(pDevIns)), GCPhys, 1301 pThis->GCPhysVRAM + addr, X86_PTE_RW | X86_PTE_P); 1300 1302 pThis->fRemappedVGA = true; 1301 1303 } -
trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h
r42778 r45305 3838 3838 uint32_t u32Value; 3839 3839 if (!IEM_VERIFICATION_ENABLED(pIemCpu)) 3840 rcStrict = IOMIOPortRead(IEMCPU_TO_VM(pIemCpu), u16Port, &u32Value, cbReg);3840 rcStrict = IOMIOPortRead(IEMCPU_TO_VM(pIemCpu), IEMCPU_TO_VMCPU(pIemCpu), u16Port, &u32Value, cbReg); 3841 3841 else 3842 3842 rcStrict = iemVerifyFakeIOPortRead(pIemCpu, u16Port, &u32Value, cbReg); … … 3900 3900 } 3901 3901 if (!IEM_VERIFICATION_ENABLED(pIemCpu)) 3902 rcStrict = IOMIOPortWrite(IEMCPU_TO_VM(pIemCpu), u16Port, u32Value, cbReg);3902 rcStrict = IOMIOPortWrite(IEMCPU_TO_VM(pIemCpu), IEMCPU_TO_VMCPU(pIemCpu), u16Port, u32Value, cbReg); 3903 3903 else 3904 3904 rcStrict = iemVerifyFakeIOPortWrite(pIemCpu, u16Port, u32Value, cbReg); -
trunk/src/VBox/VMM/VMMAll/IEMAllCImplStrInstr.cpp.h
r42761 r45305 1061 1061 uint32_t u32Value; 1062 1062 if (!IEM_VERIFICATION_ENABLED(pIemCpu)) 1063 rcStrict = IOMIOPortRead(pVM, pCtx->dx, &u32Value, OP_SIZE / 8);1063 rcStrict = IOMIOPortRead(pVM, IEMCPU_TO_VMCPU(pIemCpu), pCtx->dx, &u32Value, OP_SIZE / 8); 1064 1064 else 1065 1065 rcStrict = iemVerifyFakeIOPortRead(pIemCpu, pCtx->dx, &u32Value, OP_SIZE / 8); … … 1091 1091 IEM_CIMPL_DEF_0(RT_CONCAT4(iemCImpl_rep_ins_op,OP_SIZE,_addr,ADDR_SIZE)) 1092 1092 { 1093 PVM pVM = IEMCPU_TO_VM(pIemCpu); 1094 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); 1093 PVM pVM = IEMCPU_TO_VM(pIemCpu); 1094 PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu); 1095 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); 1095 1096 1096 1097 /* … … 1173 1174 uint32_t u32Value; 1174 1175 if (!IEM_VERIFICATION_ENABLED(pIemCpu)) 1175 rcStrict = IOMIOPortRead(pVM, u16Port, &u32Value, OP_SIZE / 8);1176 rcStrict = IOMIOPortRead(pVM, pVCpu, u16Port, &u32Value, OP_SIZE / 8); 1176 1177 else 1177 1178 rcStrict = iemVerifyFakeIOPortRead(pIemCpu, u16Port, &u32Value, OP_SIZE / 8); … … 1224 1225 uint32_t u32Value; 1225 1226 if (!IEM_VERIFICATION_ENABLED(pIemCpu)) 1226 rcStrict = IOMIOPortRead(pVM, u16Port, &u32Value, OP_SIZE / 8);1227 rcStrict = IOMIOPortRead(pVM, pVCpu, u16Port, &u32Value, OP_SIZE / 8); 1227 1228 else 1228 1229 rcStrict = iemVerifyFakeIOPortRead(pIemCpu, u16Port, &u32Value, OP_SIZE / 8); … … 1280 1281 { 1281 1282 if (!IEM_VERIFICATION_ENABLED(pIemCpu)) 1282 rcStrict = IOMIOPortWrite(pVM, pCtx->dx, uValue, OP_SIZE / 8);1283 rcStrict = IOMIOPortWrite(pVM, IEMCPU_TO_VMCPU(pIemCpu), pCtx->dx, uValue, OP_SIZE / 8); 1283 1284 else 1284 1285 rcStrict = iemVerifyFakeIOPortWrite(pIemCpu, pCtx->dx, uValue, OP_SIZE / 8); … … 1303 1304 IEM_CIMPL_DEF_1(RT_CONCAT4(iemCImpl_rep_outs_op,OP_SIZE,_addr,ADDR_SIZE), uint8_t, iEffSeg) 1304 1305 { 1305 PVM pVM = IEMCPU_TO_VM(pIemCpu); 1306 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); 1306 PVM pVM = IEMCPU_TO_VM(pIemCpu); 1307 PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu); 1308 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx); 1307 1309 1308 1310 /* … … 1377 1379 uint32_t u32Value = *puMem++; 1378 1380 if (!IEM_VERIFICATION_ENABLED(pIemCpu)) 1379 rcStrict = IOMIOPortWrite(pVM, u16Port, u32Value, OP_SIZE / 8);1381 rcStrict = IOMIOPortWrite(pVM, pVCpu, u16Port, u32Value, OP_SIZE / 8); 1380 1382 else 1381 1383 rcStrict = iemVerifyFakeIOPortWrite(pIemCpu, u16Port, u32Value, OP_SIZE / 8); … … 1426 1428 1427 1429 if (!IEM_VERIFICATION_ENABLED(pIemCpu)) 1428 rcStrict = IOMIOPortWrite(pVM, u16Port, uValue, OP_SIZE / 8);1430 rcStrict = IOMIOPortWrite(pVM, pVCpu, u16Port, uValue, OP_SIZE / 8); 1429 1431 else 1430 1432 rcStrict = iemVerifyFakeIOPortWrite(pIemCpu, u16Port, uValue, OP_SIZE / 8); -
trunk/src/VBox/VMM/VMMAll/IOMAll.cpp
r45301 r45305 220 220 * 221 221 * @param pVM Pointer to the VM. 222 * @param pVCpu Pointer to the virtual CPU structure of the caller. 222 223 * @param Port The port to read. 223 224 * @param pu32Value Where to store the value read. 224 225 * @param cbValue The size of the register to read in bytes. 1, 2 or 4 bytes. 225 226 */ 226 VMMDECL(VBOXSTRICTRC) IOMIOPortRead(PVM pVM, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue)227 VMMDECL(VBOXSTRICTRC) IOMIOPortRead(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue) 227 228 { 228 229 /** @todo should initialize *pu32Value here because it can happen that some … … 243 244 * Get the statistics record. 244 245 */ 245 PIOMIOPORTSTATS pStats = pV M->iom.s.CTX_SUFF(pStatsLastRead);246 PIOMIOPORTSTATS pStats = pVCpu->iom.s.CTX_SUFF(pStatsLastRead); 246 247 if (!pStats || pStats->Core.Key != Port) 247 248 { 248 249 pStats = (PIOMIOPORTSTATS)RTAvloIOPortGet(&pVM->iom.s.CTX_SUFF(pTrees)->IOPortStatTree, Port); 249 250 if (pStats) 250 pV M->iom.s.CTX_SUFF(pStatsLastRead) = pStats;251 pVCpu->iom.s.CTX_SUFF(pStatsLastRead) = pStats; 251 252 } 252 253 #endif … … 255 256 * Get handler for current context. 256 257 */ 257 CTX_SUFF(PIOMIOPORTRANGE) pRange = pV M->iom.s.CTX_SUFF(pRangeLastRead);258 CTX_SUFF(PIOMIOPORTRANGE) pRange = pVCpu->iom.s.CTX_SUFF(pRangeLastRead); 258 259 if ( !pRange 259 260 || (unsigned)Port - (unsigned)pRange->Port >= (unsigned)pRange->cPorts) … … 261 262 pRange = iomIOPortGetRange(pVM, Port); 262 263 if (pRange) 263 pV M->iom.s.CTX_SUFF(pRangeLastRead) = pRange;264 pVCpu->iom.s.CTX_SUFF(pRangeLastRead) = pRange; 264 265 } 265 266 MMHYPER_RC_ASSERT_RCPTR(pVM, pRange); … … 393 394 * 394 395 * @param pVM Pointer to the VM. 396 * @param pVCpu Pointer to the virtual CPU structure of the caller. 395 397 * @param Port The port to read. 396 398 * @param pGCPtrDst Pointer to the destination buffer (GC, incremented appropriately). … … 398 400 * @param cb Size of the transfer unit (1, 2 or 4 bytes). 399 401 */ 400 VMMDECL(VBOXSTRICTRC) IOMIOPortReadString(PVM pVM, RTIOPORT Port, PRTGCPTR pGCPtrDst, PRTGCUINTREG pcTransfers, unsigned cb) 402 VMMDECL(VBOXSTRICTRC) IOMIOPortReadString(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, 403 PRTGCPTR pGCPtrDst, PRTGCUINTREG pcTransfers, unsigned cb) 401 404 { 402 405 /* Take the IOM lock before performing any device I/O. */ … … 418 421 * Get the statistics record. 419 422 */ 420 PIOMIOPORTSTATS pStats = pV M->iom.s.CTX_SUFF(pStatsLastRead);423 PIOMIOPORTSTATS pStats = pVCpu->iom.s.CTX_SUFF(pStatsLastRead); 421 424 if (!pStats || pStats->Core.Key != Port) 422 425 { 423 426 pStats = (PIOMIOPORTSTATS)RTAvloIOPortGet(&pVM->iom.s.CTX_SUFF(pTrees)->IOPortStatTree, Port); 424 427 if (pStats) 425 pV M->iom.s.CTX_SUFF(pStatsLastRead) = pStats;428 pVCpu->iom.s.CTX_SUFF(pStatsLastRead) = pStats; 426 429 } 427 430 #endif … … 430 433 * Get handler for current context. 431 434 */ 432 CTX_SUFF(PIOMIOPORTRANGE) pRange = pV M->iom.s.CTX_SUFF(pRangeLastRead);435 CTX_SUFF(PIOMIOPORTRANGE) pRange = pVCpu->iom.s.CTX_SUFF(pRangeLastRead); 433 436 if ( !pRange 434 437 || (unsigned)Port - (unsigned)pRange->Port >= (unsigned)pRange->cPorts) … … 436 439 pRange = iomIOPortGetRange(pVM, Port); 437 440 if (pRange) 438 pV M->iom.s.CTX_SUFF(pRangeLastRead) = pRange;441 pVCpu->iom.s.CTX_SUFF(pRangeLastRead) = pRange; 439 442 } 440 443 MMHYPER_RC_ASSERT_RCPTR(pVM, pRange); … … 545 548 * 546 549 * @param pVM Pointer to the VM. 550 * @param pVCpu Pointer to the virtual CPU structure of the caller. 547 551 * @param Port The port to write to. 548 552 * @param u32Value The value to write. 549 553 * @param cbValue The size of the register to read in bytes. 1, 2 or 4 bytes. 550 554 */ 551 VMMDECL(VBOXSTRICTRC) IOMIOPortWrite(PVM pVM, RTIOPORT Port, uint32_t u32Value, size_t cbValue)555 VMMDECL(VBOXSTRICTRC) IOMIOPortWrite(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, uint32_t u32Value, size_t cbValue) 552 556 { 553 557 /* Take the IOM lock before performing any device I/O. */ … … 568 572 * Find the statistics record. 569 573 */ 570 PIOMIOPORTSTATS pStats = pV M->iom.s.CTX_SUFF(pStatsLastWrite);574 PIOMIOPORTSTATS pStats = pVCpu->iom.s.CTX_SUFF(pStatsLastWrite); 571 575 if (!pStats || pStats->Core.Key != Port) 572 576 { 573 577 pStats = (PIOMIOPORTSTATS)RTAvloIOPortGet(&pVM->iom.s.CTX_SUFF(pTrees)->IOPortStatTree, Port); 574 578 if (pStats) 575 pV M->iom.s.CTX_SUFF(pStatsLastWrite) = pStats;579 pVCpu->iom.s.CTX_SUFF(pStatsLastWrite) = pStats; 576 580 } 577 581 #endif … … 580 584 * Get handler for current context. 581 585 */ 582 CTX_SUFF(PIOMIOPORTRANGE) pRange = pV M->iom.s.CTX_SUFF(pRangeLastWrite);586 CTX_SUFF(PIOMIOPORTRANGE) pRange = pVCpu->iom.s.CTX_SUFF(pRangeLastWrite); 583 587 if ( !pRange 584 588 || (unsigned)Port - (unsigned)pRange->Port >= (unsigned)pRange->cPorts) … … 586 590 pRange = iomIOPortGetRange(pVM, Port); 587 591 if (pRange) 588 pV M->iom.s.CTX_SUFF(pRangeLastWrite) = pRange;592 pVCpu->iom.s.CTX_SUFF(pRangeLastWrite) = pRange; 589 593 } 590 594 MMHYPER_RC_ASSERT_RCPTR(pVM, pRange); … … 693 697 * 694 698 * @param pVM Pointer to the VM. 699 * @param pVCpu Pointer to the virtual CPU structure of the caller. 695 700 * @param Port The port to write. 696 701 * @param pGCPtrSrc Pointer to the source buffer (GC, incremented appropriately). 697 702 * @param pcTransfers Pointer to the number of transfer units to write, on return remaining transfer units. 698 703 * @param cb Size of the transfer unit (1, 2 or 4 bytes). 699 * */ 700 VMMDECL(VBOXSTRICTRC) IOMIOPortWriteString(PVM pVM, RTIOPORT Port, PRTGCPTR pGCPtrSrc, PRTGCUINTREG pcTransfers, unsigned cb) 704 */ 705 VMMDECL(VBOXSTRICTRC) IOMIOPortWriteString(PVM pVM, PVMCPU pVCpu, RTIOPORT Port, 706 PRTGCPTR pGCPtrSrc, PRTGCUINTREG pcTransfers, unsigned cb) 701 707 { 702 708 /* Take the IOM lock before performing any device I/O. */ … … 718 724 * Get the statistics record. 719 725 */ 720 PIOMIOPORTSTATS pStats = pV M->iom.s.CTX_SUFF(pStatsLastWrite);726 PIOMIOPORTSTATS pStats = pVCpu->iom.s.CTX_SUFF(pStatsLastWrite); 721 727 if (!pStats || pStats->Core.Key != Port) 722 728 { 723 729 pStats = (PIOMIOPORTSTATS)RTAvloIOPortGet(&pVM->iom.s.CTX_SUFF(pTrees)->IOPortStatTree, Port); 724 730 if (pStats) 725 pV M->iom.s.CTX_SUFF(pStatsLastWrite) = pStats;731 pVCpu->iom.s.CTX_SUFF(pStatsLastWrite) = pStats; 726 732 } 727 733 #endif … … 730 736 * Get handler for current context. 731 737 */ 732 CTX_SUFF(PIOMIOPORTRANGE) pRange = pV M->iom.s.CTX_SUFF(pRangeLastWrite);738 CTX_SUFF(PIOMIOPORTRANGE) pRange = pVCpu->iom.s.CTX_SUFF(pRangeLastWrite); 733 739 if ( !pRange 734 740 || (unsigned)Port - (unsigned)pRange->Port >= (unsigned)pRange->cPorts) … … 736 742 pRange = iomIOPortGetRange(pVM, Port); 737 743 if (pRange) 738 pV M->iom.s.CTX_SUFF(pRangeLastWrite) = pRange;744 pVCpu->iom.s.CTX_SUFF(pRangeLastWrite) = pRange; 739 745 } 740 746 MMHYPER_RC_ASSERT_RCPTR(pVM, pRange); … … 947 953 * 948 954 * @param pVM The virtual machine (GC pointer of course). 955 * @param pVCpu Pointer to the virtual CPU structure of the caller. 949 956 * @param pRegFrame Pointer to CPUMCTXCORE guest registers structure. 950 957 * @param pCpu Disassembler CPU state. 951 958 */ 952 VMMDECL(VBOXSTRICTRC) IOMInterpretIN(PVM pVM, P CPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu)959 VMMDECL(VBOXSTRICTRC) IOMInterpretIN(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu) 953 960 { 954 961 #ifdef IN_RC … … 974 981 */ 975 982 uint32_t u32Data = UINT32_C(0xffffffff); 976 rcStrict = IOMIOPortRead(pVM, uPort, &u32Data, cbSize);983 rcStrict = IOMIOPortRead(pVM, pVCpu, uPort, &u32Data, cbSize); 977 984 if (IOM_SUCCESS(rcStrict)) 978 985 { … … 1007 1014 * 1008 1015 * @param pVM The virtual machine (GC pointer of course). 1016 * @param pVCpu Pointer to the virtual CPU structure of the caller. 1009 1017 * @param pRegFrame Pointer to CPUMCTXCORE guest registers structure. 1010 1018 * @param pCpu Disassembler CPU state. 1011 1019 */ 1012 VMMDECL(VBOXSTRICTRC) IOMInterpretOUT(PVM pVM, P CPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu)1020 VMMDECL(VBOXSTRICTRC) IOMInterpretOUT(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu) 1013 1021 { 1014 1022 #ifdef IN_RC … … 1035 1043 * Attempt to write to the port. 1036 1044 */ 1037 rcStrict = IOMIOPortWrite(pVM, uPort, u64Data, cbSize);1045 rcStrict = IOMIOPortWrite(pVM, pVCpu, uPort, u64Data, cbSize); 1038 1046 AssertMsg(rcStrict == VINF_SUCCESS || rcStrict == VINF_IOM_R3_IOPORT_WRITE || (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST) || RT_FAILURE(rcStrict), ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); 1039 1047 } -
trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp
r44715 r45305 274 274 * @warning RT_SUCCESS(rc=VINF_IOM_R3_MMIO_WRITE) is TRUE! 275 275 */ 276 static int iomMMIODoWrite(PVM pVM, P IOMMMIORANGE pRange, RTGCPHYS GCPhysFault, const void *pvData, unsigned cb)276 static int iomMMIODoWrite(PVM pVM, PVMCPU pVCpu, PIOMMMIORANGE pRange, RTGCPHYS GCPhysFault, const void *pvData, unsigned cb) 277 277 { 278 278 #ifdef VBOX_WITH_STATISTICS 279 PIOMMMIOSTATS pStats = iomMmioGetStats(pVM, GCPhysFault, pRange);279 PIOMMMIOSTATS pStats = iomMmioGetStats(pVM, pVCpu, GCPhysFault, pRange); 280 280 Assert(pStats); 281 281 #endif … … 481 481 * Wrapper which does the read and updates range statistics when such are enabled. 482 482 */ 483 DECLINLINE(int) iomMMIODoRead(PVM pVM, P IOMMMIORANGE pRange, RTGCPHYS GCPhys, void *pvValue, unsigned cbValue)483 DECLINLINE(int) iomMMIODoRead(PVM pVM, PVMCPU pVCpu, PIOMMMIORANGE pRange, RTGCPHYS GCPhys, void *pvValue, unsigned cbValue) 484 484 { 485 485 #ifdef VBOX_WITH_STATISTICS 486 PIOMMMIOSTATS pStats = iomMmioGetStats(pVM, GCPhys, pRange);486 PIOMMMIOSTATS pStats = iomMmioGetStats(pVM, pVCpu, GCPhys, pRange); 487 487 Assert(pStats); 488 488 STAM_PROFILE_START(&pStats->CTX_SUFF_Z(ProfRead), a); … … 557 557 * 558 558 * @param pVM The virtual machine. 559 * @param pVCpu Pointer to the virtual CPU structure of the caller. 559 560 * @param pRegFrame Pointer to CPUMCTXCORE guest registers structure. 560 561 * @param pCpu Disassembler CPU state. … … 562 563 * @param GCPhysFault The GC physical address corresponding to pvFault. 563 564 */ 564 static int iomInterpretMOVxXRead(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange, RTGCPHYS GCPhysFault) 565 static int iomInterpretMOVxXRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, 566 PIOMMMIORANGE pRange, RTGCPHYS GCPhysFault) 565 567 { 566 568 Assert(pRange->CTX_SUFF(pfnReadCallback) || !pRange->pfnReadCallbackR3); … … 574 576 575 577 uint64_t u64Data = 0; 576 int rc = iomMMIODoRead(pVM, p Range, GCPhysFault, &u64Data, cb);578 int rc = iomMMIODoRead(pVM, pVCpu, pRange, GCPhysFault, &u64Data, cb); 577 579 if (rc == VINF_SUCCESS) 578 580 { … … 616 618 * 617 619 * @param pVM The virtual machine. 620 * @param pVCpu Pointer to the virtual CPU structure of the caller. 618 621 * @param pRegFrame Pointer to CPUMCTXCORE guest registers structure. 619 622 * @param pCpu Disassembler CPU state. … … 621 624 * @param GCPhysFault The GC physical address corresponding to pvFault. 622 625 */ 623 static int iomInterpretMOVxXWrite(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange, RTGCPHYS GCPhysFault) 626 static int iomInterpretMOVxXWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, 627 PIOMMMIORANGE pRange, RTGCPHYS GCPhysFault) 624 628 { 625 629 Assert(pRange->CTX_SUFF(pfnWriteCallback) || !pRange->pfnWriteCallbackR3); … … 634 638 AssertMsg(fRc, ("Failed to get reg/imm port number!\n")); NOREF(fRc); 635 639 636 int rc = iomMMIODoWrite(pVM, p Range, GCPhysFault, &u64Data, cb);640 int rc = iomMMIODoWrite(pVM, pVCpu, pRange, GCPhysFault, &u64Data, cb); 637 641 if (rc == VINF_SUCCESS) 638 642 iomMMIOStatLength(pVM, cb); … … 950 954 * 951 955 * @param pVM The virtual machine. 956 * @param pVCpu Pointer to the virtual CPU structure of the caller. 952 957 * @param pRegFrame Trap register frame. 953 958 * @param GCPhysFault The GC physical address corresponding to pvFault. … … 955 960 * @param pRange Pointer MMIO range. 956 961 */ 957 static int iomInterpretSTOS(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) 962 static int iomInterpretSTOS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, 963 PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) 958 964 { 959 965 /* … … 1046 1052 do 1047 1053 { 1048 rc = iomMMIODoWrite(pVM, p Range, Phys, &u64Data, cb);1054 rc = iomMMIODoWrite(pVM, pVCpu, pRange, Phys, &u64Data, cb); 1049 1055 if (rc != VINF_SUCCESS) 1050 1056 break; … … 1082 1088 * 1083 1089 * @param pVM The virtual machine. 1090 * @param pVCpu Pointer to the virtual CPU structure of the caller. 1084 1091 * @param pRegFrame Trap register frame. 1085 1092 * @param GCPhysFault The GC physical address corresponding to pvFault. … … 1087 1094 * @param pRange Pointer MMIO range. 1088 1095 */ 1089 static int iomInterpretLODS(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) 1096 static int iomInterpretLODS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, 1097 PIOMMMIORANGE pRange) 1090 1098 { 1091 1099 Assert(pRange->CTX_SUFF(pfnReadCallback) || !pRange->pfnReadCallbackR3); … … 1107 1115 * Perform read. 1108 1116 */ 1109 int rc = iomMMIODoRead(pVM, p Range, GCPhysFault, &pRegFrame->rax, cb);1117 int rc = iomMMIODoRead(pVM, pVCpu, pRange, GCPhysFault, &pRegFrame->rax, cb); 1110 1118 if (rc == VINF_SUCCESS) 1111 1119 { … … 1139 1147 * @param pRange Pointer MMIO range. 1140 1148 */ 1141 static int iomInterpretCMP(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) 1149 static int iomInterpretCMP(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, 1150 PIOMMMIORANGE pRange) 1142 1151 { 1143 1152 Assert(pRange->CTX_SUFF(pfnReadCallback) || !pRange->pfnReadCallbackR3); … … 1152 1161 if (iomGetRegImmData(pCpu, &pCpu->Param1, pRegFrame, &uData1, &cb)) 1153 1162 /* cmp reg, [MMIO]. */ 1154 rc = iomMMIODoRead(pVM, p Range, GCPhysFault, &uData2, cb);1163 rc = iomMMIODoRead(pVM, pVCpu, pRange, GCPhysFault, &uData2, cb); 1155 1164 else if (iomGetRegImmData(pCpu, &pCpu->Param2, pRegFrame, &uData2, &cb)) 1156 1165 /* cmp [MMIO], reg|imm. */ 1157 rc = iomMMIODoRead(pVM, p Range, GCPhysFault, &uData1, cb);1166 rc = iomMMIODoRead(pVM, pVCpu, pRange, GCPhysFault, &uData1, cb); 1158 1167 else 1159 1168 { … … 1192 1201 * 1193 1202 * @param pVM The virtual machine. 1203 * @param pVCpu Pointer to the virtual CPU structure of the caller. 1194 1204 * @param pRegFrame Trap register frame. 1195 1205 * @param GCPhysFault The GC physical address corresponding to pvFault. … … 1198 1208 * @param pfnEmulate Instruction emulation function. 1199 1209 */ 1200 static int iomInterpretOrXorAnd(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange, PFNEMULATEPARAM3 pfnEmulate) 1210 static int iomInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, 1211 PIOMMMIORANGE pRange, PFNEMULATEPARAM3 pfnEmulate) 1201 1212 { 1202 1213 unsigned cb = 0; … … 1229 1240 Assert(pRange->CTX_SUFF(pfnReadCallback) || !pRange->pfnReadCallbackR3); 1230 1241 fAndWrite = false; 1231 rc = iomMMIODoRead(pVM, p Range, GCPhysFault, &uData2, cb);1242 rc = iomMMIODoRead(pVM, pVCpu, pRange, GCPhysFault, &uData2, cb); 1232 1243 } 1233 1244 else if (iomGetRegImmData(pCpu, &pCpu->Param2, pRegFrame, &uData2, &cb)) … … 1242 1253 if ( (pRange->CTX_SUFF(pfnReadCallback) || !pRange->pfnReadCallbackR3) 1243 1254 && (pRange->CTX_SUFF(pfnWriteCallback) || !pRange->pfnWriteCallbackR3)) 1244 rc = iomMMIODoRead(pVM, p Range, GCPhysFault, &uData1, cb);1255 rc = iomMMIODoRead(pVM, pVCpu, pRange, GCPhysFault, &uData1, cb); 1245 1256 else 1246 1257 rc = VINF_IOM_R3_MMIO_READ_WRITE; … … 1261 1272 if (fAndWrite) 1262 1273 /* Store result to MMIO. */ 1263 rc = iomMMIODoWrite(pVM, p Range, GCPhysFault, &uData1, cb);1274 rc = iomMMIODoWrite(pVM, pVCpu, pRange, GCPhysFault, &uData1, cb); 1264 1275 else 1265 1276 { … … 1291 1302 * 1292 1303 * @param pVM The virtual machine. 1304 * @param pVCpu Pointer to the virtual CPU structure of the caller. 1293 1305 * @param pRegFrame Trap register frame. 1294 1306 * @param GCPhysFault The GC physical address corresponding to pvFault. … … 1296 1308 * @param pRange Pointer MMIO range. 1297 1309 */ 1298 static int iomInterpretTEST(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) 1310 static int iomInterpretTEST(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, 1311 PIOMMMIORANGE pRange) 1299 1312 { 1300 1313 Assert(pRange->CTX_SUFF(pfnReadCallback) || !pRange->pfnReadCallbackR3); … … 1308 1321 { 1309 1322 /* and test, [MMIO]. */ 1310 rc = iomMMIODoRead(pVM, p Range, GCPhysFault, &uData2, cb);1323 rc = iomMMIODoRead(pVM, pVCpu, pRange, GCPhysFault, &uData2, cb); 1311 1324 } 1312 1325 else if (iomGetRegImmData(pCpu, &pCpu->Param2, pRegFrame, &uData2, &cb)) 1313 1326 { 1314 1327 /* test [MMIO], reg|imm. */ 1315 rc = iomMMIODoRead(pVM, p Range, GCPhysFault, &uData1, cb);1328 rc = iomMMIODoRead(pVM, pVCpu, pRange, GCPhysFault, &uData1, cb); 1316 1329 } 1317 1330 else … … 1349 1362 * 1350 1363 * @param pVM The virtual machine. 1364 * @param pVCpu Pointer to the virtual CPU structure of the caller. 1351 1365 * @param pRegFrame Trap register frame. 1352 1366 * @param GCPhysFault The GC physical address corresponding to pvFault. … … 1354 1368 * @param pRange Pointer MMIO range. 1355 1369 */ 1356 static int iomInterpretBT(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) 1370 static int iomInterpretBT(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, 1371 PIOMMMIORANGE pRange) 1357 1372 { 1358 1373 Assert(pRange->CTX_SUFF(pfnReadCallback) || !pRange->pfnReadCallbackR3); … … 1371 1386 1372 1387 /* bt [MMIO], reg|imm. */ 1373 int rc = iomMMIODoRead(pVM, p Range, GCPhysFault, &uData, cbData);1388 int rc = iomMMIODoRead(pVM, pVCpu, pRange, GCPhysFault, &uData, cbData); 1374 1389 if (rc == VINF_SUCCESS) 1375 1390 { … … 1392 1407 * 1393 1408 * @param pVM The virtual machine. 1409 * @param pVCpu Pointer to the virtual CPU structure of the caller. 1394 1410 * @param pRegFrame Trap register frame. 1395 1411 * @param GCPhysFault The GC physical address corresponding to pvFault. … … 1397 1413 * @param pRange Pointer MMIO range. 1398 1414 */ 1399 static int iomInterpretXCHG(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange) 1415 static int iomInterpretXCHG(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, 1416 PIOMMMIORANGE pRange) 1400 1417 { 1401 1418 /* Check for read & write handlers since IOMMMIOHandler doesn't cover this. */ … … 1411 1428 { 1412 1429 /* xchg reg, [MMIO]. */ 1413 rc = iomMMIODoRead(pVM, p Range, GCPhysFault, &uData2, cb);1430 rc = iomMMIODoRead(pVM, pVCpu, pRange, GCPhysFault, &uData2, cb); 1414 1431 if (rc == VINF_SUCCESS) 1415 1432 { 1416 1433 /* Store result to MMIO. */ 1417 rc = iomMMIODoWrite(pVM, p Range, GCPhysFault, &uData1, cb);1434 rc = iomMMIODoWrite(pVM, pVCpu, pRange, GCPhysFault, &uData1, cb); 1418 1435 1419 1436 if (rc == VINF_SUCCESS) … … 1432 1449 { 1433 1450 /* xchg [MMIO], reg. */ 1434 rc = iomMMIODoRead(pVM, p Range, GCPhysFault, &uData1, cb);1451 rc = iomMMIODoRead(pVM, pVCpu, pRange, GCPhysFault, &uData1, cb); 1435 1452 if (rc == VINF_SUCCESS) 1436 1453 { 1437 1454 /* Store result to MMIO. */ 1438 rc = iomMMIODoWrite(pVM, p Range, GCPhysFault, &uData2, cb);1455 rc = iomMMIODoWrite(pVM, pVCpu, pRange, GCPhysFault, &uData2, cb); 1439 1456 if (rc == VINF_SUCCESS) 1440 1457 { … … 1463 1480 * @returns VBox status code (appropriate for GC return). 1464 1481 * @param pVM Pointer to the VM. 1482 * @param pVCpu Pointer to the virtual CPU structure of the caller. 1465 1483 * @param uErrorCode CPU Error code. This is UINT32_MAX when we don't have 1466 1484 * any error code (the EPT misconfig hack). … … 1469 1487 * @param pvUser Pointer to the MMIO ring-3 range entry. 1470 1488 */ 1471 static int iomMMIOHandler(PVM pVM, uint32_t uErrorCode, PCPUMCTXCORE pCtxCore, RTGCPHYS GCPhysFault, void *pvUser) 1472 { 1473 /* Take the IOM lock before performing any MMIO. */ 1489 static int iomMMIOHandler(PVM pVM, PVMCPU pVCpu, uint32_t uErrorCode, PCPUMCTXCORE pCtxCore, RTGCPHYS GCPhysFault, void *pvUser) 1490 { 1474 1491 int rc = IOM_LOCK(pVM); 1475 1492 #ifndef IN_RING3 … … 1480 1497 1481 1498 STAM_PROFILE_START(&pVM->iom.s.StatRZMMIOHandler, a); 1482 Log(("iomMMIOHandler: GCPhys=%RGp uErr=%#x rip=%RGv\n", 1483 GCPhysFault, uErrorCode, (RTGCPTR)pCtxCore->rip)); 1499 Log(("iomMMIOHandler: GCPhys=%RGp uErr=%#x rip=%RGv\n", GCPhysFault, uErrorCode, (RTGCPTR)pCtxCore->rip)); 1484 1500 1485 1501 PIOMMMIORANGE pRange = (PIOMMMIORANGE)pvUser; 1486 1502 Assert(pRange); 1487 Assert(pRange == iomMmioGetRange(pVM, GCPhysFault));1503 Assert(pRange == iomMmioGetRange(pVM, pVCpu, GCPhysFault)); 1488 1504 1489 1505 #ifdef VBOX_WITH_STATISTICS … … 1491 1507 * Locate the statistics, if > PAGE_SIZE we'll use the first byte for everything. 1492 1508 */ 1493 PIOMMMIOSTATS pStats = iomMmioGetStats(pVM, GCPhysFault, pRange);1509 PIOMMMIOSTATS pStats = iomMmioGetStats(pVM, pVCpu, GCPhysFault, pRange); 1494 1510 if (!pStats) 1495 1511 { … … 1550 1566 * Disassemble the instruction and interpret it. 1551 1567 */ 1552 PVMCPU pVCpu = VMMGetCpu(pVM);1553 1568 PDISCPUSTATE pDis = &pVCpu->iom.s.DisState; 1554 1569 unsigned cbOp; … … 1571 1586 ? uErrorCode & X86_TRAP_PF_RW 1572 1587 : DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)) 1573 rc = iomInterpretMOVxXWrite(pVM, p CtxCore, pDis, pRange, GCPhysFault);1588 rc = iomInterpretMOVxXWrite(pVM, pVCpu, pCtxCore, pDis, pRange, GCPhysFault); 1574 1589 else 1575 rc = iomInterpretMOVxXRead(pVM, p CtxCore, pDis, pRange, GCPhysFault);1590 rc = iomInterpretMOVxXRead(pVM, pVCpu, pCtxCore, pDis, pRange, GCPhysFault); 1576 1591 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstMov, b); 1577 1592 break; … … 1600 1615 Assert(uErrorCode & X86_TRAP_PF_RW); 1601 1616 STAM_PROFILE_START(&pVM->iom.s.StatRZInstStos, d); 1602 rc = iomInterpretSTOS(pVM, p CtxCore, GCPhysFault, pDis, pRange);1617 rc = iomInterpretSTOS(pVM, pVCpu, pCtxCore, GCPhysFault, pDis, pRange); 1603 1618 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstStos, d); 1604 1619 break; … … 1608 1623 Assert(!(uErrorCode & X86_TRAP_PF_RW) || uErrorCode == UINT32_MAX); 1609 1624 STAM_PROFILE_START(&pVM->iom.s.StatRZInstLods, e); 1610 rc = iomInterpretLODS(pVM, p CtxCore, GCPhysFault, pDis, pRange);1625 rc = iomInterpretLODS(pVM, pVCpu, pCtxCore, GCPhysFault, pDis, pRange); 1611 1626 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstLods, e); 1612 1627 break; … … 1615 1630 Assert(!(uErrorCode & X86_TRAP_PF_RW) || uErrorCode == UINT32_MAX); 1616 1631 STAM_PROFILE_START(&pVM->iom.s.StatRZInstCmp, f); 1617 rc = iomInterpretCMP(pVM, p CtxCore, GCPhysFault, pDis, pRange);1632 rc = iomInterpretCMP(pVM, pVCpu, pCtxCore, GCPhysFault, pDis, pRange); 1618 1633 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstCmp, f); 1619 1634 break; … … 1621 1636 case OP_AND: 1622 1637 STAM_PROFILE_START(&pVM->iom.s.StatRZInstAnd, g); 1623 rc = iomInterpretOrXorAnd(pVM, p CtxCore, GCPhysFault, pDis, pRange, EMEmulateAnd);1638 rc = iomInterpretOrXorAnd(pVM, pVCpu, pCtxCore, GCPhysFault, pDis, pRange, EMEmulateAnd); 1624 1639 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstAnd, g); 1625 1640 break; … … 1627 1642 case OP_OR: 1628 1643 STAM_PROFILE_START(&pVM->iom.s.StatRZInstOr, k); 1629 rc = iomInterpretOrXorAnd(pVM, p CtxCore, GCPhysFault, pDis, pRange, EMEmulateOr);1644 rc = iomInterpretOrXorAnd(pVM, pVCpu, pCtxCore, GCPhysFault, pDis, pRange, EMEmulateOr); 1630 1645 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstOr, k); 1631 1646 break; … … 1633 1648 case OP_XOR: 1634 1649 STAM_PROFILE_START(&pVM->iom.s.StatRZInstXor, m); 1635 rc = iomInterpretOrXorAnd(pVM, p CtxCore, GCPhysFault, pDis, pRange, EMEmulateXor);1650 rc = iomInterpretOrXorAnd(pVM, pVCpu, pCtxCore, GCPhysFault, pDis, pRange, EMEmulateXor); 1636 1651 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstXor, m); 1637 1652 break; … … 1640 1655 Assert(!(uErrorCode & X86_TRAP_PF_RW) || uErrorCode == UINT32_MAX); 1641 1656 STAM_PROFILE_START(&pVM->iom.s.StatRZInstTest, h); 1642 rc = iomInterpretTEST(pVM, p CtxCore, GCPhysFault, pDis, pRange);1657 rc = iomInterpretTEST(pVM, pVCpu, pCtxCore, GCPhysFault, pDis, pRange); 1643 1658 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstTest, h); 1644 1659 break; … … 1647 1662 Assert(!(uErrorCode & X86_TRAP_PF_RW) || uErrorCode == UINT32_MAX); 1648 1663 STAM_PROFILE_START(&pVM->iom.s.StatRZInstBt, l); 1649 rc = iomInterpretBT(pVM, p CtxCore, GCPhysFault, pDis, pRange);1664 rc = iomInterpretBT(pVM, pVCpu, pCtxCore, GCPhysFault, pDis, pRange); 1650 1665 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstBt, l); 1651 1666 break; … … 1653 1668 case OP_XCHG: 1654 1669 STAM_PROFILE_START(&pVM->iom.s.StatRZInstXchg, i); 1655 rc = iomInterpretXCHG(pVM, p CtxCore, GCPhysFault, pDis, pRange);1670 rc = iomInterpretXCHG(pVM, pVCpu, pCtxCore, GCPhysFault, pDis, pRange); 1656 1671 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstXchg, i); 1657 1672 break; … … 1710 1725 LogFlow(("IOMMMIOHandler: GCPhys=%RGp uErr=%#x pvFault=%RGv rip=%RGv\n", 1711 1726 GCPhysFault, (uint32_t)uErrorCode, pvFault, (RTGCPTR)pCtxCore->rip)); 1712 VBOXSTRICTRC rcStrict = iomMMIOHandler(pVM, (uint32_t)uErrorCode, pCtxCore, GCPhysFault, pvUser);1727 VBOXSTRICTRC rcStrict = iomMMIOHandler(pVM, VMMGetCpu(pVM), (uint32_t)uErrorCode, pCtxCore, GCPhysFault, pvUser); 1713 1728 return VBOXSTRICTRC_VAL(rcStrict); 1714 1729 } … … 1719 1734 * @returns VBox status code (appropriate for GC return). 1720 1735 * @param pVM Pointer to the VM. 1736 * @param pVCpu Pointer to the virtual CPU structure of the caller. 1721 1737 * @param uErrorCode CPU Error code. 1722 1738 * @param pCtxCore Trap register frame. 1723 1739 * @param GCPhysFault The GC physical address. 1724 1740 */ 1725 VMMDECL(VBOXSTRICTRC) IOMMMIOPhysHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pCtxCore, RTGCPHYS GCPhysFault)1741 VMMDECL(VBOXSTRICTRC) IOMMMIOPhysHandler(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pCtxCore, RTGCPHYS GCPhysFault) 1726 1742 { 1727 1743 int rc2 = IOM_LOCK(pVM); NOREF(rc2); … … 1730 1746 return VINF_IOM_R3_MMIO_READ_WRITE; 1731 1747 #endif 1732 VBOXSTRICTRC rcStrict = iomMMIOHandler(pVM, (uint32_t)uErrorCode, pCtxCore, GCPhysFault, iomMmioGetRange(pVM, GCPhysFault)); 1748 VBOXSTRICTRC rcStrict = iomMMIOHandler(pVM, pVCpu, (uint32_t)uErrorCode, pCtxCore, GCPhysFault, 1749 iomMmioGetRange(pVM, pVCpu, GCPhysFault)); 1733 1750 IOM_UNLOCK(pVM); 1734 1751 return VBOXSTRICTRC_VAL(rcStrict); … … 1753 1770 PGMACCESSTYPE enmAccessType, void *pvUser) 1754 1771 { 1772 PVMCPU pVCpu = VMMGetCpu(pVM); 1755 1773 PIOMMMIORANGE pRange = (PIOMMMIORANGE)pvUser; 1756 1774 STAM_COUNTER_INC(&pVM->iom.s.StatR3MMIOHandler); … … 1765 1783 int rc = IOM_LOCK(pVM); 1766 1784 AssertRC(rc); 1767 Assert(pRange == iomMmioGetRange(pVM, GCPhysFault));1785 Assert(pRange == iomMmioGetRange(pVM, pVCpu, GCPhysFault)); 1768 1786 1769 1787 /* … … 1784 1802 */ 1785 1803 if (enmAccessType == PGMACCESSTYPE_READ) 1786 rc = iomMMIODoRead(pVM, p Range, GCPhysFault, pvBuf, (unsigned)cbBuf);1804 rc = iomMMIODoRead(pVM, pVCpu, pRange, GCPhysFault, pvBuf, (unsigned)cbBuf); 1787 1805 else 1788 rc = iomMMIODoWrite(pVM, p Range, GCPhysFault, pvBuf, (unsigned)cbBuf);1806 rc = iomMMIODoWrite(pVM, pVCpu, pRange, GCPhysFault, pvBuf, (unsigned)cbBuf); 1789 1807 1790 1808 AssertRC(rc); … … 1802 1820 * 1803 1821 * @param pVM Pointer to the VM. 1822 * @param pVCpu Pointer to the virtual CPU structure of the caller. 1804 1823 * @param GCPhys The physical address to read. 1805 1824 * @param pu32Value Where to store the value read. 1806 1825 * @param cbValue The size of the register to read in bytes. 1, 2 or 4 bytes. 1807 1826 */ 1808 VMMDECL(VBOXSTRICTRC) IOMMMIORead(PVM pVM, RTGCPHYS GCPhys, uint32_t *pu32Value, size_t cbValue)1827 VMMDECL(VBOXSTRICTRC) IOMMMIORead(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, uint32_t *pu32Value, size_t cbValue) 1809 1828 { 1810 1829 /* Take the IOM lock before performing any MMIO. */ … … 1822 1841 * Lookup the current context range node and statistics. 1823 1842 */ 1824 PIOMMMIORANGE pRange = iomMmioGetRange(pVM, GCPhys);1843 PIOMMMIORANGE pRange = iomMmioGetRange(pVM, pVCpu, GCPhys); 1825 1844 if (!pRange) 1826 1845 { … … 1830 1849 } 1831 1850 #ifdef VBOX_WITH_STATISTICS 1832 PIOMMMIOSTATS pStats = iomMmioGetStats(pVM, GCPhys, pRange);1851 PIOMMMIOSTATS pStats = iomMmioGetStats(pVM, pVCpu, GCPhys, pRange); 1833 1852 if (!pStats) 1834 1853 { … … 1931 1950 * 1932 1951 * @param pVM Pointer to the VM. 1952 * @param pVCpu Pointer to the virtual CPU structure of the caller. 1933 1953 * @param GCPhys The physical address to write to. 1934 1954 * @param u32Value The value to write. 1935 1955 * @param cbValue The size of the register to read in bytes. 1, 2 or 4 bytes. 1936 1956 */ 1937 VMMDECL(VBOXSTRICTRC) IOMMMIOWrite(PVM pVM, RTGCPHYS GCPhys, uint32_t u32Value, size_t cbValue)1957 VMMDECL(VBOXSTRICTRC) IOMMMIOWrite(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, uint32_t u32Value, size_t cbValue) 1938 1958 { 1939 1959 /* Take the IOM lock before performing any MMIO. */ … … 1951 1971 * Lookup the current context range node. 1952 1972 */ 1953 PIOMMMIORANGE pRange = iomMmioGetRange(pVM, GCPhys);1973 PIOMMMIORANGE pRange = iomMmioGetRange(pVM, pVCpu, GCPhys); 1954 1974 if (!pRange) 1955 1975 { … … 1959 1979 } 1960 1980 #ifdef VBOX_WITH_STATISTICS 1961 PIOMMMIOSTATS pStats = iomMmioGetStats(pVM, GCPhys, pRange);1981 PIOMMMIOSTATS pStats = iomMmioGetStats(pVM, pVCpu, GCPhys, pRange); 1962 1982 if (!pStats) 1963 1983 { … … 2047 2067 * 2048 2068 * @param pVM The virtual machine. 2069 * @param pVCpu Pointer to the virtual CPU structure of the caller. 2049 2070 * @param pRegFrame Pointer to CPUMCTXCORE guest registers structure. 2050 2071 * @param uPort IO Port … … 2053 2074 * @param cbTransfer Size of transfer unit 2054 2075 */ 2055 VMMDECL(VBOXSTRICTRC) IOMInterpretINSEx(PVM pVM, P CPUMCTXCORE pRegFrame, uint32_t uPort, uint32_t uPrefix,2076 VMMDECL(VBOXSTRICTRC) IOMInterpretINSEx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uPort, uint32_t uPrefix, 2056 2077 DISCPUMODE enmAddrMode, uint32_t cbTransfer) 2057 2078 { … … 2065 2086 || pRegFrame->eflags.Bits.u1DF) 2066 2087 return VINF_EM_RAW_EMULATE_INSTR; 2067 2068 PVMCPU pVCpu = VMMGetCpu(pVM);2069 2088 2070 2089 /* … … 2113 2132 * much as it wants. The rest is done with single-word transfers. */ 2114 2133 const RTGCUINTREG cTransfersOrg = cTransfers; 2115 rcStrict = IOMIOPortReadString(pVM, uPort, &GCPtrDst, &cTransfers, cbTransfer);2134 rcStrict = IOMIOPortReadString(pVM, pVCpu, uPort, &GCPtrDst, &cTransfers, cbTransfer); 2116 2135 AssertRC(VBOXSTRICTRC_VAL(rcStrict)); Assert(cTransfers <= cTransfersOrg); 2117 2136 pRegFrame->rdi = ((pRegFrame->rdi + (cTransfersOrg - cTransfers) * cbTransfer) & fAddrMask) … … 2125 2144 { 2126 2145 uint32_t u32Value; 2127 rcStrict = IOMIOPortRead(pVM, uPort, &u32Value, cbTransfer);2146 rcStrict = IOMIOPortRead(pVM, pVCpu, uPort, &u32Value, cbTransfer); 2128 2147 if (!IOM_SUCCESS(rcStrict)) 2129 2148 break; … … 2165 2184 * 2166 2185 * @param pVM The virtual machine. 2186 * @param pVCpu Pointer to the virtual CPU structure of the caller. 2167 2187 * @param pRegFrame Pointer to CPUMCTXCORE guest registers structure. 2168 2188 * @param pCpu Disassembler CPU state. 2169 2189 */ 2170 VMMDECL(VBOXSTRICTRC) IOMInterpretINS(PVM pVM, P CPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu)2190 VMMDECL(VBOXSTRICTRC) IOMInterpretINS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu) 2171 2191 { 2172 2192 /* … … 2188 2208 } 2189 2209 2190 return IOMInterpretINSEx(pVM, p RegFrame, Port, pCpu->fPrefix, (DISCPUMODE)pCpu->uAddrMode, cb);2210 return IOMInterpretINSEx(pVM, pVCpu, pRegFrame, Port, pCpu->fPrefix, (DISCPUMODE)pCpu->uAddrMode, cb); 2191 2211 } 2192 2212 … … 2209 2229 * 2210 2230 * @param pVM The virtual machine. 2231 * @param pVCpu Pointer to the virtual CPU structure of the caller. 2211 2232 * @param pRegFrame Pointer to CPUMCTXCORE guest registers structure. 2212 2233 * @param uPort IO Port … … 2215 2236 * @param cbTransfer Size of transfer unit 2216 2237 */ 2217 VMMDECL(VBOXSTRICTRC) IOMInterpretOUTSEx(PVM pVM, P CPUMCTXCORE pRegFrame, uint32_t uPort, uint32_t uPrefix,2238 VMMDECL(VBOXSTRICTRC) IOMInterpretOUTSEx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uPort, uint32_t uPrefix, 2218 2239 DISCPUMODE enmAddrMode, uint32_t cbTransfer) 2219 2240 { … … 2227 2248 || pRegFrame->eflags.Bits.u1DF) 2228 2249 return VINF_EM_RAW_EMULATE_INSTR; 2229 2230 PVMCPU pVCpu = VMMGetCpu(pVM);2231 2250 2232 2251 /* … … 2277 2296 */ 2278 2297 const RTGCUINTREG cTransfersOrg = cTransfers; 2279 rcStrict = IOMIOPortWriteString(pVM, uPort, &GCPtrSrc, &cTransfers, cbTransfer);2298 rcStrict = IOMIOPortWriteString(pVM, pVCpu, uPort, &GCPtrSrc, &cTransfers, cbTransfer); 2280 2299 AssertRC(VBOXSTRICTRC_VAL(rcStrict)); Assert(cTransfers <= cTransfersOrg); 2281 2300 pRegFrame->rsi = ((pRegFrame->rsi + (cTransfersOrg - cTransfers) * cbTransfer) & fAddrMask) … … 2293 2312 if (rcStrict != VINF_SUCCESS) 2294 2313 break; 2295 rcStrict = IOMIOPortWrite(pVM, uPort, u32Value, cbTransfer);2314 rcStrict = IOMIOPortWrite(pVM, pVCpu, uPort, u32Value, cbTransfer); 2296 2315 if (!IOM_SUCCESS(rcStrict)) 2297 2316 break; … … 2332 2351 * 2333 2352 * @param pVM The virtual machine. 2353 * @param pVCpu Pointer to the virtual CPU structure of the caller. 2334 2354 * @param pRegFrame Pointer to CPUMCTXCORE guest registers structure. 2335 2355 * @param pCpu Disassembler CPU state. 2336 2356 */ 2337 VMMDECL(VBOXSTRICTRC) IOMInterpretOUTS(PVM pVM, P CPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu)2357 VMMDECL(VBOXSTRICTRC) IOMInterpretOUTS(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu) 2338 2358 { 2339 2359 /* … … 2357 2377 } 2358 2378 2359 return IOMInterpretOUTSEx(pVM, p RegFrame, Port, pCpu->fPrefix, (DISCPUMODE)pCpu->uAddrMode, cb);2379 return IOMInterpretOUTSEx(pVM, pVCpu, pRegFrame, Port, pCpu->fPrefix, (DISCPUMODE)pCpu->uAddrMode, cb); 2360 2380 } 2361 2381 … … 2396 2416 * Lookup the context range node the page belongs to. 2397 2417 */ 2398 PIOMMMIORANGE pRange = iomMmioGetRange(pVM, GCPhys);2418 PIOMMMIORANGE pRange = iomMmioGetRange(pVM, pVCpu, GCPhys); 2399 2419 AssertMsgReturn(pRange, 2400 2420 ("Handlers and page tables are out of sync or something! GCPhys=%RGp\n", GCPhys), VERR_IOM_MMIO_RANGE_NOT_FOUND); … … 2461 2481 #ifdef VBOX_STRICT 2462 2482 /* Can't lock IOM here due to potential deadlocks in the VGA device; not safe to access. */ 2463 PIOMMMIORANGE pRange = iomMMIOGetRangeUnsafe(pVM, GCPhys);2483 PIOMMMIORANGE pRange = iomMMIOGetRangeUnsafe(pVM, pVCpu, GCPhys); 2464 2484 AssertMsgReturn(pRange, 2465 2485 ("Handlers and page tables are out of sync or something! GCPhys=%RGp\n", GCPhys), VERR_IOM_MMIO_RANGE_NOT_FOUND); … … 2514 2534 #ifdef VBOX_STRICT 2515 2535 /* Can't lock IOM here due to potential deadlocks in the VGA device; not safe to access. */ 2516 PIOMMMIORANGE pRange = iomMMIOGetRangeUnsafe(pVM, GCPhys);2536 PIOMMMIORANGE pRange = iomMMIOGetRangeUnsafe(pVM, pVCpu, GCPhys); 2517 2537 AssertMsgReturn(pRange, 2518 2538 ("Handlers and page tables are out of sync or something! GCPhys=%RGp\n", GCPhys), VERR_IOM_MMIO_RANGE_NOT_FOUND); -
trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp
r45235 r45305 2475 2475 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize)); 2476 2476 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite); 2477 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,2477 rc = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix, 2478 2478 (DISCPUMODE)pDis->uAddrMode, uIOSize); 2479 2479 } … … 2482 2482 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize)); 2483 2483 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead); 2484 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,2484 rc = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix, 2485 2485 (DISCPUMODE)pDis->uAddrMode, uIOSize); 2486 2486 } … … 2499 2499 uIOSize)); 2500 2500 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite); 2501 rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);2501 rc = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize); 2502 2502 if (rc == VINF_IOM_R3_IOPORT_WRITE) 2503 2503 { … … 2511 2511 2512 2512 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead); 2513 rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);2513 rc = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, uIOSize); 2514 2514 if (IOM_SUCCESS(rc)) 2515 2515 { -
trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
r45237 r45305 4609 4609 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize)); 4610 4610 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite); 4611 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->fPrefix, (DISCPUMODE)pDis->uAddrMode, cbSize); 4611 rc = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), uPort, pDis->fPrefix, 4612 (DISCPUMODE)pDis->uAddrMode, cbSize); 4612 4613 } 4613 4614 else … … 4615 4616 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize)); 4616 4617 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead); 4617 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->fPrefix, (DISCPUMODE)pDis->uAddrMode, cbSize); 4618 rc = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), uPort, pDis->fPrefix, 4619 (DISCPUMODE)pDis->uAddrMode, cbSize); 4618 4620 } 4619 4621 } … … 4631 4633 { 4632 4634 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite); 4633 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);4635 rc = IOMIOPortWrite(pVM, pVCpu, uPort, pCtx->eax & uAndVal, cbSize); 4634 4636 if (rc == VINF_IOM_R3_IOPORT_WRITE) 4635 4637 HMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pCtx->rip + cbInstr, uPort, uAndVal, cbSize); … … 4640 4642 4641 4643 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead); 4642 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);4644 rc = IOMIOPortRead(pVM, pVCpu, uPort, &u32Val, cbSize); 4643 4645 if (IOM_SUCCESS(rc)) 4644 4646 { … … 4763 4765 4764 4766 LogFlow(("Apic access at %RGp\n", GCPhys)); 4765 rc = IOMMMIOPhysHandler(pVM, (uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ) ? 0 : X86_TRAP_PF_RW,4767 rc = IOMMMIOPhysHandler(pVM, pVCpu, (uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ) ? 0 : X86_TRAP_PF_RW, 4766 4768 CPUMCTX2CORE(pCtx), GCPhys); 4767 4769 if (rc == VINF_SUCCESS) -
trunk/src/VBox/VMM/VMMR3/EMHM.cpp
r45276 r45305 313 313 { 314 314 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn); 315 rcStrict = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);315 rcStrict = IOMInterpretIN(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu); 316 316 break; 317 317 } … … 320 320 { 321 321 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut); 322 rcStrict = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);322 rcStrict = IOMInterpretOUT(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu); 323 323 break; 324 324 } … … 333 333 { 334 334 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn); 335 rcStrict = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);335 rcStrict = IOMInterpretINS(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu); 336 336 break; 337 337 } … … 341 341 { 342 342 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut); 343 rcStrict = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);343 rcStrict = IOMInterpretOUTS(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu); 344 344 break; 345 345 } -
trunk/src/VBox/VMM/VMMR3/EMRaw.cpp
r45276 r45305 435 435 { 436 436 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn); 437 rcStrict = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);437 rcStrict = IOMInterpretIN(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu); 438 438 break; 439 439 } … … 442 442 { 443 443 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut); 444 rcStrict = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);444 rcStrict = IOMInterpretOUT(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu); 445 445 break; 446 446 } … … 455 455 { 456 456 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn); 457 rcStrict = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);457 rcStrict = IOMInterpretINS(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu); 458 458 break; 459 459 } … … 463 463 { 464 464 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut); 465 rcStrict = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);465 rcStrict = IOMInterpretOUTS(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu); 466 466 break; 467 467 } -
trunk/src/VBox/VMM/VMMR3/HM.cpp
r45291 r45305 2552 2552 uint32_t u32Val = 0; 2553 2553 2554 rcStrict = IOMIOPortRead(pVM, pVCpu ->hm.s.PendingIO.s.Port.uPort,2554 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort, 2555 2555 &u32Val, 2556 2556 pVCpu->hm.s.PendingIO.s.Port.cbSize); … … 2565 2565 2566 2566 case HMPENDINGIO_PORT_WRITE: 2567 rcStrict = IOMIOPortWrite(pVM, pVCpu ->hm.s.PendingIO.s.Port.uPort,2567 rcStrict = IOMIOPortWrite(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort, 2568 2568 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal, 2569 2569 pVCpu->hm.s.PendingIO.s.Port.cbSize); -
trunk/src/VBox/VMM/VMMR3/IOM.cpp
r45301 r45305 238 238 static void iomR3FlushCache(PVM pVM) 239 239 { 240 /* 241 * Since all relevant (1) cache use requires at least read access to the 242 * critical section, we can exclude all other EMTs by grabbing exclusive 243 * access to the critical section and then safely update the caches of 244 * other EMTs. 245 * (1) The irrelvant access not holding the lock is in assertion code. 246 */ 240 247 IOM_LOCK(pVM); 241 242 /* 243 * Caching of port and statistics (saves some time in rep outs/ins instruction emulation) 244 */ 245 pVM->iom.s.pRangeLastReadR0 = NIL_RTR0PTR; 246 pVM->iom.s.pRangeLastWriteR0 = NIL_RTR0PTR; 247 pVM->iom.s.pStatsLastReadR0 = NIL_RTR0PTR; 248 pVM->iom.s.pStatsLastWriteR0 = NIL_RTR0PTR; 249 pVM->iom.s.pMMIORangeLastR0 = NIL_RTR0PTR; 250 pVM->iom.s.pMMIOStatsLastR0 = NIL_RTR0PTR; 251 252 pVM->iom.s.pRangeLastReadR3 = NULL; 253 pVM->iom.s.pRangeLastWriteR3 = NULL; 254 pVM->iom.s.pStatsLastReadR3 = NULL; 255 pVM->iom.s.pStatsLastWriteR3 = NULL; 256 pVM->iom.s.pMMIORangeLastR3 = NULL; 257 pVM->iom.s.pMMIOStatsLastR3 = NULL; 258 259 pVM->iom.s.pRangeLastReadRC = NIL_RTRCPTR; 260 pVM->iom.s.pRangeLastWriteRC = NIL_RTRCPTR; 261 pVM->iom.s.pStatsLastReadRC = NIL_RTRCPTR; 262 pVM->iom.s.pStatsLastWriteRC = NIL_RTRCPTR; 263 pVM->iom.s.pMMIORangeLastRC = NIL_RTRCPTR; 264 pVM->iom.s.pMMIOStatsLastRC = NIL_RTRCPTR; 248 VMCPUID iCpu = pVM->cCpus; 249 while (iCpu-- > 0) 250 { 251 PVMCPU pVCpu = &pVM->aCpus[iCpu]; 252 pVCpu->iom.s.pRangeLastReadR0 = NIL_RTR0PTR; 253 pVCpu->iom.s.pRangeLastWriteR0 = NIL_RTR0PTR; 254 pVCpu->iom.s.pStatsLastReadR0 = NIL_RTR0PTR; 255 pVCpu->iom.s.pStatsLastWriteR0 = NIL_RTR0PTR; 256 pVCpu->iom.s.pMMIORangeLastR0 = NIL_RTR0PTR; 257 pVCpu->iom.s.pMMIOStatsLastR0 = NIL_RTR0PTR; 258 259 pVCpu->iom.s.pRangeLastReadR3 = NULL; 260 pVCpu->iom.s.pRangeLastWriteR3 = NULL; 261 pVCpu->iom.s.pStatsLastReadR3 = NULL; 262 pVCpu->iom.s.pStatsLastWriteR3 = NULL; 263 pVCpu->iom.s.pMMIORangeLastR3 = NULL; 264 pVCpu->iom.s.pMMIOStatsLastR3 = NULL; 265 266 pVCpu->iom.s.pRangeLastReadRC = NIL_RTRCPTR; 267 pVCpu->iom.s.pRangeLastWriteRC = NIL_RTRCPTR; 268 pVCpu->iom.s.pStatsLastReadRC = NIL_RTRCPTR; 269 pVCpu->iom.s.pStatsLastWriteRC = NIL_RTRCPTR; 270 pVCpu->iom.s.pMMIORangeLastRC = NIL_RTRCPTR; 271 pVCpu->iom.s.pMMIOStatsLastRC = NIL_RTRCPTR; 272 } 265 273 266 274 IOM_UNLOCK(pVM); … … 304 312 305 313 /* 306 * Apply relocations to the cached GC handlers 307 */ 308 if (pVM->iom.s.pRangeLastReadRC) 309 pVM->iom.s.pRangeLastReadRC += offDelta; 310 if (pVM->iom.s.pRangeLastWriteRC) 311 pVM->iom.s.pRangeLastWriteRC += offDelta; 312 if (pVM->iom.s.pStatsLastReadRC) 313 pVM->iom.s.pStatsLastReadRC += offDelta; 314 if (pVM->iom.s.pStatsLastWriteRC) 315 pVM->iom.s.pStatsLastWriteRC += offDelta; 316 if (pVM->iom.s.pMMIORangeLastRC) 317 pVM->iom.s.pMMIORangeLastRC += offDelta; 318 if (pVM->iom.s.pMMIOStatsLastRC) 319 pVM->iom.s.pMMIOStatsLastRC += offDelta; 314 * Reset the raw-mode cache (don't bother relocating it). 315 */ 316 VMCPUID iCpu = pVM->cCpus; 317 while (iCpu-- > 0) 318 { 319 PVMCPU pVCpu = &pVM->aCpus[iCpu]; 320 pVCpu->iom.s.pRangeLastReadRC = NIL_RTRCPTR; 321 pVCpu->iom.s.pRangeLastWriteRC = NIL_RTRCPTR; 322 pVCpu->iom.s.pStatsLastReadRC = NIL_RTRCPTR; 323 pVCpu->iom.s.pStatsLastWriteRC = NIL_RTRCPTR; 324 pVCpu->iom.s.pMMIORangeLastRC = NIL_RTRCPTR; 325 pVCpu->iom.s.pMMIOStatsLastRC = NIL_RTRCPTR; 326 } 320 327 } 321 328 … … 1317 1324 sizeof(RTRCPTR) * 2, "pvUser "); 1318 1325 RTAvlroIOPortDoWithAll(&pVM->iom.s.pTreesR3->IOPortTreeRC, true, iomR3IOPortInfoOneRC, (void *)pHlp); 1319 1320 if (pVM->iom.s.pRangeLastReadRC)1321 {1322 PIOMIOPORTRANGERC pRange = (PIOMIOPORTRANGERC)MMHyperRCToCC(pVM, pVM->iom.s.pRangeLastReadRC);1323 pHlp->pfnPrintf(pHlp, "RC Read Ports: %#04x-%#04x %RRv %s\n",1324 pRange->Port, pRange->Port + pRange->cPorts, pVM->iom.s.pRangeLastReadRC, pRange->pszDesc);1325 }1326 if (pVM->iom.s.pStatsLastReadRC)1327 {1328 PIOMIOPORTSTATS pRange = (PIOMIOPORTSTATS)MMHyperRCToCC(pVM, pVM->iom.s.pStatsLastReadRC);1329 pHlp->pfnPrintf(pHlp, "RC Read Stats: %#04x %RRv\n",1330 pRange->Core.Key, pVM->iom.s.pStatsLastReadRC);1331 }1332 1333 if (pVM->iom.s.pRangeLastWriteRC)1334 {1335 PIOMIOPORTRANGERC pRange = (PIOMIOPORTRANGERC)MMHyperRCToCC(pVM, pVM->iom.s.pRangeLastWriteRC);1336 pHlp->pfnPrintf(pHlp, "RC Write Ports: %#04x-%#04x %RRv %s\n",1337 pRange->Port, pRange->Port + pRange->cPorts, pVM->iom.s.pRangeLastWriteRC, pRange->pszDesc);1338 }1339 if (pVM->iom.s.pStatsLastWriteRC)1340 {1341 PIOMIOPORTSTATS pRange = (PIOMIOPORTSTATS)MMHyperRCToCC(pVM, pVM->iom.s.pStatsLastWriteRC);1342 pHlp->pfnPrintf(pHlp, "RC Write Stats: %#04x %RRv\n",1343 pRange->Core.Key, pVM->iom.s.pStatsLastWriteRC);1344 }1345 1346 if (pVM->iom.s.pRangeLastReadR3)1347 {1348 PIOMIOPORTRANGER3 pRange = pVM->iom.s.pRangeLastReadR3;1349 pHlp->pfnPrintf(pHlp, "R3 Read Ports: %#04x-%#04x %p %s\n",1350 pRange->Port, pRange->Port + pRange->cPorts, pRange, pRange->pszDesc);1351 }1352 if (pVM->iom.s.pStatsLastReadR3)1353 {1354 PIOMIOPORTSTATS pRange = pVM->iom.s.pStatsLastReadR3;1355 pHlp->pfnPrintf(pHlp, "R3 Read Stats: %#04x %p\n",1356 pRange->Core.Key, pRange);1357 }1358 1359 if (pVM->iom.s.pRangeLastWriteR3)1360 {1361 PIOMIOPORTRANGER3 pRange = pVM->iom.s.pRangeLastWriteR3;1362 pHlp->pfnPrintf(pHlp, "R3 Write Ports: %#04x-%#04x %p %s\n",1363 pRange->Port, pRange->Port + pRange->cPorts, pRange, pRange->pszDesc);1364 }1365 if (pVM->iom.s.pStatsLastWriteR3)1366 {1367 PIOMIOPORTSTATS pRange = pVM->iom.s.pStatsLastWriteR3;1368 pHlp->pfnPrintf(pHlp, "R3 Write Stats: %#04x %p\n",1369 pRange->Core.Key, pRange);1370 }1371 1372 if (pVM->iom.s.pRangeLastReadR0)1373 {1374 PIOMIOPORTRANGER0 pRange = (PIOMIOPORTRANGER0)MMHyperR0ToCC(pVM, pVM->iom.s.pRangeLastReadR0);1375 pHlp->pfnPrintf(pHlp, "R0 Read Ports: %#04x-%#04x %p %s\n",1376 pRange->Port, pRange->Port + pRange->cPorts, pRange, pRange->pszDesc);1377 }1378 if (pVM->iom.s.pStatsLastReadR0)1379 {1380 PIOMIOPORTSTATS pRange = (PIOMIOPORTSTATS)MMHyperR0ToCC(pVM, pVM->iom.s.pStatsLastReadR0);1381 pHlp->pfnPrintf(pHlp, "R0 Read Stats: %#04x %p\n",1382 pRange->Core.Key, pRange);1383 }1384 1385 if (pVM->iom.s.pRangeLastWriteR0)1386 {1387 PIOMIOPORTRANGER0 pRange = (PIOMIOPORTRANGER0)MMHyperR0ToCC(pVM, pVM->iom.s.pRangeLastWriteR0);1388 pHlp->pfnPrintf(pHlp, "R0 Write Ports: %#04x-%#04x %p %s\n",1389 pRange->Port, pRange->Port + pRange->cPorts, pRange, pRange->pszDesc);1390 }1391 if (pVM->iom.s.pStatsLastWriteR0)1392 {1393 PIOMIOPORTSTATS pRange = (PIOMIOPORTSTATS)MMHyperR0ToCC(pVM, pVM->iom.s.pStatsLastWriteR0);1394 pHlp->pfnPrintf(pHlp, "R0 Write Stats: %#04x %p\n",1395 pRange->Core.Key, pRange);1396 }1397 1326 } 1398 1327 … … 1532 1461 * @param pfnReadCallback Pointer to function which is gonna handle Read operations. 1533 1462 * @param pfnFillCallback Pointer to function which is gonna handle Fill/memset operations. 1463 * @thread EMT 1534 1464 */ 1535 1465 VMMR3_INT_DECL(int) … … 1549 1479 return VERR_INVALID_PARAMETER; 1550 1480 } 1481 PVMCPU pVCpu = VMMGetCpu(pVM); Assert(pVCpu); 1551 1482 1552 1483 /* … … 1554 1485 */ 1555 1486 IOM_LOCK(pVM); 1556 PIOMMMIORANGE pRange = iomMmioGetRange(pVM, GCPhysStart);1487 PIOMMMIORANGE pRange = iomMmioGetRange(pVM, pVCpu, GCPhysStart); 1557 1488 AssertReturnStmt(pRange, IOM_UNLOCK(pVM), VERR_IOM_MMIO_RANGE_NOT_FOUND); 1558 1489 AssertReturnStmt(pRange->pDevInsR3 == pDevIns, IOM_UNLOCK(pVM), VERR_IOM_NOT_MMIO_RANGE_OWNER); … … 1588 1519 * @param pfnReadCallback Pointer to function which is gonna handle Read operations. 1589 1520 * @param pfnFillCallback Pointer to function which is gonna handle Fill/memset operations. 1521 * @thread EMT 1590 1522 */ 1591 1523 VMMR3_INT_DECL(int) … … 1606 1538 return VERR_INVALID_PARAMETER; 1607 1539 } 1540 PVMCPU pVCpu = VMMGetCpu(pVM); Assert(pVCpu); 1608 1541 1609 1542 /* … … 1611 1544 */ 1612 1545 IOM_LOCK(pVM); 1613 PIOMMMIORANGE pRange = iomMmioGetRange(pVM, GCPhysStart);1546 PIOMMMIORANGE pRange = iomMmioGetRange(pVM, pVCpu, GCPhysStart); 1614 1547 AssertReturnStmt(pRange, IOM_UNLOCK(pVM), VERR_IOM_MMIO_RANGE_NOT_FOUND); 1615 1548 AssertReturnStmt(pRange->pDevInsR3 == pDevIns, IOM_UNLOCK(pVM), VERR_IOM_NOT_MMIO_RANGE_OWNER); … … 1656 1589 return VERR_IOM_INVALID_MMIO_RANGE; 1657 1590 } 1591 PVMCPU pVCpu = VMMGetCpu(pVM); Assert(pVCpu); 1658 1592 1659 1593 IOM_LOCK(pVM); … … 1665 1599 while (GCPhys <= GCPhysLast && GCPhys >= GCPhysStart) 1666 1600 { 1667 PIOMMMIORANGE pRange = iomMmioGetRange(pVM, GCPhys);1601 PIOMMMIORANGE pRange = iomMmioGetRange(pVM, pVCpu, GCPhys); 1668 1602 if (!pRange) 1669 1603 { -
trunk/src/VBox/VMM/VMMRC/IOMRC.cpp
r41965 r45305 62 62 * 63 63 * @param pVM The virtual machine handle. 64 * @param pVCpu Pointer to the virtual CPU structure of the caller. 64 65 * @param pRegFrame Pointer to CPUMCTXCORE guest registers structure. 65 66 * @param pCpu Disassembler CPU state. 66 67 */ 67 VMMRCDECL(VBOXSTRICTRC) IOMRCIOPortHandler(PVM pVM, P CPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu)68 VMMRCDECL(VBOXSTRICTRC) IOMRCIOPortHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu) 68 69 { 69 70 switch (pCpu->pCurInstr->uOpcode) 70 71 { 71 72 case OP_IN: 72 return IOMInterpretIN(pVM, p RegFrame, pCpu);73 return IOMInterpretIN(pVM, pVCpu, pRegFrame, pCpu); 73 74 74 75 case OP_OUT: 75 return IOMInterpretOUT(pVM, p RegFrame, pCpu);76 return IOMInterpretOUT(pVM, pVCpu, pRegFrame, pCpu); 76 77 77 78 case OP_INSB: 78 79 case OP_INSWD: 79 return IOMInterpretINS(pVM, p RegFrame, pCpu);80 return IOMInterpretINS(pVM, pVCpu, pRegFrame, pCpu); 80 81 81 82 case OP_OUTSB: 82 83 case OP_OUTSWD: 83 return IOMInterpretOUTS(pVM, p RegFrame, pCpu);84 return IOMInterpretOUTS(pVM, pVCpu, pRegFrame, pCpu); 84 85 85 86 /* -
trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp
r45276 r45305 1072 1072 && (Cpu.pCurInstr->fOpType & DISOPTYPE_PORTIO)) 1073 1073 { 1074 VBOXSTRICTRC rcStrict = IOMRCIOPortHandler(pVM, p RegFrame, &Cpu);1074 VBOXSTRICTRC rcStrict = IOMRCIOPortHandler(pVM, pVCpu, pRegFrame, &Cpu); 1075 1075 if (IOM_SUCCESS(rcStrict)) 1076 1076 pRegFrame->rip += cbOp; -
trunk/src/VBox/VMM/include/IOMInline.h
r45301 r45305 63 63 * 64 64 * @param pVM Pointer to the VM. 65 * @param GCPhys Physical address to lookup. 66 */ 67 DECLINLINE(PIOMMMIORANGE) iomMmioGetRange(PVM pVM, RTGCPHYS GCPhys) 65 * @param pVCpu Pointer to the virtual CPU structure of the caller. 66 * @param GCPhys Physical address to lookup. 67 */ 68 DECLINLINE(PIOMMMIORANGE) iomMmioGetRange(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys) 68 69 { 69 70 Assert(IOM_IS_SHARED_LOCK_OWNER(pVM)); 70 PIOMMMIORANGE pRange = pV M->iom.s.CTX_SUFF(pMMIORangeLast);71 PIOMMMIORANGE pRange = pVCpu->iom.s.CTX_SUFF(pMMIORangeLast); 71 72 if ( !pRange 72 73 || GCPhys - pRange->GCPhys >= pRange->cb) 73 pV M->iom.s.CTX_SUFF(pMMIORangeLast) = pRange74 pVCpu->iom.s.CTX_SUFF(pMMIORangeLast) = pRange 74 75 = (PIOMMMIORANGE)RTAvlroGCPhysRangeGet(&pVM->iom.s.CTX_SUFF(pTrees)->MMIOTree, GCPhys); 75 76 return pRange; … … 98 99 * 99 100 * @param pVM Pointer to the VM. 100 * @param GCPhys Physical address to lookup. 101 */ 102 DECLINLINE(PIOMMMIORANGE) iomMmioGetRangeWithRef(PVM pVM, RTGCPHYS GCPhys) 101 * @param pVCpu Pointer to the virtual CPU structure of the caller. 102 * @param GCPhys Physical address to lookup. 103 */ 104 DECLINLINE(PIOMMMIORANGE) iomMmioGetRangeWithRef(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys) 103 105 { 104 106 int rc = IOM_LOCK_SHARED_EX(pVM, VINF_SUCCESS); 105 107 AssertRCReturn(rc, NULL); 106 108 107 PIOMMMIORANGE pRange = pV M->iom.s.CTX_SUFF(pMMIORangeLast);109 PIOMMMIORANGE pRange = pVCpu->iom.s.CTX_SUFF(pMMIORangeLast); 108 110 if ( !pRange 109 111 || GCPhys - pRange->GCPhys >= pRange->cb) 110 pV M->iom.s.CTX_SUFF(pMMIORangeLast) = pRange112 pVCpu->iom.s.CTX_SUFF(pMMIORangeLast) = pRange 111 113 = (PIOMMMIORANGE)RTAvlroGCPhysRangeGet(&pVM->iom.s.CTX_SUFF(pTrees)->MMIOTree, GCPhys); 112 114 if (pRange) … … 140 142 * 141 143 * @param pVM Pointer to the VM. 142 * @param GCPhys Physical address to lookup. 143 */ 144 DECLINLINE(PIOMMMIORANGE) iomMMIOGetRangeUnsafe(PVM pVM, RTGCPHYS GCPhys) 145 { 146 PIOMMMIORANGE pRange = pVM->iom.s.CTX_SUFF(pMMIORangeLast); 144 * @param pVCpu Pointer to the virtual CPU structure of the caller. 145 * @param GCPhys Physical address to lookup. 146 */ 147 DECLINLINE(PIOMMMIORANGE) iomMMIOGetRangeUnsafe(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys) 148 { 149 PIOMMMIORANGE pRange = pVCpu->iom.s.CTX_SUFF(pMMIORangeLast); 147 150 if ( !pRange 148 151 || GCPhys - pRange->GCPhys >= pRange->cb) 149 pV M->iom.s.CTX_SUFF(pMMIORangeLast) = pRange152 pVCpu->iom.s.CTX_SUFF(pMMIORangeLast) = pRange 150 153 = (PIOMMMIORANGE)RTAvlroGCPhysRangeGet(&pVM->iom.s.CTX_SUFF(pTrees)->MMIOTree, GCPhys); 151 154 return pRange; … … 164 167 * @returns NULL if not found (R0/GC), or out of memory (R3). 165 168 * 166 * @param pVM Pointer to the VM. 167 * @param GCPhys Physical address to lookup. 168 * @param pRange The MMIO range. 169 */ 170 DECLINLINE(PIOMMMIOSTATS) iomMmioGetStats(PVM pVM, RTGCPHYS GCPhys, PIOMMMIORANGE pRange) 169 * @param pVM Pointer to the VM. 170 * @param pVCpu Pointer to the virtual CPU structure of the caller. 171 * @param GCPhys Physical address to lookup. 172 * @param pRange The MMIO range. 173 */ 174 DECLINLINE(PIOMMMIOSTATS) iomMmioGetStats(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, PIOMMMIORANGE pRange) 171 175 { 172 176 IOM_LOCK_SHARED_EX(pVM, VINF_SUCCESS); … … 176 180 GCPhys = pRange->GCPhys; 177 181 178 PIOMMMIOSTATS pStats = pV M->iom.s.CTX_SUFF(pMMIOStatsLast);182 PIOMMMIOSTATS pStats = pVCpu->iom.s.CTX_SUFF(pMMIOStatsLast); 179 183 if ( !pStats 180 184 || pStats->Core.Key != GCPhys) -
trunk/src/VBox/VMM/include/IOMInternal.h
r45301 r45305 335 335 #endif 336 336 337 /** @name Caching of I/O Port and MMIO ranges and statistics.338 * (Saves quite some time in rep outs/ins instruction emulation.)339 * @{ */340 R3PTRTYPE(PIOMIOPORTRANGER3) pRangeLastReadR3;341 R3PTRTYPE(PIOMIOPORTRANGER3) pRangeLastWriteR3;342 R3PTRTYPE(PIOMIOPORTSTATS) pStatsLastReadR3;343 R3PTRTYPE(PIOMIOPORTSTATS) pStatsLastWriteR3;344 R3PTRTYPE(PIOMMMIORANGE) pMMIORangeLastR3;345 R3PTRTYPE(PIOMMMIOSTATS) pMMIOStatsLastR3;346 347 R0PTRTYPE(PIOMIOPORTRANGER0) pRangeLastReadR0;348 R0PTRTYPE(PIOMIOPORTRANGER0) pRangeLastWriteR0;349 R0PTRTYPE(PIOMIOPORTSTATS) pStatsLastReadR0;350 R0PTRTYPE(PIOMIOPORTSTATS) pStatsLastWriteR0;351 R0PTRTYPE(PIOMMMIORANGE) pMMIORangeLastR0;352 R0PTRTYPE(PIOMMMIOSTATS) pMMIOStatsLastR0;353 354 RCPTRTYPE(PIOMIOPORTRANGERC) pRangeLastReadRC;355 RCPTRTYPE(PIOMIOPORTRANGERC) pRangeLastWriteRC;356 RCPTRTYPE(PIOMIOPORTSTATS) pStatsLastReadRC;357 RCPTRTYPE(PIOMIOPORTSTATS) pStatsLastWriteRC;358 RCPTRTYPE(PIOMMMIORANGE) pMMIORangeLastRC;359 RCPTRTYPE(PIOMMMIOSTATS) pMMIOStatsLastRC;360 /** @} */361 362 337 /** @name I/O Port statistics. 363 338 * @{ */ … … 414 389 * on the stack. */ 415 390 DISCPUSTATE DisState; 391 392 /** @name Caching of I/O Port and MMIO ranges and statistics. 393 * (Saves quite some time in rep outs/ins instruction emulation.) 394 * @{ */ 395 R3PTRTYPE(PIOMIOPORTRANGER3) pRangeLastReadR3; 396 R3PTRTYPE(PIOMIOPORTRANGER3) pRangeLastWriteR3; 397 R3PTRTYPE(PIOMIOPORTSTATS) pStatsLastReadR3; 398 R3PTRTYPE(PIOMIOPORTSTATS) pStatsLastWriteR3; 399 R3PTRTYPE(PIOMMMIORANGE) pMMIORangeLastR3; 400 R3PTRTYPE(PIOMMMIOSTATS) pMMIOStatsLastR3; 401 402 R0PTRTYPE(PIOMIOPORTRANGER0) pRangeLastReadR0; 403 R0PTRTYPE(PIOMIOPORTRANGER0) pRangeLastWriteR0; 404 R0PTRTYPE(PIOMIOPORTSTATS) pStatsLastReadR0; 405 R0PTRTYPE(PIOMIOPORTSTATS) pStatsLastWriteR0; 406 R0PTRTYPE(PIOMMMIORANGE) pMMIORangeLastR0; 407 R0PTRTYPE(PIOMMMIOSTATS) pMMIOStatsLastR0; 408 409 RCPTRTYPE(PIOMIOPORTRANGERC) pRangeLastReadRC; 410 RCPTRTYPE(PIOMIOPORTRANGERC) pRangeLastWriteRC; 411 RCPTRTYPE(PIOMIOPORTSTATS) pStatsLastReadRC; 412 RCPTRTYPE(PIOMIOPORTSTATS) pStatsLastWriteRC; 413 RCPTRTYPE(PIOMMMIORANGE) pMMIORangeLastRC; 414 RCPTRTYPE(PIOMMMIOSTATS) pMMIOStatsLastRC; 415 /** @} */ 416 416 } IOMCPU; 417 417 /** Pointer to IOM per virtual CPU instance data. */ -
trunk/src/VBox/VMM/testcase/tstVMStruct.h
r45152 r45305 276 276 GEN_CHECK_OFF(IOM, pTreesR3); 277 277 GEN_CHECK_OFF(IOM, pTreesR0); 278 GEN_CHECK_OFF(IOM, pMMIORangeLastR3);279 GEN_CHECK_OFF(IOM, pMMIOStatsLastR3);280 GEN_CHECK_OFF(IOM, pMMIORangeLastR0);281 GEN_CHECK_OFF(IOM, pMMIOStatsLastR0);282 GEN_CHECK_OFF(IOM, pMMIORangeLastRC);283 GEN_CHECK_OFF(IOM, pMMIOStatsLastRC);284 GEN_CHECK_OFF(IOM, pRangeLastReadR0);285 GEN_CHECK_OFF(IOM, pRangeLastReadRC);286 278 287 279 GEN_CHECK_SIZE(IOMCPU); 288 280 GEN_CHECK_OFF(IOMCPU, DisState); 281 GEN_CHECK_OFF(IOMCPU, pMMIORangeLastR3); 282 GEN_CHECK_OFF(IOMCPU, pMMIOStatsLastR3); 283 GEN_CHECK_OFF(IOMCPU, pMMIORangeLastR0); 284 GEN_CHECK_OFF(IOMCPU, pMMIOStatsLastR0); 285 GEN_CHECK_OFF(IOMCPU, pMMIORangeLastRC); 286 GEN_CHECK_OFF(IOMCPU, pMMIOStatsLastRC); 287 GEN_CHECK_OFF(IOMCPU, pRangeLastReadR0); 288 GEN_CHECK_OFF(IOMCPU, pRangeLastReadRC); 289 289 290 290 GEN_CHECK_SIZE(IOMMMIORANGE); -
trunk/src/recompiler/VBoxREMWrapper.cpp
r44528 r45305 680 680 { 681 681 { REMPARMDESC_FLAGS_INT, sizeof(PVM), NULL }, 682 { REMPARMDESC_FLAGS_INT, sizeof(PVMCPU), NULL }, 682 683 { REMPARMDESC_FLAGS_INT, sizeof(RTIOPORT), NULL }, 683 684 { REMPARMDESC_FLAGS_INT, sizeof(uint32_t *), NULL }, … … 687 688 { 688 689 { REMPARMDESC_FLAGS_INT, sizeof(PVM), NULL }, 690 { REMPARMDESC_FLAGS_INT, sizeof(PVMCPU), NULL }, 689 691 { REMPARMDESC_FLAGS_INT, sizeof(RTIOPORT), NULL }, 690 692 { REMPARMDESC_FLAGS_INT, sizeof(uint32_t), NULL }, … … 694 696 { 695 697 { REMPARMDESC_FLAGS_INT, sizeof(PVM), NULL }, 698 { REMPARMDESC_FLAGS_INT, sizeof(PVMCPU), NULL }, 696 699 { REMPARMDESC_FLAGS_GCPHYS, sizeof(RTGCPHYS), NULL }, 697 700 { REMPARMDESC_FLAGS_INT, sizeof(uint32_t *), NULL }, … … 701 704 { 702 705 { REMPARMDESC_FLAGS_INT, sizeof(PVM), NULL }, 706 { REMPARMDESC_FLAGS_INT, sizeof(PVMCPU), NULL }, 703 707 { REMPARMDESC_FLAGS_GCPHYS, sizeof(RTGCPHYS), NULL }, 704 708 { REMPARMDESC_FLAGS_INT, sizeof(uint32_t), NULL }, … … 1234 1238 { "EMGetInhibitInterruptsPC", VMM_FN(EMGetInhibitInterruptsPC), &g_aArgsVMCPU[0], RT_ELEMENTS(g_aArgsVMCPU), REMFNDESC_FLAGS_RET_INT, sizeof(RTGCPTR), NULL }, 1235 1239 { "EMSetInhibitInterruptsPC", VMM_FN(EMSetInhibitInterruptsPC), &g_aArgsEMSetInhibitInterruptsPC[0], RT_ELEMENTS(g_aArgsEMSetInhibitInterruptsPC), REMFNDESC_FLAGS_RET_INT, sizeof(int), NULL }, 1236 { "HMR3CanExecuteGuest", VMM_FN(HMR3CanExecuteGuest), &g_aArgsHMR3CanExecuteGuest[0], RT_ELEMENTS(g_aArgsHMR3CanExecuteGuest),REMFNDESC_FLAGS_RET_INT, sizeof(int), NULL },1240 { "HMR3CanExecuteGuest", VMM_FN(HMR3CanExecuteGuest), &g_aArgsHMR3CanExecuteGuest[0], RT_ELEMENTS(g_aArgsHMR3CanExecuteGuest), REMFNDESC_FLAGS_RET_INT, sizeof(int), NULL }, 1237 1241 { "IOMIOPortRead", VMM_FN(IOMIOPortRead), &g_aArgsIOMIOPortRead[0], RT_ELEMENTS(g_aArgsIOMIOPortRead), REMFNDESC_FLAGS_RET_INT, sizeof(int), NULL }, 1238 1242 { "IOMIOPortWrite", VMM_FN(IOMIOPortWrite), &g_aArgsIOMIOPortWrite[0], RT_ELEMENTS(g_aArgsIOMIOPortWrite), REMFNDESC_FLAGS_RET_INT, sizeof(int), NULL }, -
trunk/src/recompiler/VBoxRecompiler.c
r45276 r45305 93 93 static int remR3InitPhysRamSizeAndDirtyMap(PVM pVM, bool fGuarded); 94 94 95 static uint32_t remR3MMIOReadU8(void *pv VM, target_phys_addr_t GCPhys);96 static uint32_t remR3MMIOReadU16(void *pv VM, target_phys_addr_t GCPhys);97 static uint32_t remR3MMIOReadU32(void *pv VM, target_phys_addr_t GCPhys);98 static void remR3MMIOWriteU8(void *pv VM, target_phys_addr_t GCPhys, uint32_t u32);99 static void remR3MMIOWriteU16(void *pv VM, target_phys_addr_t GCPhys, uint32_t u32);100 static void remR3MMIOWriteU32(void *pv VM, target_phys_addr_t GCPhys, uint32_t u32);95 static uint32_t remR3MMIOReadU8(void *pvEnv, target_phys_addr_t GCPhys); 96 static uint32_t remR3MMIOReadU16(void *pvEnv, target_phys_addr_t GCPhys); 97 static uint32_t remR3MMIOReadU32(void *pvEnv, target_phys_addr_t GCPhys); 98 static void remR3MMIOWriteU8(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32); 99 static void remR3MMIOWriteU16(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32); 100 static void remR3MMIOWriteU32(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32); 101 101 102 102 static uint32_t remR3HandlerReadU8(void *pvVM, target_phys_addr_t GCPhys); … … 334 334 * Register ram types. 335 335 */ 336 pVM->rem.s.iMMIOMemType = cpu_register_io_memory(g_apfnMMIORead, g_apfnMMIOWrite, pVM);336 pVM->rem.s.iMMIOMemType = cpu_register_io_memory(g_apfnMMIORead, g_apfnMMIOWrite, &pVM->rem.s.Env); 337 337 AssertReleaseMsg(pVM->rem.s.iMMIOMemType >= 0, ("pVM->rem.s.iMMIOMemType=%d\n", pVM->rem.s.iMMIOMemType)); 338 338 pVM->rem.s.iHandlerMemType = cpu_register_io_memory(g_apfnHandlerRead, g_apfnHandlerWrite, pVM); … … 3785 3785 3786 3786 /** Read MMIO memory. */ 3787 static uint32_t remR3MMIOReadU8(void *pvVM, target_phys_addr_t GCPhys) 3788 { 3789 uint32_t u32 = 0; 3790 int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 1); 3787 static uint32_t remR3MMIOReadU8(void *pvEnv, target_phys_addr_t GCPhys) 3788 { 3789 CPUX86State *env = (CPUX86State *)pvEnv; 3790 uint32_t u32 = 0; 3791 int rc = IOMMMIORead(env->pVM, env->pVCpu, GCPhys, &u32, 1); 3791 3792 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc); 3792 3793 Log2(("remR3MMIOReadU8: GCPhys=%RGp -> %02x\n", (RTGCPHYS)GCPhys, u32)); … … 3795 3796 3796 3797 /** Read MMIO memory. */ 3797 static uint32_t remR3MMIOReadU16(void *pvVM, target_phys_addr_t GCPhys) 3798 { 3799 uint32_t u32 = 0; 3800 int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 2); 3798 static uint32_t remR3MMIOReadU16(void *pvEnv, target_phys_addr_t GCPhys) 3799 { 3800 CPUX86State *env = (CPUX86State *)pvEnv; 3801 uint32_t u32 = 0; 3802 int rc = IOMMMIORead(env->pVM, env->pVCpu, GCPhys, &u32, 2); 3801 3803 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc); 3802 3804 Log2(("remR3MMIOReadU16: GCPhys=%RGp -> %04x\n", (RTGCPHYS)GCPhys, u32)); … … 3805 3807 3806 3808 /** Read MMIO memory. */ 3807 static uint32_t remR3MMIOReadU32(void *pvVM, target_phys_addr_t GCPhys) 3808 { 3809 uint32_t u32 = 0; 3810 int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 4); 3809 static uint32_t remR3MMIOReadU32(void *pvEnv, target_phys_addr_t GCPhys) 3810 { 3811 CPUX86State *env = (CPUX86State *)pvEnv; 3812 uint32_t u32 = 0; 3813 int rc = IOMMMIORead(env->pVM, env->pVCpu, GCPhys, &u32, 4); 3811 3814 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc); 3812 3815 Log2(("remR3MMIOReadU32: GCPhys=%RGp -> %08x\n", (RTGCPHYS)GCPhys, u32)); … … 3815 3818 3816 3819 /** Write to MMIO memory. */ 3817 static void remR3MMIOWriteU8(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32) 3818 { 3819 int rc; 3820 static void remR3MMIOWriteU8(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32) 3821 { 3822 CPUX86State *env = (CPUX86State *)pvEnv; 3823 int rc; 3820 3824 Log2(("remR3MMIOWriteU8: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32)); 3821 rc = IOMMMIOWrite( (PVM)pvVM, GCPhys, u32, 1);3825 rc = IOMMMIOWrite(env->pVM, env->pVCpu, GCPhys, u32, 1); 3822 3826 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc); 3823 3827 } 3824 3828 3825 3829 /** Write to MMIO memory. */ 3826 static void remR3MMIOWriteU16(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32) 3827 { 3828 int rc; 3830 static void remR3MMIOWriteU16(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32) 3831 { 3832 CPUX86State *env = (CPUX86State *)pvEnv; 3833 int rc; 3829 3834 Log2(("remR3MMIOWriteU16: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32)); 3830 rc = IOMMMIOWrite( (PVM)pvVM, GCPhys, u32, 2);3835 rc = IOMMMIOWrite(env->pVM, env->pVCpu, GCPhys, u32, 2); 3831 3836 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc); 3832 3837 } 3833 3838 3834 3839 /** Write to MMIO memory. */ 3835 static void remR3MMIOWriteU32(void *pvVM, target_phys_addr_t GCPhys, uint32_t u32) 3836 { 3837 int rc; 3840 static void remR3MMIOWriteU32(void *pvEnv, target_phys_addr_t GCPhys, uint32_t u32) 3841 { 3842 CPUX86State *env = (CPUX86State *)pvEnv; 3843 int rc; 3838 3844 Log2(("remR3MMIOWriteU32: GCPhys=%RGp u32=%#x\n", (RTGCPHYS)GCPhys, u32)); 3839 rc = IOMMMIOWrite( (PVM)pvVM, GCPhys, u32, 4);3845 rc = IOMMMIOWrite(env->pVM, env->pVCpu, GCPhys, u32, 4); 3840 3846 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc); 3841 3847 } … … 4557 4563 Log2(("cpu_outb: addr=%#06x val=%#x\n", addr, val)); 4558 4564 4559 rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 1);4565 rc = IOMIOPortWrite(env->pVM, env->pVCpu, (RTIOPORT)addr, val, 1); 4560 4566 if (RT_LIKELY(rc == VINF_SUCCESS)) 4561 4567 return; … … 4572 4578 { 4573 4579 //Log2(("cpu_outw: addr=%#06x val=%#x\n", addr, val)); 4574 int rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 2);4580 int rc = IOMIOPortWrite(env->pVM, env->pVCpu, (RTIOPORT)addr, val, 2); 4575 4581 if (RT_LIKELY(rc == VINF_SUCCESS)) 4576 4582 return; … … 4588 4594 int rc; 4589 4595 Log2(("cpu_outl: addr=%#06x val=%#x\n", addr, val)); 4590 rc = IOMIOPortWrite(env->pVM, (RTIOPORT)addr, val, 4);4596 rc = IOMIOPortWrite(env->pVM, env->pVCpu, (RTIOPORT)addr, val, 4); 4591 4597 if (RT_LIKELY(rc == VINF_SUCCESS)) 4592 4598 return; … … 4603 4609 { 4604 4610 uint32_t u32 = 0; 4605 int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 1);4611 int rc = IOMIOPortRead(env->pVM, env->pVCpu, (RTIOPORT)addr, &u32, 1); 4606 4612 if (RT_LIKELY(rc == VINF_SUCCESS)) 4607 4613 { … … 4623 4629 { 4624 4630 uint32_t u32 = 0; 4625 int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 2);4631 int rc = IOMIOPortRead(env->pVM, env->pVCpu, (RTIOPORT)addr, &u32, 2); 4626 4632 if (RT_LIKELY(rc == VINF_SUCCESS)) 4627 4633 { … … 4642 4648 { 4643 4649 uint32_t u32 = 0; 4644 int rc = IOMIOPortRead(env->pVM, (RTIOPORT)addr, &u32, 4);4650 int rc = IOMIOPortRead(env->pVM, env->pVCpu, (RTIOPORT)addr, &u32, 4); 4645 4651 if (RT_LIKELY(rc == VINF_SUCCESS)) 4646 4652 {
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