Index: /trunk/include/VBox/vmm/hm_vmx.h =================================================================== --- /trunk/include/VBox/vmm/hm_vmx.h (revision 43802) +++ /trunk/include/VBox/vmm/hm_vmx.h (revision 43803) @@ -659,32 +659,32 @@ -/** @name MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR - * @{ - */ -#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0) -#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1) -#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2) -#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3) -#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4) -#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5) -#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6) -#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7) -#define MSR_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8) -#define MSR_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9) -#define MSR_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12) -#define MSR_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13) -#define MSR_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14) -#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16) -#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17) -#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18) -#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19) -#define MSR_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20) -#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_SINGLE_CONTEXT RT_BIT_64(25) -#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL_CONTEXTS RT_BIT_64(26) -#define MSR_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32) -#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR RT_BIT_64(40) -#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT RT_BIT_64(41) -#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL_CONTEXTS RT_BIT_64(42) -#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43) +/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR + * @{ + */ +#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0) +#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY RT_BIT_64(1) +#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY RT_BIT_64(2) +#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS RT_BIT_64(3) +#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS RT_BIT_64(4) +#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS RT_BIT_64(5) +#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS RT_BIT_64(6) +#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS RT_BIT_64(7) +#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8) +#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC RT_BIT_64(9) +#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT RT_BIT_64(12) +#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP RT_BIT_64(13) +#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14) +#define MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS RT_BIT_64(16) +#define MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS RT_BIT_64(17) +#define MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS RT_BIT_64(18) +#define MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS RT_BIT_64(19) +#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20) +#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25) +#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26) +#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32) +#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40) +#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41) +#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42) +#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43) /** @} */ Index: /trunk/include/iprt/x86.h =================================================================== --- /trunk/include/iprt/x86.h (revision 43802) +++ /trunk/include/iprt/x86.h (revision 43803) @@ -1020,5 +1020,5 @@ #define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B /** EPT capabilities. */ -#define MSR_IA32_VMX_EPT_CAPS 0x48C +#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C /** DS Save Area (R/W). */ #define MSR_IA32_DS_AREA 0x600 Index: /trunk/src/VBox/VMM/VMMR0/HMR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HMR0.cpp (revision 43802) +++ /trunk/src/VBox/VMM/VMMR0/HMR0.cpp (revision 43803) @@ -136,5 +136,5 @@ uint64_t vmx_cr4_fixed1; uint64_t vmx_vmcs_enum; - uint64_t vmx_eptcaps; + uint64_t vmx_ept_vpid_caps; } msr; /* Last instruction error */ @@ -426,5 +426,7 @@ if ( g_HvmR0.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT | VMX_VMCS_CTRL_PROC_EXEC2_VPID)) - g_HvmR0.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS); + { + g_HvmR0.vmx.msr.vmx_ept_vpid_caps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP); + } } @@ -1213,5 +1215,5 @@ pVM->hm.s.vmx.msr.vmx_cr4_fixed1 = g_HvmR0.vmx.msr.vmx_cr4_fixed1; pVM->hm.s.vmx.msr.vmx_vmcs_enum = g_HvmR0.vmx.msr.vmx_vmcs_enum; - pVM->hm.s.vmx.msr.vmx_eptcaps = g_HvmR0.vmx.msr.vmx_eptcaps; + pVM->hm.s.vmx.msr.vmx_ept_vpid_caps = g_HvmR0.vmx.msr.vmx_ept_vpid_caps; pVM->hm.s.svm.msrHwcr = g_HvmR0.svm.msrHwcr; pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev; Index: /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (revision 43802) +++ /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (revision 43803) @@ -166,5 +166,5 @@ if ( pVM && pVM->hm.s.vmx.fVpid - && (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL_CONTEXTS)) + && (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS)) { hmR0VmxFlushVPID(pVM, NULL /* pvCpu */, VMX_FLUSH_VPID_ALL_CONTEXTS, 0 /* GCPtr */); @@ -431,9 +431,9 @@ if (pVM->hm.s.fNestedPaging) { - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT) - { - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_SINGLE_CONTEXT) + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT) + { + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT) pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_SINGLE_CONTEXT; - else if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL_CONTEXTS) + else if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS) pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_ALL_CONTEXTS; else @@ -460,9 +460,9 @@ if (pVM->hm.s.vmx.fVpid) { - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID) - { - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT) + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID) + { + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT) pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_SINGLE_CONTEXT; - else if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL_CONTEXTS) + else if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS) pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_ALL_CONTEXTS; else @@ -472,7 +472,7 @@ * We do not handle other flush type combinations, ignore VPID capabilities. */ - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR) + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR) Log(("VMXR0SetupVM: Only VMX_FLUSH_VPID_INDIV_ADDR supported. Ignoring VPID.\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT_RETAIN_GLOBALS) + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS) Log(("VMXR0SetupVM: Only VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS supported. Ignoring VPID.\n")); pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_NOT_SUPPORTED; @@ -2552,5 +2552,5 @@ else { - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT) + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT) hmR0VmxFlushVPID(pVM, pVCpu, VMX_FLUSH_VPID_SINGLE_CONTEXT, 0 /* GCPtr */); else @@ -2579,5 +2579,5 @@ * as supported by the CPU. */ - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR) + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR) { for (unsigned i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++) @@ -2742,5 +2742,5 @@ * as supported by the CPU. */ - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR) + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR) { for (unsigned i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++) @@ -5101,5 +5101,5 @@ { /* If we can flush just this page do it, otherwise flush as little as possible. */ - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR) + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR) hmR0VmxFlushVPID(pVM, pVCpu, VMX_FLUSH_VPID_INDIV_ADDR, GCVirt); else Index: /trunk/src/VBox/VMM/VMMR3/HM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/HM.cpp (revision 43802) +++ /trunk/src/VBox/VMM/VMMR3/HM.cpp (revision 43803) @@ -1049,58 +1049,58 @@ LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps) + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps) { - LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hm.s.vmx.msr.vmx_eptcaps)); - - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_SINGLE_CONTEXT) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_SINGLE_CONTEXT\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL_CONTEXTS) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL_CONTEXTS\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL_CONTEXTS) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL_CONTEXTS\n")); - if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT_RETAIN_GLOBALS) - LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT_RETAIN_GLOBALS\n")); + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %RX64\n", pVM->hm.s.vmx.msr.vmx_ept_vpid_caps)); + + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVEPT\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS\n")); + if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS) + LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n")); } Index: /trunk/src/VBox/VMM/include/HMInternal.h =================================================================== --- /trunk/src/VBox/VMM/include/HMInternal.h (revision 43802) +++ /trunk/src/VBox/VMM/include/HMInternal.h (revision 43803) @@ -357,5 +357,5 @@ uint64_t vmx_cr4_fixed1; uint64_t vmx_vmcs_enum; - uint64_t vmx_eptcaps; + uint64_t vmx_ept_vpid_caps; } msr;