Index: /trunk/include/VBox/vmm/hm_vmx.h =================================================================== --- /trunk/include/VBox/vmm/hm_vmx.h (revision 43699) +++ /trunk/include/VBox/vmm/hm_vmx.h (revision 43700) @@ -735,10 +735,10 @@ * @{ */ -#define VMX_VMCS_HOST_FIELD_PAT_FULL 0x2C00 -#define VMX_VMCS_HOST_FIELD_PAT_HIGH 0x2C01 -#define VMX_VMCS_HOST_FIELD_EFER_FULL 0x2C02 -#define VMX_VMCS_HOST_FIELD_EFER_HIGH 0x2C03 -#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /**< MSR IA32_PERF_GLOBAL_CTRL */ -#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /**< MSR IA32_PERF_GLOBAL_CTRL */ +#define VMX_VMCS64_HOST_FIELD_PAT_FULL 0x2C00 +#define VMX_VMCS64_HOST_FIELD_PAT_HIGH 0x2C01 +#define VMX_VMCS64_HOST_FIELD_EFER_FULL 0x2C02 +#define VMX_VMCS64_HOST_FIELD_EFER_HIGH 0x2C03 +#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /**< MSR IA32_PERF_GLOBAL_CTRL */ +#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /**< MSR IA32_PERF_GLOBAL_CTRL */ /** @} */ @@ -747,42 +747,50 @@ * @{ */ -#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000 -#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001 -#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002 -#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003 +#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000 +#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001 +#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002 +#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003 /* Optional */ -#define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004 -#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005 - -#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006 -#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007 -#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008 -#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009 - -#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A -#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B - -#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C -#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D - -#define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010 -#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011 +#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004 +#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005 + +#define VMX_VMCS64_CTRL_VMEXIT_MSR_STORE_FULL 0x2006 +#define VMX_VMCS64_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007 +#define VMX_VMCS64_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008 +#define VMX_VMCS64_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009 + +#define VMX_VMCS64_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A +#define VMX_VMCS64_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B + +#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C +#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D + +#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010 +#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011 /** Optional (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) */ -#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012 -#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013 +#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012 +#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013 /** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */ -#define VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL 0x2014 -#define VMX_VMCS_CTRL_APIC_ACCESSADDR_HIGH 0x2015 +#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014 +#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015 + +/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */ +#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018 +#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019 /** Extended page table pointer. */ -#define VMX_VMCS_CTRL_EPTP_FULL 0x201a -#define VMX_VMCS_CTRL_EPTP_HIGH 0x201b - -/** VM-exit phyiscal address. */ -#define VMX_VMCS_EXIT_PHYS_ADDR_FULL 0x2400 -#define VMX_VMCS_EXIT_PHYS_ADDR_HIGH 0x2401 +#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a +#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b + +/** Extended page table pointer lists. */ +#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024 +#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025 + +/** VM-exit guest phyiscal address. */ +#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400 +#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401 /** @} */ @@ -791,22 +799,22 @@ * @{ */ -#define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800 -#define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801 -#define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /**< MSR IA32_DEBUGCTL */ -#define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /**< MSR IA32_DEBUGCTL */ -#define VMX_VMCS_GUEST_PAT_FULL 0x2804 -#define VMX_VMCS_GUEST_PAT_HIGH 0x2805 -#define VMX_VMCS_GUEST_EFER_FULL 0x2806 -#define VMX_VMCS_GUEST_EFER_HIGH 0x2807 -#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /**< MSR IA32_PERF_GLOBAL_CTRL */ -#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /**< MSR IA32_PERF_GLOBAL_CTRL */ -#define VMX_VMCS_GUEST_PDPTR0_FULL 0x280A -#define VMX_VMCS_GUEST_PDPTR0_HIGH 0x280B -#define VMX_VMCS_GUEST_PDPTR1_FULL 0x280C -#define VMX_VMCS_GUEST_PDPTR1_HIGH 0x280D -#define VMX_VMCS_GUEST_PDPTR2_FULL 0x280E -#define VMX_VMCS_GUEST_PDPTR2_HIGH 0x280F -#define VMX_VMCS_GUEST_PDPTR3_FULL 0x2810 -#define VMX_VMCS_GUEST_PDPTR3_HIGH 0x2811 +#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800 +#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801 +#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802 /**< MSR IA32_DEBUGCTL */ +#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803 /**< MSR IA32_DEBUGCTL */ +#define VMX_VMCS64_GUEST_PAT_FULL 0x2804 +#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805 +#define VMX_VMCS64_GUEST_EFER_FULL 0x2806 +#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807 +#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /**< MSR IA32_PERF_GLOBAL_CTRL */ +#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /**< MSR IA32_PERF_GLOBAL_CTRL */ +#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280A +#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280B +#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280C +#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280D +#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280E +#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280F +#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810 +#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811 /** @} */ @@ -815,22 +823,20 @@ * @{ */ -#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000 -#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002 -#define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004 -#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006 -#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008 -#define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A -#define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C -#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E -#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010 -#define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012 -#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014 -#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016 -#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018 -#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A -/** This field exists only on processors that support the 1-setting of the “use TPR shadow” VM-execution control. */ -#define VMX_VMCS_CTRL_TPR_THRESHOLD 0x401C -/** This field exists only on processors that support the 1-setting of the “activate secondary controls” VM-execution control. */ -#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2 0x401E +#define VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS 0x4000 +#define VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS 0x4002 +#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004 +#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006 +#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008 +#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400A +#define VMX_VMCS32_CTRL_EXIT_CONTROLS 0x400C +#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400E +#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010 +#define VMX_VMCS32_CTRL_ENTRY_CONTROLS 0x4012 +#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014 +#define VMX_VMCS32_CTRL_ENTRY_IRQ_INFO 0x4016 +#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018 +#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401A +#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401C +#define VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS2 0x401E /** @} */ @@ -918,4 +924,10 @@ /** A specified nr of pause loops cause a VM-exit. */ #define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10) +/** VM Exit when executing RDRAND instructions. */ +#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT RT_BIT(11) +/** Enables INVPCID instructions. */ +#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID RT_BIT(12) +/** Enables VMFUNC instructions. */ +#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC RT_BIT(13) /** @} */ @@ -1250,24 +1262,24 @@ * @{ */ -#define VMX_VMCS64_GUEST_CR0 0x6800 -#define VMX_VMCS64_GUEST_CR3 0x6802 -#define VMX_VMCS64_GUEST_CR4 0x6804 -#define VMX_VMCS64_GUEST_ES_BASE 0x6806 -#define VMX_VMCS64_GUEST_CS_BASE 0x6808 -#define VMX_VMCS64_GUEST_SS_BASE 0x680A -#define VMX_VMCS64_GUEST_DS_BASE 0x680C -#define VMX_VMCS64_GUEST_FS_BASE 0x680E -#define VMX_VMCS64_GUEST_GS_BASE 0x6810 -#define VMX_VMCS64_GUEST_LDTR_BASE 0x6812 -#define VMX_VMCS64_GUEST_TR_BASE 0x6814 -#define VMX_VMCS64_GUEST_GDTR_BASE 0x6816 -#define VMX_VMCS64_GUEST_IDTR_BASE 0x6818 -#define VMX_VMCS64_GUEST_DR7 0x681A -#define VMX_VMCS64_GUEST_RSP 0x681C -#define VMX_VMCS64_GUEST_RIP 0x681E -#define VMX_VMCS_GUEST_RFLAGS 0x6820 -#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822 -#define VMX_VMCS64_GUEST_SYSENTER_ESP 0x6824 /**< MSR IA32_SYSENTER_ESP */ -#define VMX_VMCS64_GUEST_SYSENTER_EIP 0x6826 /**< MSR IA32_SYSENTER_EIP */ +#define VMX_VMCS_GUEST_CR0 0x6800 +#define VMX_VMCS_GUEST_CR3 0x6802 +#define VMX_VMCS_GUEST_CR4 0x6804 +#define VMX_VMCS_GUEST_ES_BASE 0x6806 +#define VMX_VMCS_GUEST_CS_BASE 0x6808 +#define VMX_VMCS_GUEST_SS_BASE 0x680A +#define VMX_VMCS_GUEST_DS_BASE 0x680C +#define VMX_VMCS_GUEST_FS_BASE 0x680E +#define VMX_VMCS_GUEST_GS_BASE 0x6810 +#define VMX_VMCS_GUEST_LDTR_BASE 0x6812 +#define VMX_VMCS_GUEST_TR_BASE 0x6814 +#define VMX_VMCS_GUEST_GDTR_BASE 0x6816 +#define VMX_VMCS_GUEST_IDTR_BASE 0x6818 +#define VMX_VMCS_GUEST_DR7 0x681A +#define VMX_VMCS_GUEST_RSP 0x681C +#define VMX_VMCS_GUEST_RIP 0x681E +#define VMX_VMCS_GUEST_RFLAGS 0x6820 +#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822 +#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /**< MSR IA32_SYSENTER_ESP */ +#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /**< MSR IA32_SYSENTER_EIP */ /** @} */ Index: /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (revision 43699) +++ /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (revision 43700) @@ -528,5 +528,5 @@ val &= pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1; - rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS, val); AssertRC(rc); @@ -582,5 +582,5 @@ pVCpu->hm.s.vmx.proc_ctls = val; - rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, val); AssertRC(rc); @@ -613,5 +613,5 @@ val &= pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1; pVCpu->hm.s.vmx.proc_ctls2 = val; - rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS2, val); AssertRC(rc); } @@ -621,5 +621,5 @@ * Set required bits to one and zero according to the MSR capabilities. */ - rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, 0); AssertRC(rc); @@ -641,14 +641,14 @@ * Don't filter page faults, all of them should cause a world switch. */ - rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, 0); AssertRC(rc); - rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, 0); AssertRC(rc); - rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0); + rc = VMXWriteVMCS64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, 0); AssertRC(rc); - rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0); + rc = VMXWriteVMCS64(VMX_VMCS64_CTRL_IO_BITMAP_A_FULL, 0); AssertRC(rc); - rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0); + rc = VMXWriteVMCS64(VMX_VMCS64_CTRL_IO_BITMAP_B_FULL, 0); AssertRC(rc); @@ -660,5 +660,5 @@ Assert(pVCpu->hm.s.vmx.HCPhysMsrBitmap); - rc = VMXWriteVMCS64(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVCpu->hm.s.vmx.HCPhysMsrBitmap); + rc = VMXWriteVMCS64(VMX_VMCS64_CTRL_MSR_BITMAP_FULL, pVCpu->hm.s.vmx.HCPhysMsrBitmap); AssertRC(rc); @@ -685,18 +685,18 @@ */ Assert(pVCpu->hm.s.vmx.HCPhysGuestMsr); - rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr); + rc = VMXWriteVMCS64(VMX_VMCS64_CTRL_VMENTRY_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr); AssertRC(rc); - rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr); + rc = VMXWriteVMCS64(VMX_VMCS64_CTRL_VMEXIT_MSR_STORE_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr); AssertRC(rc); Assert(pVCpu->hm.s.vmx.HCPhysHostMsr); - rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysHostMsr); + rc = VMXWriteVMCS64(VMX_VMCS64_CTRL_VMEXIT_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysHostMsr); AssertRC(rc); #endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */ - rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT, 0); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, 0); AssertRC(rc); - rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, 0); AssertRC(rc); - rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, 0); AssertRC(rc); @@ -705,9 +705,9 @@ Assert(pVM->hm.s.vmx.hMemObjApicAccess); /* Optional */ - rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0); - rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hm.s.vmx.HCPhysVAPIC); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_TPR_THRESHOLD, 0); + rc |= VMXWriteVMCS64(VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hm.s.vmx.HCPhysVAPIC); if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) - rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL, pVM->hm.s.vmx.HCPhysApicAccess); + rc |= VMXWriteVMCS64(VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL, pVM->hm.s.vmx.HCPhysApicAccess); AssertRC(rc); @@ -715,5 +715,5 @@ /* Set link pointer to -1. Not currently used. */ - rc = VMXWriteVMCS64(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL); + rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL); AssertRC(rc); @@ -730,20 +730,20 @@ PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache; - VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RIP); - VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RSP); + VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RIP); + VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RSP); VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RFLAGS); VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE); VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW); - VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR0); + VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_CR0); VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW); - VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR4); - VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_DR7); + VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_CR4); + VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_DR7); VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_SYSENTER_CS); - VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_EIP); - VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_ESP); + VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_SYSENTER_EIP); + VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_SYSENTER_ESP); VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT); - VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_GDTR_BASE); + VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_GDTR_BASE); VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT); - VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_IDTR_BASE); + VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_IDTR_BASE); VMX_SETUP_SELREG(ES, pCache); @@ -771,6 +771,6 @@ if (pVM->hm.s.fNestedPaging) { - VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR3); - VMXSetupCachedReadVMCS(pCache, VMX_VMCS_EXIT_PHYS_ADDR_FULL); + VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_CR3); + VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL); pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX; } @@ -974,7 +974,7 @@ * Set event injection state. */ - rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)); - rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr); - rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)); + rc |= VMXWriteVMCS(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, cbInstr); + rc |= VMXWriteVMCS(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode); AssertRC(rc); @@ -1044,5 +1044,5 @@ LogFlow(("Enable irq window exit!\n")); pVCpu->hm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT; - rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); AssertRC(rc); } @@ -1460,5 +1460,5 @@ /** @todo r=ramshankar: check IA32_VMX_MISC bits 27:25 for valid idxMsr * range. */ - rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, idxMsr); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, idxMsr); AssertRC(rc); #endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */ @@ -1486,8 +1486,8 @@ AssertRCReturn(rc, rc); - rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL, aPdpes[0].u); AssertRCReturn(rc, rc); - rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR1_FULL, aPdpes[1].u); AssertRCReturn(rc, rc); - rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR2_FULL, aPdpes[2].u); AssertRCReturn(rc, rc); - rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR3_FULL, aPdpes[3].u); AssertRCReturn(rc, rc); + rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_PDPTE0_FULL, aPdpes[0].u); AssertRCReturn(rc, rc); + rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_PDPTE1_FULL, aPdpes[1].u); AssertRCReturn(rc, rc); + rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_PDPTE2_FULL, aPdpes[2].u); AssertRCReturn(rc, rc); + rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_PDPTE3_FULL, aPdpes[3].u); AssertRCReturn(rc, rc); } return VINF_SUCCESS; @@ -1511,8 +1511,8 @@ int rc; X86PDPE aPdpes[4]; - rc = VMXReadVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL, &aPdpes[0].u); AssertRCReturn(rc, rc); - rc = VMXReadVMCS64(VMX_VMCS_GUEST_PDPTR1_FULL, &aPdpes[1].u); AssertRCReturn(rc, rc); - rc = VMXReadVMCS64(VMX_VMCS_GUEST_PDPTR2_FULL, &aPdpes[2].u); AssertRCReturn(rc, rc); - rc = VMXReadVMCS64(VMX_VMCS_GUEST_PDPTR3_FULL, &aPdpes[3].u); AssertRCReturn(rc, rc); + rc = VMXReadVMCS64(VMX_VMCS64_GUEST_PDPTE0_FULL, &aPdpes[0].u); AssertRCReturn(rc, rc); + rc = VMXReadVMCS64(VMX_VMCS64_GUEST_PDPTE1_FULL, &aPdpes[1].u); AssertRCReturn(rc, rc); + rc = VMXReadVMCS64(VMX_VMCS64_GUEST_PDPTE2_FULL, &aPdpes[2].u); AssertRCReturn(rc, rc); + rc = VMXReadVMCS64(VMX_VMCS64_GUEST_PDPTE3_FULL, &aPdpes[3].u); AssertRCReturn(rc, rc); rc = PGMGstUpdatePaePdpes(pVCpu, &aPdpes[0]); @@ -1599,5 +1599,5 @@ } - int rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, u32TrapMask); + int rc = VMXWriteVMCS(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, u32TrapMask); AssertRC(rc); } @@ -1623,6 +1623,6 @@ * Load EIP, ESP and EFLAGS. */ - rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_RIP, pCtx->rip); - rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_RSP, pCtx->rsp); + rc = VMXWriteVMCS64(VMX_VMCS_GUEST_RIP, pCtx->rip); + rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_RSP, pCtx->rsp); AssertRC(rc); @@ -1645,5 +1645,5 @@ eflags.Bits.u2IOPL = 0; /* must always be 0 or else certain instructions won't cause faults. */ } - rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32); + rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32); AssertRC(rc); } @@ -1685,5 +1685,5 @@ */ val &= pVM->hm.s.vmx.msr.vmx_entry.n.allowed1; - rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_ENTRY_CONTROLS, val); AssertRC(rc); @@ -1715,5 +1715,5 @@ * Don't acknowledge external interrupts on VM-exit. */ - rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_EXIT_CONTROLS, val); AssertRC(rc); @@ -1786,5 +1786,5 @@ rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, 0); rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, 0); - rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, 0); + rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_LDTR_BASE, 0); /* @todo removing "64" in the function should be the same. */ /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */ rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */); @@ -1794,5 +1794,5 @@ rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr.Sel); rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtr.u32Limit); - rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtr.u64Base); + rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtr.u64Base); /* @todo removing "64" and it should be the same */ rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtr.Attr.u); } @@ -1820,5 +1820,5 @@ rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, 0); rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, HM_VTX_TSS_SIZE); - rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */); + rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */); X86DESCATTR attr; @@ -1833,5 +1833,5 @@ rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr.Sel); rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->tr.u32Limit); - rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->tr.u64Base); + rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_TR_BASE, pCtx->tr.u64Base); val = pCtx->tr.Attr.u; @@ -1859,5 +1859,5 @@ { rc = VMXWriteVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt); - rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_GDTR_BASE, pCtx->gdtr.pGdt); + rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt); AssertRC(rc); } @@ -1869,5 +1869,5 @@ { rc = VMXWriteVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt); - rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_IDTR_BASE, pCtx->idtr.pIdt); + rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt); AssertRC(rc); } @@ -1879,6 +1879,6 @@ { rc = VMXWriteVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs); - rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip); - rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp); + rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip); + rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp); AssertRC(rc); } @@ -1923,5 +1923,5 @@ | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT; } - rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); AssertRC(rc); } @@ -1935,5 +1935,5 @@ val &= ~(X86_CR0_CD|X86_CR0_NW); - rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR0, val); + rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_CR0, val); Log2(("Guest CR0 %08x\n", val)); @@ -2015,5 +2015,5 @@ } - rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR4, val); + rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_CR4, val); Log2(("Guest CR4 %08x\n", val)); @@ -2057,5 +2057,5 @@ | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT); - rc = VMXWriteVMCS64(VMX_VMCS_CTRL_EPTP_FULL, pVCpu->hm.s.vmx.GCPhysEPTP); + rc = VMXWriteVMCS64(VMX_VMCS64_CTRL_EPTP_FULL, pVCpu->hm.s.vmx.GCPhysEPTP); AssertRC(rc); @@ -2090,5 +2090,5 @@ /* Save our shadow CR3 register. */ - rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_CR3, val); + rc = VMXWriteVMCS64(VMX_VMCS_GUEST_CR3, val); AssertRC(rc); } @@ -2107,5 +2107,5 @@ /* Resync DR7 */ - rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]); + rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DR7, pCtx->dr[7]); AssertRC(rc); @@ -2123,5 +2123,5 @@ /* Override dr7 with the hypervisor value. */ - rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, CPUMGetHyperDR7(pVCpu)); + rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DR7, CPUMGetHyperDR7(pVCpu)); AssertRC(rc); } @@ -2137,5 +2137,5 @@ /* Disable DRx move intercepts. */ pVCpu->hm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT; - rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); AssertRC(rc); @@ -2146,5 +2146,5 @@ /* IA32_DEBUGCTL MSR. */ - rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0); + rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, 0); AssertRC(rc); @@ -2173,7 +2173,7 @@ { /* Update these as wrmsr might have changed them. */ - rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fs.u64Base); + rc = VMXWriteVMCS64(VMX_VMCS_GUEST_FS_BASE, pCtx->fs.u64Base); AssertRC(rc); - rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gs.u64Base); + rc = VMXWriteVMCS64(VMX_VMCS_GUEST_GS_BASE, pCtx->gs.u64Base); AssertRC(rc); } @@ -2247,8 +2247,8 @@ pVCpu->hm.s.vmx.cCachedMsrs = idxMsr; - rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT, idxMsr); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, idxMsr); AssertRC(rc); - rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, idxMsr); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, idxMsr); AssertRC(rc); #endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */ @@ -2279,9 +2279,9 @@ { /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET, applies to RDTSCP too. */ - rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, pVCpu->hm.s.vmx.u64TSCOffset); + rc = VMXWriteVMCS64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, pVCpu->hm.s.vmx.u64TSCOffset); AssertRC(rc); pVCpu->hm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT; - rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); AssertRC(rc); STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset); @@ -2295,5 +2295,5 @@ TMCpuTickGet(pVCpu))); pVCpu->hm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT; - rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); AssertRC(rc); STAM_COUNTER_INC(&pVCpu->hm.s.StatTscInterceptOverFlow); @@ -2303,5 +2303,5 @@ { pVCpu->hm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT; - rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); AssertRC(rc); STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept); @@ -2332,8 +2332,8 @@ /* First sync back EIP, ESP, and EFLAGS. */ - rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP, &val); + rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RIP, &val); AssertRC(rc); pCtx->rip = val; - rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP, &val); + rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RSP, &val); AssertRC(rc); pCtx->rsp = val; @@ -2356,10 +2356,10 @@ /* Control registers. */ VMXReadCachedVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow); - VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR0, &val); + VMXReadCachedVMCS(VMX_VMCS_GUEST_CR0, &val); val = (valShadow & pVCpu->hm.s.vmx.cr0_mask) | (val & ~pVCpu->hm.s.vmx.cr0_mask); CPUMSetGuestCR0(pVCpu, val); VMXReadCachedVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow); - VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR4, &val); + VMXReadCachedVMCS(VMX_VMCS_GUEST_CR4, &val); val = (valShadow & pVCpu->hm.s.vmx.cr4_mask) | (val & ~pVCpu->hm.s.vmx.cr4_mask); CPUMSetGuestCR4(pVCpu, val); @@ -2377,5 +2377,5 @@ CPUMSetGuestCR2(pVCpu, pCache->cr2); - VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR3, &val); + VMXReadCachedVMCS(VMX_VMCS_GUEST_CR3, &val); if (val != pCtx->cr3) @@ -2389,5 +2389,5 @@ /* Sync back DR7. */ - VMXReadCachedVMCS(VMX_VMCS64_GUEST_DR7, &val); + VMXReadCachedVMCS(VMX_VMCS_GUEST_DR7, &val); pCtx->dr[7] = val; @@ -2403,7 +2403,7 @@ VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, &val); pCtx->SysEnter.cs = val; - VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_EIP, &val); + VMXReadCachedVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val); pCtx->SysEnter.eip = val; - VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_ESP, &val); + VMXReadCachedVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val); pCtx->SysEnter.esp = val; @@ -2413,10 +2413,10 @@ VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, &val); pCtx->gdtr.cbGdt = val; - VMXReadCachedVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val); + VMXReadCachedVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val); pCtx->gdtr.pGdt = val; VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, &val); pCtx->idtr.cbIdt = val; - VMXReadCachedVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val); + VMXReadCachedVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val); pCtx->idtr.pIdt = val; @@ -2835,5 +2835,5 @@ * originated before a VM reset *after* the VM has been reset. See @bugref{6220}. */ - VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, 0); + VMXWriteVMCS(VMX_VMCS32_CTRL_ENTRY_IRQ_INFO, 0); #ifdef VBOX_STRICT @@ -2841,5 +2841,5 @@ RTCCUINTREG val2; - rc2 = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val2); + rc2 = VMXReadVMCS(VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS, &val2); AssertRC(rc2); Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val2)); @@ -2853,5 +2853,5 @@ Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n")); - rc2 = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val2); + rc2 = VMXReadVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, &val2); AssertRC(rc2); Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val2)); @@ -2875,5 +2875,5 @@ Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n")); - rc2 = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val2); + rc2 = VMXReadVMCS(VMX_VMCS32_CTRL_ENTRY_CONTROLS, &val2); AssertRC(rc2); Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val2)); @@ -2887,5 +2887,5 @@ Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n")); - rc2 = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val2); + rc2 = VMXReadVMCS(VMX_VMCS32_CTRL_EXIT_CONTROLS, &val2); AssertRC(rc2); Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val2)); @@ -3081,5 +3081,5 @@ /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */ - rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? (u8LastTPR >> 4) : 0); + rc = VMXWriteVMCS(VMX_VMCS32_CTRL_TPR_THRESHOLD, (fPending) ? (u8LastTPR >> 4) : 0); AssertRC(VBOXSTRICTRC_VAL(rc)); @@ -3408,9 +3408,4 @@ { Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ); -#if 0 //def VBOX_WITH_VMMR0_DISABLE_PREEMPTION - if ( RTThreadPreemptIsPendingTrusty() - && !RTThreadPreemptIsPending(NIL_RTTHREAD)) - goto ResumeExecution; -#endif /* External interrupt; leave to allow it to be dispatched again. */ rc = VINF_EM_RAW_INTERRUPT; @@ -3655,5 +3650,5 @@ /* Resync DR7 */ - rc2 = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]); + rc2 = VMXWriteVMCS64(VMX_VMCS_GUEST_DR7, pCtx->dr[7]); AssertRC(rc2); @@ -4024,5 +4019,5 @@ Assert(pVM->hm.s.fNestedPaging); - rc2 = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys); + rc2 = VMXReadVMCS64(VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL, &GCPhys); AssertRC(rc2); Assert(((exitQualification >> 7) & 3) != 2); @@ -4098,5 +4093,5 @@ Assert(pVM->hm.s.fNestedPaging); - rc2 = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys); + rc2 = VMXReadVMCS64(VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL, &GCPhys); AssertRC(rc2); Log(("VMX_EXIT_EPT_MISCONFIG for %RGp\n", GCPhys)); @@ -4144,5 +4139,5 @@ VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF)); pVCpu->hm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT; - rc2 = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); + rc2 = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); AssertRC(rc2); STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIrqWindow); @@ -4399,5 +4394,5 @@ /* Disable DRx move intercepts. */ pVCpu->hm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT; - rc2 = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); + rc2 = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); AssertRC(rc2); @@ -4589,5 +4584,5 @@ /* Resync DR7 */ - rc2 = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]); + rc2 = VMXWriteVMCS64(VMX_VMCS_GUEST_DR7, pCtx->dr[7]); AssertRC(rc2); @@ -4765,5 +4760,5 @@ LogFlow(("VMX_EXIT_MTF at %RGv\n", (RTGCPTR)pCtx->rip)); pVCpu->hm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG; - rc2 = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); + rc2 = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); AssertRC(rc2); STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMtf); @@ -4836,14 +4831,14 @@ Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n")); - VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val2); + VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val2); Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val2)); - VMXReadVMCS(VMX_VMCS64_GUEST_CR0, &val2); + VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val2); Log(("VMX_VMCS_GUEST_CR0 %RX64\n", (uint64_t)val2)); - VMXReadVMCS(VMX_VMCS64_GUEST_CR3, &val2); + VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val2); Log(("VMX_VMCS_GUEST_CR3 %RX64\n", (uint64_t)val2)); - VMXReadVMCS(VMX_VMCS64_GUEST_CR4, &val2); + VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val2); Log(("VMX_VMCS_GUEST_CR4 %RX64\n", (uint64_t)val2)); @@ -4860,7 +4855,7 @@ VMX_LOG_SELREG(LDTR, "LDTR", val2); - VMXReadVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val2); + VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val2); Log(("VMX_VMCS_GUEST_GDTR_BASE %RX64\n", (uint64_t)val2)); - VMXReadVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val2); + VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val2); Log(("VMX_VMCS_GUEST_IDTR_BASE %RX64\n", (uint64_t)val2)); #endif /* VBOX_STRICT */ @@ -5000,5 +4995,5 @@ /* Enable DRx move intercepts again. */ pVCpu->hm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT; - int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); + int rc = VMXWriteVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.proc_ctls); AssertRC(rc); @@ -5191,13 +5186,13 @@ ASMGetGDTR(&gdtr); - VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val); + VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val); Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val)); - VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val); + VMXReadVMCS(VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS, &val); Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val)); - VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val); + VMXReadVMCS(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, &val); Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val)); - VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val); + VMXReadVMCS(VMX_VMCS32_CTRL_ENTRY_CONTROLS, &val); Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val)); - VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val); + VMXReadVMCS(VMX_VMCS32_CTRL_EXIT_CONTROLS, &val); Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val)); @@ -5387,43 +5382,43 @@ switch (idxField) { - case VMX_VMCS64_GUEST_RIP: - case VMX_VMCS64_GUEST_RSP: + case VMX_VMCS_GUEST_RIP: + case VMX_VMCS_GUEST_RSP: case VMX_VMCS_GUEST_RFLAGS: case VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE: case VMX_VMCS_CTRL_CR0_READ_SHADOW: - case VMX_VMCS64_GUEST_CR0: + case VMX_VMCS_GUEST_CR0: case VMX_VMCS_CTRL_CR4_READ_SHADOW: - case VMX_VMCS64_GUEST_CR4: - case VMX_VMCS64_GUEST_DR7: + case VMX_VMCS_GUEST_CR4: + case VMX_VMCS_GUEST_DR7: case VMX_VMCS32_GUEST_SYSENTER_CS: - case VMX_VMCS64_GUEST_SYSENTER_EIP: - case VMX_VMCS64_GUEST_SYSENTER_ESP: + case VMX_VMCS_GUEST_SYSENTER_EIP: + case VMX_VMCS_GUEST_SYSENTER_ESP: case VMX_VMCS32_GUEST_GDTR_LIMIT: case VMX_VMCS64_GUEST_GDTR_BASE: case VMX_VMCS32_GUEST_IDTR_LIMIT: - case VMX_VMCS64_GUEST_IDTR_BASE: + case VMX_VMCS_GUEST_IDTR_BASE: case VMX_VMCS16_GUEST_FIELD_CS: case VMX_VMCS32_GUEST_CS_LIMIT: - case VMX_VMCS64_GUEST_CS_BASE: + case VMX_VMCS_GUEST_CS_BASE: case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS: case VMX_VMCS16_GUEST_FIELD_DS: case VMX_VMCS32_GUEST_DS_LIMIT: - case VMX_VMCS64_GUEST_DS_BASE: + case VMX_VMCS_GUEST_DS_BASE: case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS: case VMX_VMCS16_GUEST_FIELD_ES: case VMX_VMCS32_GUEST_ES_LIMIT: - case VMX_VMCS64_GUEST_ES_BASE: + case VMX_VMCS_GUEST_ES_BASE: case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS: case VMX_VMCS16_GUEST_FIELD_FS: case VMX_VMCS32_GUEST_FS_LIMIT: - case VMX_VMCS64_GUEST_FS_BASE: + case VMX_VMCS_GUEST_FS_BASE: case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS: case VMX_VMCS16_GUEST_FIELD_GS: case VMX_VMCS32_GUEST_GS_LIMIT: - case VMX_VMCS64_GUEST_GS_BASE: + case VMX_VMCS_GUEST_GS_BASE: case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS: case VMX_VMCS16_GUEST_FIELD_SS: case VMX_VMCS32_GUEST_SS_LIMIT: - case VMX_VMCS64_GUEST_SS_BASE: + case VMX_VMCS_GUEST_SS_BASE: case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS: case VMX_VMCS16_GUEST_FIELD_LDTR: @@ -5433,5 +5428,5 @@ case VMX_VMCS16_GUEST_FIELD_TR: case VMX_VMCS32_GUEST_TR_LIMIT: - case VMX_VMCS64_GUEST_TR_BASE: + case VMX_VMCS_GUEST_TR_BASE: case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS: case VMX_VMCS32_RO_EXIT_REASON: @@ -5444,6 +5439,6 @@ case VMX_VMCS32_RO_IDT_INFO: case VMX_VMCS32_RO_IDT_ERRCODE: - case VMX_VMCS64_GUEST_CR3: - case VMX_VMCS_EXIT_PHYS_ADDR_FULL: + case VMX_VMCS_GUEST_CR3: + case VMX_VMCS_EXIT_GUEST_PHYS_ADDR_FULL: return true; } @@ -5578,21 +5573,21 @@ switch (idxField) { - case VMX_VMCS_CTRL_TSC_OFFSET_FULL: - case VMX_VMCS_CTRL_IO_BITMAP_A_FULL: - case VMX_VMCS_CTRL_IO_BITMAP_B_FULL: - case VMX_VMCS_CTRL_MSR_BITMAP_FULL: - case VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL: - case VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL: - case VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL: - case VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL: - case VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL: - case VMX_VMCS_GUEST_LINK_PTR_FULL: - case VMX_VMCS_GUEST_PDPTR0_FULL: - case VMX_VMCS_GUEST_PDPTR1_FULL: - case VMX_VMCS_GUEST_PDPTR2_FULL: - case VMX_VMCS_GUEST_PDPTR3_FULL: - case VMX_VMCS_GUEST_DEBUGCTL_FULL: - case VMX_VMCS_GUEST_EFER_FULL: - case VMX_VMCS_CTRL_EPTP_FULL: + case VMX_VMCS64_CTRL_TSC_OFFSET_FULL: + case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL: + case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL: + case VMX_VMCS64_CTRL_MSR_BITMAP_FULL: + case VMX_VMCS64_CTRL_VMEXIT_MSR_STORE_FULL: + case VMX_VMCS64_CTRL_VMEXIT_MSR_LOAD_FULL: + case VMX_VMCS64_CTRL_VMENTRY_MSR_LOAD_FULL: + case VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL: + case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL: + case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL: + case VMX_VMCS64_GUEST_PDPTE0_FULL: + case VMX_VMCS64_GUEST_PDPTE1_FULL: + case VMX_VMCS64_GUEST_PDPTE2_FULL: + case VMX_VMCS64_GUEST_PDPTE3_FULL: + case VMX_VMCS64_GUEST_DEBUGCTL_FULL: + case VMX_VMCS64_GUEST_EFER_FULL: + case VMX_VMCS64_CTRL_EPTP_FULL: /* These fields consist of two parts, which are both writable in 32 bits mode. */ rc = VMXWriteVMCS32(idxField, u64Val); @@ -5601,22 +5596,22 @@ return rc; - case VMX_VMCS64_GUEST_LDTR_BASE: - case VMX_VMCS64_GUEST_TR_BASE: - case VMX_VMCS64_GUEST_GDTR_BASE: - case VMX_VMCS64_GUEST_IDTR_BASE: - case VMX_VMCS64_GUEST_SYSENTER_EIP: - case VMX_VMCS64_GUEST_SYSENTER_ESP: - case VMX_VMCS64_GUEST_CR0: - case VMX_VMCS64_GUEST_CR4: - case VMX_VMCS64_GUEST_CR3: - case VMX_VMCS64_GUEST_DR7: - case VMX_VMCS64_GUEST_RIP: - case VMX_VMCS64_GUEST_RSP: - case VMX_VMCS64_GUEST_CS_BASE: - case VMX_VMCS64_GUEST_DS_BASE: - case VMX_VMCS64_GUEST_ES_BASE: - case VMX_VMCS64_GUEST_FS_BASE: - case VMX_VMCS64_GUEST_GS_BASE: - case VMX_VMCS64_GUEST_SS_BASE: + case VMX_VMCS_GUEST_LDTR_BASE: + case VMX_VMCS_GUEST_TR_BASE: + case VMX_VMCS_GUEST_GDTR_BASE: + case VMX_VMCS_GUEST_IDTR_BASE: + case VMX_VMCS_GUEST_SYSENTER_EIP: + case VMX_VMCS_GUEST_SYSENTER_ESP: + case VMX_VMCS_GUEST_CR0: + case VMX_VMCS_GUEST_CR4: + case VMX_VMCS_GUEST_CR3: + case VMX_VMCS_GUEST_DR7: + case VMX_VMCS_GUEST_RIP: + case VMX_VMCS_GUEST_RSP: + case VMX_VMCS_GUEST_CS_BASE: + case VMX_VMCS_GUEST_DS_BASE: + case VMX_VMCS_GUEST_ES_BASE: + case VMX_VMCS_GUEST_FS_BASE: + case VMX_VMCS_GUEST_GS_BASE: + case VMX_VMCS_GUEST_SS_BASE: /* Queue a 64 bits value as we can't set it in 32 bits host mode. */ if (u64Val >> 32ULL) Index: /trunk/src/VBox/VMM/VMMR0/HWVMXR0.h =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HWVMXR0.h (revision 43699) +++ /trunk/src/VBox/VMM/VMMR0/HWVMXR0.h (revision 43700) @@ -37,51 +37,51 @@ /* Read cache indices. */ -#define VMX_VMCS64_GUEST_RIP_CACHE_IDX 0 -#define VMX_VMCS64_GUEST_RSP_CACHE_IDX 1 +#define VMX_VMCS_GUEST_RIP_CACHE_IDX 0 +#define VMX_VMCS_GUEST_RSP_CACHE_IDX 1 #define VMX_VMCS_GUEST_RFLAGS_CACHE_IDX 2 #define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE_CACHE_IDX 3 #define VMX_VMCS_CTRL_CR0_READ_SHADOW_CACHE_IDX 4 -#define VMX_VMCS64_GUEST_CR0_CACHE_IDX 5 +#define VMX_VMCS_GUEST_CR0_CACHE_IDX 5 #define VMX_VMCS_CTRL_CR4_READ_SHADOW_CACHE_IDX 6 -#define VMX_VMCS64_GUEST_CR4_CACHE_IDX 7 -#define VMX_VMCS64_GUEST_DR7_CACHE_IDX 8 +#define VMX_VMCS_GUEST_CR4_CACHE_IDX 7 +#define VMX_VMCS_GUEST_DR7_CACHE_IDX 8 #define VMX_VMCS32_GUEST_SYSENTER_CS_CACHE_IDX 9 -#define VMX_VMCS64_GUEST_SYSENTER_EIP_CACHE_IDX 10 -#define VMX_VMCS64_GUEST_SYSENTER_ESP_CACHE_IDX 11 +#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 10 +#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 11 #define VMX_VMCS32_GUEST_GDTR_LIMIT_CACHE_IDX 12 -#define VMX_VMCS64_GUEST_GDTR_BASE_CACHE_IDX 13 +#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 13 #define VMX_VMCS32_GUEST_IDTR_LIMIT_CACHE_IDX 14 -#define VMX_VMCS64_GUEST_IDTR_BASE_CACHE_IDX 15 +#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 15 #define VMX_VMCS16_GUEST_FIELD_CS_CACHE_IDX 16 #define VMX_VMCS32_GUEST_CS_LIMIT_CACHE_IDX 17 -#define VMX_VMCS64_GUEST_CS_BASE_CACHE_IDX 18 +#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 18 #define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS_CACHE_IDX 19 #define VMX_VMCS16_GUEST_FIELD_DS_CACHE_IDX 20 #define VMX_VMCS32_GUEST_DS_LIMIT_CACHE_IDX 21 -#define VMX_VMCS64_GUEST_DS_BASE_CACHE_IDX 22 +#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 22 #define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS_CACHE_IDX 23 #define VMX_VMCS16_GUEST_FIELD_ES_CACHE_IDX 24 #define VMX_VMCS32_GUEST_ES_LIMIT_CACHE_IDX 25 -#define VMX_VMCS64_GUEST_ES_BASE_CACHE_IDX 26 +#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 26 #define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS_CACHE_IDX 27 #define VMX_VMCS16_GUEST_FIELD_FS_CACHE_IDX 28 #define VMX_VMCS32_GUEST_FS_LIMIT_CACHE_IDX 29 -#define VMX_VMCS64_GUEST_FS_BASE_CACHE_IDX 30 +#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 30 #define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS_CACHE_IDX 31 #define VMX_VMCS16_GUEST_FIELD_GS_CACHE_IDX 32 #define VMX_VMCS32_GUEST_GS_LIMIT_CACHE_IDX 33 -#define VMX_VMCS64_GUEST_GS_BASE_CACHE_IDX 34 +#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 34 #define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS_CACHE_IDX 35 #define VMX_VMCS16_GUEST_FIELD_SS_CACHE_IDX 36 #define VMX_VMCS32_GUEST_SS_LIMIT_CACHE_IDX 37 -#define VMX_VMCS64_GUEST_SS_BASE_CACHE_IDX 38 +#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 38 #define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS_CACHE_IDX 39 #define VMX_VMCS16_GUEST_FIELD_TR_CACHE_IDX 40 #define VMX_VMCS32_GUEST_TR_LIMIT_CACHE_IDX 41 -#define VMX_VMCS64_GUEST_TR_BASE_CACHE_IDX 42 +#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 42 #define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS_CACHE_IDX 43 #define VMX_VMCS16_GUEST_FIELD_LDTR_CACHE_IDX 44 #define VMX_VMCS32_GUEST_LDTR_LIMIT_CACHE_IDX 45 -#define VMX_VMCS64_GUEST_LDTR_BASE_CACHE_IDX 46 +#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 46 #define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS_CACHE_IDX 47 #define VMX_VMCS32_RO_EXIT_REASON_CACHE_IDX 48 @@ -95,7 +95,7 @@ #define VMX_VMCS32_RO_IDT_ERRCODE_CACHE_IDX 56 #define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS32_RO_IDT_ERRCODE_CACHE_IDX+1) -#define VMX_VMCS64_GUEST_CR3_CACHE_IDX 57 -#define VMX_VMCS_EXIT_PHYS_ADDR_FULL_CACHE_IDX 58 -#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_EXIT_PHYS_ADDR_FULL_CACHE_IDX+1) +#define VMX_VMCS_GUEST_CR3_CACHE_IDX 57 +#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL_CACHE_IDX 58 +#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL_CACHE_IDX+1) @@ -211,5 +211,5 @@ rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_##REG, pCtx->reg.Sel); \ rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT, pCtx->reg.u32Limit); \ - rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_##REG##_BASE, pCtx->reg.u64Base); \ + rc |= VMXWriteVMCS64(VMX_VMCS_GUEST_##REG##_BASE, pCtx->reg.u64Base); \ if ((pCtx->eflags.u32 & X86_EFL_VM)) \ { \ @@ -250,5 +250,5 @@ VMXReadCachedVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT, &val); \ pCtx->reg.u32Limit = val; \ - VMXReadCachedVMCS(VMX_VMCS64_GUEST_##REG##_BASE, &val); \ + VMXReadCachedVMCS(VMX_VMCS_GUEST_##REG##_BASE, &val); \ pCtx->reg.u64Base = val; \ VMXReadCachedVMCS(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, &val); \ @@ -264,5 +264,5 @@ VMXReadVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT, &(val)); \ Log(("%s Limit %x\n", szSelReg, (val))); \ - VMXReadVMCS(VMX_VMCS64_GUEST_##REG##_BASE, &(val)); \ + VMXReadVMCS(VMX_VMCS_GUEST_##REG##_BASE, &(val)); \ Log(("%s Base %RX64\n", szSelReg, (uint64_t)(val))); \ VMXReadVMCS(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, &(val)); \ @@ -327,5 +327,5 @@ VMXSetupCachedReadVMCS(pCache, VMX_VMCS16_GUEST_FIELD_##REG); \ VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_##REG##_LIMIT); \ - VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_##REG##_BASE); \ + VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_##REG##_BASE); \ VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS); \ }