Index: /trunk/include/VBox/vmm/cpum.mac =================================================================== --- /trunk/include/VBox/vmm/cpum.mac (revision 43656) +++ /trunk/include/VBox/vmm/cpum.mac (revision 43657) @@ -4,5 +4,5 @@ ; -; Copyright (C) 2006-2010 Oracle Corporation +; Copyright (C) 2006-2012 Oracle Corporation ; ; This file is part of VirtualBox Open Source Edition (OSE), as @@ -194,5 +194,6 @@ .msrSFMASK resb 8 .msrKERNELGSBASE resb 8 - .au32SizePadding resb 32 + .msrApicBase resb 8 + .au32SizePadding resb 24 endstruc @@ -206,2 +207,3 @@ %endif + Index: /trunk/include/VBox/vmm/cpumctx.h =================================================================== --- /trunk/include/VBox/vmm/cpumctx.h (revision 43656) +++ /trunk/include/VBox/vmm/cpumctx.h (revision 43657) @@ -400,8 +400,9 @@ uint64_t msrSFMASK; /**< syscall flag mask. */ uint64_t msrKERNELGSBASE; /**< swapgs exchange value. */ + uint64_t msrApicBase; /**< The local APIC base (IA32_APIC_BASE MSR). */ /** @} */ /** Size padding. */ - uint32_t au32SizePadding[8]; + uint32_t au32SizePadding[6]; } CPUMCTX; #pragma pack() Index: /trunk/include/VBox/vmm/hm_vmx.h =================================================================== --- /trunk/include/VBox/vmm/hm_vmx.h (revision 43656) +++ /trunk/include/VBox/vmm/hm_vmx.h (revision 43657) @@ -429,5 +429,8 @@ struct { + /** Bits set here -must- be set in the correpsonding VM-execution controls. */ uint32_t disallowed0; + /** Bits cleared here -must- be cleared in the corresponding VM-execution + * controls. */ uint32_t allowed1; } n; Index: /trunk/include/VBox/vmm/pdmapi.h =================================================================== --- /trunk/include/VBox/vmm/pdmapi.h (revision 43656) +++ /trunk/include/VBox/vmm/pdmapi.h (revision 43657) @@ -47,6 +47,7 @@ VMMDECL(bool) PDMHasIoApic(PVM pVM); VMMDECL(int) PDMApicHasPendingIrq(PVM pVM, bool *pfPending); -VMMDECL(int) PDMApicSetBase(PVM pVM, uint64_t u64Base); -VMMDECL(int) PDMApicGetBase(PVM pVM, uint64_t *pu64Base); +VMMDECL(int) PDMApicSetBase(PVMCPU pVCpu, uint64_t u64Base); +VMMDECL(int) PDMApicGetBase(PVMCPU pVCpu, uint64_t *pu64Base); +VMMDECL(int) PDMApicGetBaseFromApic(PVMCPU pVCpu, uint64_t *pu64Base); VMMDECL(int) PDMApicSetTPR(PVMCPU pVCpu, uint8_t u8TPR); VMMDECL(int) PDMApicGetTPR(PVMCPU pVCpu, uint8_t *pu8TPR, bool *pfPending); Index: /trunk/include/VBox/vmm/pdmdev.h =================================================================== --- /trunk/include/VBox/vmm/pdmdev.h (revision 43656) +++ /trunk/include/VBox/vmm/pdmdev.h (revision 43657) @@ -1078,7 +1078,8 @@ * @returns Pending interrupt number. * @param pDevIns Device instance of the APIC. + * @param idCpu The VCPU Id. * @param puTagSrc Where to return the tag source. */ - DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc)); + DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t *puTagSrc)); /** @@ -1087,6 +1088,7 @@ * @returns Pending interrupt yes/no * @param pDevIns Device instance of the APIC. - */ - DECLR3CALLBACKMEMBER(bool, pfnHasPendingIrqR3,(PPDMDEVINS pDevIns)); + * @param idCpu The VCPU Id. + */ + DECLR3CALLBACKMEMBER(bool, pfnHasPendingIrqR3,(PPDMDEVINS pDevIns, VMCPUID idCpu)); /** @@ -1094,7 +1096,8 @@ * * @param pDevIns Device instance of the APIC. + * @param idCpu The VCPU Id. * @param u64Base The new base. */ - DECLR3CALLBACKMEMBER(void, pfnSetBaseR3,(PPDMDEVINS pDevIns, uint64_t u64Base)); + DECLR3CALLBACKMEMBER(void, pfnSetBaseR3,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint64_t u64Base)); /** @@ -1103,6 +1106,7 @@ * @returns Current base. * @param pDevIns Device instance of the APIC. - */ - DECLR3CALLBACKMEMBER(uint64_t, pfnGetBaseR3,(PPDMDEVINS pDevIns)); + * @param idCpu The VCPU Id. + */ + DECLR3CALLBACKMEMBER(uint64_t, pfnGetBaseR3,(PPDMDEVINS pDevIns, VMCPUID idCpu)); /** @@ -1110,5 +1114,5 @@ * * @param pDevIns Device instance of the APIC. - * @param idCpu VCPU id + * @param idCpu The VCPU id. * @param u8TPR The new TPR. */ Index: /trunk/src/VBox/Devices/PC/DevAPIC.cpp =================================================================== --- /trunk/src/VBox/Devices/PC/DevAPIC.cpp (revision 43656) +++ /trunk/src/VBox/Devices/PC/DevAPIC.cpp (revision 43657) @@ -461,5 +461,5 @@ { /* for now we assume LAPIC physical id == CPU id */ - return VMCPUID(s->phys_id); + return (VMCPUID)s->phys_id; } @@ -596,9 +596,9 @@ -PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val) +PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, VMCPUID idCpu, uint64_t val) { APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *); Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect))); - APICState *s = getLapic(pDev); /** @todo fix interface */ + APICState *s = getLapicById(pDev, idCpu); Log(("apicSetBase: %016RX64\n", val)); @@ -640,9 +640,9 @@ } -PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns) +PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns, VMCPUID idCpu) { APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *); Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect))); - APICState *s = getLapic(pDev); /** @todo fix interface */ + APICState *s = getLapicById(pDev, idCpu); LogFlow(("apicGetBase: %016llx\n", (uint64_t)s->apicbase)); return s->apicbase; @@ -1229,5 +1229,5 @@ /* Check if the APIC has a pending interrupt/if a TPR change would active one. */ -PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns) +PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns, VMCPUID idCpu) { APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *); @@ -1237,5 +1237,5 @@ /* We don't perform any locking here as that would cause a lot of contention for VT-x/AMD-V. */ - APICState *s = getLapic(pDev); /** @todo fix interface */ + APICState *s = getLapicById(pDev, idCpu); /* @@ -1437,5 +1437,5 @@ -PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns, uint32_t *puTagSrc) +PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t *puTagSrc) { APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *); @@ -1450,5 +1450,5 @@ Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect))); - APICState *s = getLapic(pDev); /** @todo fix interface */ + APICState *s = getLapicById(pDev, idCpu); if (!(s->spurious_vec & APIC_SV_ENABLE)) Index: /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp (revision 43656) +++ /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp (revision 43657) @@ -862,7 +862,14 @@ case MSR_IA32_APICBASE: - rc = PDMApicGetBase(pVCpu->CTX_SUFF(pVM), puValue); - if (RT_SUCCESS(rc)) - rc = VINF_SUCCESS; + { + PVM pVM = pVCpu->CTX_SUFF(pVM); + if ( ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 + && (pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_APIC)) + || ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001 + && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD + && (pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_APIC))) + { + *puValue = pVCpu->cpum.s.Guest.msrApicBase; + } else { @@ -871,4 +878,5 @@ } break; + } case MSR_IA32_CR_PAT: @@ -1122,5 +1130,5 @@ case MSR_IA32_APICBASE: - rc = PDMApicSetBase(pVCpu->CTX_SUFF(pVM), uValue); + rc = PDMApicSetBase(pVCpu, uValue); if (rc != VINF_SUCCESS) rc = VERR_CPUM_RAISE_GP_0; Index: /trunk/src/VBox/VMM/VMMAll/PDMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PDMAll.cpp (revision 43656) +++ /trunk/src/VBox/VMM/VMMAll/PDMAll.cpp (revision 43657) @@ -58,5 +58,5 @@ Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)); uint32_t uTagSrc; - int i = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), &uTagSrc); + int i = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu, &uTagSrc); AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i)); if (i >= 0) @@ -215,35 +215,46 @@ * * @returns VBox status code. - * @param pVM Pointer to the VM. + * @param pVM Pointer to the VMCPU. * @param u64Base The new base. */ -VMMDECL(int) PDMApicSetBase(PVM pVM, uint64_t u64Base) -{ +VMMDECL(int) PDMApicSetBase(PVMCPU pVCpu, uint64_t u64Base) +{ + PVM pVM = pVCpu->CTX_SUFF(pVM); if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns)) { Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetBase)); pdmLock(pVM); - pVM->pdm.s.Apic.CTX_SUFF(pfnSetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), u64Base); - pdmUnlock(pVM); - return VINF_SUCCESS; - } - return VERR_PDM_NO_APIC_INSTANCE; -} - - -/** - * Get the APIC base. - * - * @returns VBox status code. - * @param pVM Pointer to the VM. + pVM->pdm.s.Apic.CTX_SUFF(pfnSetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu, u64Base); + + /* Update CPUM's copy of the APIC base. */ + PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu); + Assert(pCtx); + pCtx->msrApicBase = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu); + + pdmUnlock(pVM); + return VINF_SUCCESS; + } + return VERR_PDM_NO_APIC_INSTANCE; +} + + +/** + * Get the APIC base from the APIC device. This is slow and involves + * taking the PDM lock, this is currently only used by CPUM to cache the APIC + * base once (during init./load state), all other callers should use + * PDMApicGetBase() and not this function. + * + * @returns VBox status code. + * @param pVM Pointer to the VMCPU. * @param pu64Base Where to store the APIC base. */ -VMMDECL(int) PDMApicGetBase(PVM pVM, uint64_t *pu64Base) -{ +VMMDECL(int) PDMApicGetBase(PVMCPU pVCpu, uint64_t *pu64Base) +{ + PVM pVM = pVCpu->CTX_SUFF(pVM); if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns)) { Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase)); pdmLock(pVM); - *pu64Base = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns)); + *pu64Base = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu); pdmUnlock(pVM); return VINF_SUCCESS; @@ -258,14 +269,15 @@ * * @returns VINF_SUCCESS or VERR_PDM_NO_APIC_INSTANCE. - * @param pDevIns Device instance of the APIC. + * @param pVCpu Pointer to the VMCPU. * @param pfPending Pending state (out). */ -VMMDECL(int) PDMApicHasPendingIrq(PVM pVM, bool *pfPending) -{ +VMMDECL(int) PDMApicHasPendingIrq(PVMCPU pVCpu, bool *pfPending) +{ + PVM pVM = pVCpu->CTX_SUFF(pVM); if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns)) { Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR)); pdmLock(pVM); - *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns)); + *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu); pdmUnlock(pVM); return VINF_SUCCESS; @@ -316,5 +328,5 @@ *pu8TPR = pVM->pdm.s.Apic.CTX_SUFF(pfnGetTPR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu); if (pfPending) - *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns)); + *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu); return VINF_SUCCESS; } Index: /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp (revision 43656) +++ /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp (revision 43657) @@ -1952,5 +1952,5 @@ { RTGCPHYS GCPhysApicBase, GCPhys; - PDMApicGetBase(pVM, &GCPhysApicBase); /** @todo cache this */ + GCPhysApicBase = pCtx->msrApicBase; GCPhysApicBase &= PAGE_BASE_GC_MASK; @@ -2117,6 +2117,5 @@ && pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches)) { - RTGCPHYS GCPhysApicBase; - PDMApicGetBase(pVM, &GCPhysApicBase); /** @todo cache this */ + RTGCPHYS GCPhysApicBase = pCtx->msrApicBase; GCPhysApicBase &= PAGE_BASE_GC_MASK; Index: /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (revision 43656) +++ /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (revision 43657) @@ -1166,5 +1166,5 @@ Assert((TRPMQueryTrap(pVCpu, NULL, NULL) == VERR_TRPM_NO_ACTIVE_TRAP)); - /* + /* * Clear the pending event and move it over to TRPM for the rest * of the world to see. @@ -3505,5 +3505,5 @@ { RTGCPHYS GCPhysApicBase, GCPhys; - PDMApicGetBase(pVM, &GCPhysApicBase); /** @todo cache this */ + GCPhysApicBase = pCtx->msrApicBase; GCPhysApicBase &= PAGE_BASE_GC_MASK; @@ -3536,5 +3536,5 @@ { RTGCPHYS GCPhysApicBase, GCPhys; - PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */ + GCPhysApicBase = pCtx->msrApicBase; GCPhysApicBase &= PAGE_BASE_GC_MASK; @@ -4048,5 +4048,5 @@ { RTGCPHYS GCPhysApicBase; - PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */ + GCPhysApicBase = pCtx->msrApicBase; GCPhysApicBase &= PAGE_BASE_GC_MASK; if (GCPhys == GCPhysApicBase + 0x80) @@ -4108,6 +4108,5 @@ && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)) { - RTGCPHYS GCPhysApicBase; - PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */ + RTGCPHYS GCPhysApicBase = pCtx->msrApicBase; GCPhysApicBase &= PAGE_BASE_GC_MASK; if (GCPhys == GCPhysApicBase + 0x80) @@ -4648,6 +4647,5 @@ case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE: { - RTGCPHYS GCPhys; - PDMApicGetBase(pVM, &GCPhys); + RTGCPHYS GCPhys = pCtx->msrApicBase; GCPhys &= PAGE_BASE_GC_MASK; GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(exitQualification); Index: /trunk/src/VBox/VMM/VMMR3/CPUM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/CPUM.cpp (revision 43656) +++ /trunk/src/VBox/VMM/VMMR3/CPUM.cpp (revision 43657) @@ -40,4 +40,5 @@ #include #include +#include #include #include @@ -1490,5 +1491,5 @@ { /** @todo anything different for VCPU > 0? */ - PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu); + PCPUMCTX pCtx = &pVCpu->cpum.s.Guest; /* @@ -1575,4 +1576,10 @@ */ pCtx->msrEFER = 0; + + /* + * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base + * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses. + */ + PDMApicGetBase(pVCpu, &pCtx->msrApicBase); } @@ -1591,5 +1598,5 @@ #ifdef VBOX_WITH_CRASHDUMP_MAGIC - PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]); + PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest; /* Magic marker for searching in crash dumps. */ @@ -2702,7 +2709,12 @@ } - /* Notify PGM of the NXE states in case they've changed. */ for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++) + { + /* Notify PGM of the NXE states in case they've changed. */ PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE)); + + /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */ + PDMApicGetBase(&pVM->aCpus[iCpu], &pVM->aCpus[iCpu].cpum.s.Guest.msrApicBase); + } return VINF_SUCCESS; } @@ -3064,5 +3076,5 @@ pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment); - PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu); + PCPUMCTX pCtx = &pVCpu->cpum.s.Guest; cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, ""); } Index: /trunk/src/VBox/VMM/VMMR3/VM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/VM.cpp (revision 43656) +++ /trunk/src/VBox/VMM/VMMR3/VM.cpp (revision 43657) @@ -2858,5 +2858,4 @@ CPUMR3Reset(pVM); } - CPUMR3ResetCpu(pVCpu); if (pVCpu->idCpu == 0) { Index: /trunk/src/VBox/VMM/include/CPUMInternal.mac =================================================================== --- /trunk/src/VBox/VMM/include/CPUMInternal.mac (revision 43656) +++ /trunk/src/VBox/VMM/include/CPUMInternal.mac (revision 43657) @@ -196,4 +196,5 @@ .Hyper.msrSFMASK resb 8 .Hyper.msrKERNELGSBASE resb 8 + .Hyper.msrApicBase resb 8 ; @@ -416,4 +417,5 @@ .Guest.msrSFMASK resb 8 .Guest.msrKERNELGSBASE resb 8 + .Guest.msrApicBase resb 8 Index: /trunk/src/VBox/VMM/include/PDMInternal.h =================================================================== --- /trunk/src/VBox/VMM/include/PDMInternal.h (revision 43656) +++ /trunk/src/VBox/VMM/include/PDMInternal.h (revision 43657) @@ -488,11 +488,11 @@ PPDMDEVINSR3 pDevInsR3; /** @copydoc PDMAPICREG::pfnGetInterruptR3 */ - DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc)); + DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t *puTagSrc)); /** @copydoc PDMAPICREG::pfnHasPendingIrqR3 */ - DECLR3CALLBACKMEMBER(bool, pfnHasPendingIrqR3,(PPDMDEVINS pDevIns)); + DECLR3CALLBACKMEMBER(bool, pfnHasPendingIrqR3,(PPDMDEVINS pDevIns, VMCPUID idCpu)); /** @copydoc PDMAPICREG::pfnSetBaseR3 */ - DECLR3CALLBACKMEMBER(void, pfnSetBaseR3,(PPDMDEVINS pDevIns, uint64_t u64Base)); + DECLR3CALLBACKMEMBER(void, pfnSetBaseR3,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint64_t u64Base)); /** @copydoc PDMAPICREG::pfnGetBaseR3 */ - DECLR3CALLBACKMEMBER(uint64_t, pfnGetBaseR3,(PPDMDEVINS pDevIns)); + DECLR3CALLBACKMEMBER(uint64_t, pfnGetBaseR3,(PPDMDEVINS pDevIns, VMCPUID idCpu)); /** @copydoc PDMAPICREG::pfnSetTPRR3 */ DECLR3CALLBACKMEMBER(void, pfnSetTPRR3,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t u8TPR)); @@ -512,11 +512,11 @@ PPDMDEVINSR0 pDevInsR0; /** @copydoc PDMAPICREG::pfnGetInterruptR3 */ - DECLR0CALLBACKMEMBER(int, pfnGetInterruptR0,(PPDMDEVINS pDevIns, uint32_t *puTagSrc)); + DECLR0CALLBACKMEMBER(int, pfnGetInterruptR0,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t *puTagSrc)); /** @copydoc PDMAPICREG::pfnHasPendingIrqR3 */ - DECLR0CALLBACKMEMBER(bool, pfnHasPendingIrqR0,(PPDMDEVINS pDevIns)); + DECLR0CALLBACKMEMBER(bool, pfnHasPendingIrqR0,(PPDMDEVINS pDevIns, VMCPUID idCpu)); /** @copydoc PDMAPICREG::pfnSetBaseR3 */ - DECLR0CALLBACKMEMBER(void, pfnSetBaseR0,(PPDMDEVINS pDevIns, uint64_t u64Base)); + DECLR0CALLBACKMEMBER(void, pfnSetBaseR0,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint64_t u64Base)); /** @copydoc PDMAPICREG::pfnGetBaseR3 */ - DECLR0CALLBACKMEMBER(uint64_t, pfnGetBaseR0,(PPDMDEVINS pDevIns)); + DECLR0CALLBACKMEMBER(uint64_t, pfnGetBaseR0,(PPDMDEVINS pDevIns, VMCPUID idCpu)); /** @copydoc PDMAPICREG::pfnSetTPRR3 */ DECLR0CALLBACKMEMBER(void, pfnSetTPRR0,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t u8TPR)); @@ -536,11 +536,11 @@ PPDMDEVINSRC pDevInsRC; /** @copydoc PDMAPICREG::pfnGetInterruptR3 */ - DECLRCCALLBACKMEMBER(int, pfnGetInterruptRC,(PPDMDEVINS pDevIns, uint32_t *puTagSrc)); + DECLRCCALLBACKMEMBER(int, pfnGetInterruptRC,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t *puTagSrc)); /** @copydoc PDMAPICREG::pfnHasPendingIrqR3 */ - DECLRCCALLBACKMEMBER(bool, pfnHasPendingIrqRC,(PPDMDEVINS pDevIns)); + DECLRCCALLBACKMEMBER(bool, pfnHasPendingIrqRC,(PPDMDEVINS pDevIns, VMCPUID idCpu)); /** @copydoc PDMAPICREG::pfnSetBaseR3 */ - DECLRCCALLBACKMEMBER(void, pfnSetBaseRC,(PPDMDEVINS pDevIns, uint64_t u64Base)); + DECLRCCALLBACKMEMBER(void, pfnSetBaseRC,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint64_t u64Base)); /** @copydoc PDMAPICREG::pfnGetBaseR3 */ - DECLRCCALLBACKMEMBER(uint64_t, pfnGetBaseRC,(PPDMDEVINS pDevIns)); + DECLRCCALLBACKMEMBER(uint64_t, pfnGetBaseRC,(PPDMDEVINS pDevIns, VMCPUID idCpu)); /** @copydoc PDMAPICREG::pfnSetTPRR3 */ DECLRCCALLBACKMEMBER(void, pfnSetTPRRC,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t u8TPR)); Index: /trunk/src/recompiler/VBoxRecompiler.c =================================================================== --- /trunk/src/recompiler/VBoxRecompiler.c (revision 43656) +++ /trunk/src/recompiler/VBoxRecompiler.c (revision 43657) @@ -4464,5 +4464,5 @@ { uint64_t u64; - int rc = PDMApicGetBase(env->pVM, &u64); + int rc = CPUMQueryGuestMsr(env->pVCpu, MSR_IA32_APICBASE, &u64); if (RT_SUCCESS(rc)) {