Index: /trunk/src/VBox/Devices/Storage/DevBusLogic.cpp =================================================================== --- /trunk/src/VBox/Devices/Storage/DevBusLogic.cpp (revision 43328) +++ /trunk/src/VBox/Devices/Storage/DevBusLogic.cpp (revision 43329) @@ -69,4 +69,7 @@ #define BUSLOGIC_SAVED_STATE_MINOR_PRE_ERROR_HANDLING 1 +/** The duration of software-initiated reset. Not documented, set to 500 us. */ +#define BUSLOGIC_RESET_DURATION_NS (500*1000) + /** * State of a device attached to the buslogic host adapter. @@ -121,5 +124,5 @@ enum BUSLOGICCOMMAND { - BUSLOGICCOMMAND_TEST_COMMAND_COMPLETE_INTERRUPT = 0x00, + BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT = 0x00, BUSLOGICCOMMAND_INITIALIZE_MAILBOX = 0x01, BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND = 0x02, @@ -249,5 +252,4 @@ #pragma pack() -#pragma pack(1) /** * The local Ram. @@ -267,5 +269,4 @@ } HostAdapterLocalRam, *PHostAdapterLocalRam; AssertCompileSize(HostAdapterLocalRam, 256); -#pragma pack() /** Pointer to a task state structure. */ @@ -304,4 +305,6 @@ /** Geometry register - Readonly. */ volatile uint8_t regGeometry; + /** Pending (delayed) interrupt. */ + uint8_t uPendingIntr; /** Local RAM for the fetch hostadapter local RAM request. @@ -345,4 +348,6 @@ #endif + /** Time when HBA reset was last initiated. */ //@todo: does this need to be saved? + uint64_t u64ResetTime; /** Physical base address of the outgoing mailboxes. */ RTGCPHYS GCPhysAddrMailboxOutgoingBase; @@ -442,5 +447,5 @@ /** Fields for the interrupt register. */ # define BUSLOGIC_REGISTER_INTERRUPT_INCOMING_MAILBOX_LOADED RT_BIT(0) -# define BUSLOGIC_REGISTER_INTERRUPT_OUTCOMING_MAILBOX_AVAILABLE RT_BIT(1) +# define BUSLOGIC_REGISTER_INTERRUPT_OUTGOING_MAILBOX_AVAILABLE RT_BIT(1) # define BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE RT_BIT(2) # define BUSLOGIC_REGISTER_INTERRUPT_EXTERNAL_BUS_RESET RT_BIT(3) @@ -451,5 +456,4 @@ /* Structure for the INQUIRE_PCI_HOST_ADAPTER_INFORMATION reply. */ -#pragma pack(1) typedef struct ReplyInquirePCIHostAdapterInformation { @@ -467,8 +471,6 @@ } ReplyInquirePCIHostAdapterInformation, *PReplyInquirePCIHostAdapterInformation; AssertCompileSize(ReplyInquirePCIHostAdapterInformation, 4); -#pragma pack() /* Structure for the INQUIRE_CONFIGURATION reply. */ -#pragma pack(1) typedef struct ReplyInquireConfiguration { @@ -489,8 +491,6 @@ } ReplyInquireConfiguration, *PReplyInquireConfiguration; AssertCompileSize(ReplyInquireConfiguration, 3); -#pragma pack() /* Structure for the INQUIRE_SETUP_INFORMATION reply. */ -#pragma pack(1) typedef struct ReplyInquireSetupInformationSynchronousValue { @@ -500,7 +500,5 @@ }ReplyInquireSetupInformationSynchronousValue, *PReplyInquireSetupInformationSynchronousValue; AssertCompileSize(ReplyInquireSetupInformationSynchronousValue, 1); -#pragma pack() - -#pragma pack(1) + typedef struct ReplyInquireSetupInformation { @@ -527,5 +525,4 @@ } ReplyInquireSetupInformation, *PReplyInquireSetupInformation; AssertCompileSize(ReplyInquireSetupInformation, 34); -#pragma pack() /* Structure for the INQUIRE_EXTENDED_SETUP_INFORMATION. */ @@ -789,4 +786,37 @@ /** + * Assert IRQ line of the BusLogic adapter. + * + * @returns nothing. + * @param pBusLogic Pointer to the BusLogic device instance. + * @param fSuppressIrq Flag to suppress IRQ generation regardless of fIRQEnabled + * @param uFlag Type of interrupt being generated. + */ +static void buslogicSetInterrupt(PBUSLOGIC pBusLogic, bool fSuppressIrq, uint8_t uIrqType) +{ + LogFlowFunc(("pBusLogic=%#p\n", pBusLogic)); + + /* The CMDC interrupt has priority over IMBL and MBOR. */ + if (uIrqType & (BUSLOGIC_REGISTER_INTERRUPT_INCOMING_MAILBOX_LOADED | BUSLOGIC_REGISTER_INTERRUPT_OUTGOING_MAILBOX_AVAILABLE)) + { + if (!(pBusLogic->regInterrupt & BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE)) + pBusLogic->regInterrupt |= uIrqType; /* Report now. */ + else + pBusLogic->uPendingIntr |= uIrqType; /* Report later. */ + } + else if (uIrqType & BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE) + { + Assert(!pBusLogic->regInterrupt); + pBusLogic->regInterrupt |= uIrqType; + } + else + AssertMsgFailed(("Invalid interrupt state!\n")); + + pBusLogic->regInterrupt |= BUSLOGIC_REGISTER_INTERRUPT_INTERRUPT_VALID; + if (pBusLogic->fIRQEnabled && !fSuppressIrq) + PDMDevHlpPCISetIrq(pBusLogic->CTX_SUFF(pDevIns), 0, 1); +} + +/** * Deasserts the interrupt line of the BusLogic adapter. * @@ -799,19 +829,10 @@ pBusLogic->regInterrupt = 0; PDMDevHlpPCISetIrq(pBusLogic->CTX_SUFF(pDevIns), 0, 0); -} - -/** - * Assert IRQ line of the BusLogic adapter. - * - * @returns nothing. - * @param pBusLogic Pointer to the BusLogic device instance. - * @param fSuppressIrq Flag to suppress IRQ generation regardless of fIRQEnabled - */ -static void buslogicSetInterrupt(PBUSLOGIC pBusLogic, bool fSuppressIrq) -{ - LogFlowFunc(("pBusLogic=%#p\n", pBusLogic)); - pBusLogic->regInterrupt |= BUSLOGIC_REGISTER_INTERRUPT_INTERRUPT_VALID; - if (pBusLogic->fIRQEnabled && !fSuppressIrq) - PDMDevHlpPCISetIrq(pBusLogic->CTX_SUFF(pDevIns), 0, 1); + /* If there's another pending interrupt, report it now. */ + if (pBusLogic->uPendingIntr) + { + buslogicSetInterrupt(pBusLogic, false, pBusLogic->uPendingIntr); + pBusLogic->uPendingIntr = 0; + } } @@ -876,4 +897,5 @@ pBusLogic->regStatus = BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY | BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED; pBusLogic->regInterrupt = 0; + pBusLogic->uPendingIntr = 0; pBusLogic->regGeometry = BUSLOGIC_REGISTER_GEOMETRY_EXTENTED_TRANSLATION_ENABLED; pBusLogic->uOperationCode = 0xff; /* No command executing. */ @@ -912,7 +934,5 @@ /* Notify that the command is complete. */ pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_DATA_IN_REGISTER_READY; - pBusLogic->regInterrupt |= BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE; - - buslogicSetInterrupt(pBusLogic, fSuppressIrq); + buslogicSetInterrupt(pBusLogic, fSuppressIrq, BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE); } @@ -931,4 +951,7 @@ { LogFlowFunc(("pBusLogic=%#p\n", pBusLogic)); + + /* Remember when the guest initiated a reset. */ + pBusLogic->u64ResetTime = PDMDevHlpTMTimeVirtGetNano(pBusLogic->CTX_SUFF(pDevIns)); buslogicHwReset(pBusLogic); @@ -987,6 +1010,5 @@ #endif - pBusLogic->regInterrupt |= BUSLOGIC_REGISTER_INTERRUPT_INCOMING_MAILBOX_LOADED; - buslogicSetInterrupt(pBusLogic, false); + buslogicSetInterrupt(pBusLogic, false, BUSLOGIC_REGISTER_INTERRUPT_INCOMING_MAILBOX_LOADED); PDMCritSectLeave(&pBusLogic->CritSectIntr); @@ -1318,4 +1340,8 @@ switch (pBusLogic->uOperationCode) { + case BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT: + /* Valid command, no reply. */ + pBusLogic->cbReplyParametersLeft = 0; + break; case BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION: { @@ -1326,4 +1352,5 @@ pReply->InformationIsValid = 0; pReply->IsaIOPort = 0xff; /* Make it invalid. */ + pReply->IRQ = PCIDevGetInterruptLine(&pBusLogic->dev); pBusLogic->cbReplyParametersLeft = sizeof(ReplyInquirePCIHostAdapterInformation); break; @@ -1367,4 +1394,21 @@ break; } + case BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS: + /* The parameter list length is determined by the first byte of the command buffer. */ + if (pBusLogic->iParameter == 1) + { + /* First pass - set the number of following parameter bytes. */ + pBusLogic->cbCommandParametersLeft = pBusLogic->aCommandBuffer[0]; + Log(("Set HA options: %u bytes follow\n", pBusLogic->aCommandBuffer[0])); + } + else + { + /* Second pass - process received data. */ + Log(("Set HA options: received %u bytes\n", pBusLogic->aCommandBuffer[0])); + /* We ignore the data - it only concerns the SCSI hardware protocol. */ + } + pBusLogic->cbReplyParametersLeft = 0; + break; + case BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER: { @@ -1384,4 +1428,6 @@ case BUSLOGICCOMMAND_INQUIRE_CONFIGURATION: { + uint8_t uPciIrq = PCIDevGetInterruptLine(&pBusLogic->dev); + pBusLogic->cbReplyParametersLeft = sizeof(ReplyInquireConfiguration); PReplyInquireConfiguration pReply = (PReplyInquireConfiguration)pBusLogic->aReplyBuffer; @@ -1389,8 +1435,18 @@ pReply->uHostAdapterId = 7; /* The controller has always 7 as ID. */ - /* - * The rest of this reply only applies for ISA adapters. - * This is a PCI adapter so they are not important and are skipped. - */ + //@todo: What should the DMA channel be? + pReply->fDmaChannel6 = 1; + /* The IRQ is not necessarily representable in this structure. */ + switch (uPciIrq) { + case 9: pReply->fIrqChannel9 = 1; break; + case 10: pReply->fIrqChannel10 = 1; break; + case 11: pReply->fIrqChannel11 = 1; break; + case 12: pReply->fIrqChannel12 = 1; break; + case 14: pReply->fIrqChannel14 = 1; break; + case 15: pReply->fIrqChannel15 = 1; break; + default: + Log(("Inquire configuration: PCI IRQ %d cannot be represented\n", uPciIrq)); + break; + } break; } @@ -1405,4 +1461,6 @@ pReply->uBusType = 'E'; /* EISA style */ pReply->u16ScatterGatherLimit = 8192; + pReply->cMailbox = pBusLogic->cMailbox; + pReply->uMailboxAddressBase = (uint32_t)pBusLogic->GCPhysAddrMailboxOutgoingBase; pReply->fLevelSensitiveInterrupt = true; pReply->fHostWideSCSI = true; @@ -1444,5 +1502,6 @@ Log(("GCPhysAddrMailboxOutgoingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxOutgoingBase)); Log(("GCPhysAddrMailboxIncomingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxIncomingBase)); - Log(("cMailboxes=%u\n", pBusLogic->cMailbox)); + Log(("cMailboxes=%u (32-bit mode)\n", pBusLogic->cMailbox)); + LogRel(("Initialized 32-bit mailbox, %d entries at %08x\n", pRequest->cMailbox, pRequest->uMailboxBaseAddress)); pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED; @@ -1474,4 +1533,17 @@ break; } + case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7: + /* This is supposed to send TEST UNIT READY to each target/LUN. + * We cheat and skip that, since we already know what's attached + */ + memset(pBusLogic->aReplyBuffer, 0, 8); + for (int i = 0; i < 8; ++i) + { + if (pBusLogic->aDeviceStates[i].fPresent) + pBusLogic->aReplyBuffer[i] = 1; + } + pBusLogic->aReplyBuffer[7] = 0; /* HA hardcoded at ID 7. */ + pBusLogic->cbReplyParametersLeft = 8; + break; case BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES: { @@ -1528,4 +1600,6 @@ break; } + default: + AssertMsgFailed(("Invalid command %#x\n", pBusLogic->uOperationCode)); case BUSLOGICCOMMAND_EXT_BIOS_INFO: case BUSLOGICCOMMAND_UNLOCK_MAILBOX: @@ -1538,6 +1612,5 @@ break; case BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND: /* Should be handled already. */ - default: - AssertMsgFailed(("Invalid command %#x\n", pBusLogic->uOperationCode)); + AssertMsgFailed(("Invalid mailbox execute state!\n")); } @@ -1547,5 +1620,5 @@ if (pBusLogic->cbReplyParametersLeft) pBusLogic->regStatus |= BUSLOGIC_REGISTER_STATUS_DATA_IN_REGISTER_READY; - else + else if (!pBusLogic->cbCommandParametersLeft) buslogicCommandComplete(pBusLogic, fSuppressIrq); @@ -1570,12 +1643,24 @@ { *pu32 = pBusLogic->regStatus; - /* - * If the diagnostic active bit is set we are in a hard reset initiated from the guest. - * The guest reads the status register and waits that the host adapter ready bit is set. + + /* If the diagnostic active bit is set, we are in a guest-initiated + * hard or soft reset. If the guest reads the status register and + * waits for the host adapter ready bit to be set, we terminate the + * reset right away. However, guests may also expect the reset + * condition to clear automatically after a period of time. */ if (pBusLogic->regStatus & BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_ACTIVE) { + uint64_t u64AccessTime = PDMDevHlpTMTimeVirtGetNano(pBusLogic->CTX_SUFF(pDevIns)); + pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_ACTIVE; pBusLogic->regStatus |= BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY; + if (u64AccessTime - pBusLogic->u64ResetTime > BUSLOGIC_RESET_DURATION_NS) + { + /* Let the guest see the ready condition right away. */ + *pu32 &= ~BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_ACTIVE; + *pu32 |= BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY; + pBusLogic->u64ResetTime = 0; + } } break; @@ -1588,16 +1673,22 @@ *pu32 = pBusLogic->aReplyBuffer[pBusLogic->iReply]; - pBusLogic->iReply++; - pBusLogic->cbReplyParametersLeft--; - - LogFlowFunc(("cbReplyParametersLeft=%u\n", pBusLogic->cbReplyParametersLeft)); - if (!pBusLogic->cbReplyParametersLeft) + /* Careful about underflow - guest can read data register even if + * no data is available. + */ + if (pBusLogic->cbReplyParametersLeft) { - /* - * Reply finished, set command complete bit, unset data in ready bit and - * interrupt the guest if enabled. - */ - buslogicCommandComplete(pBusLogic, false); + pBusLogic->iReply++; + pBusLogic->cbReplyParametersLeft--; + if (!pBusLogic->cbReplyParametersLeft) + { + /* + * Reply finished, set command complete bit, unset data-in ready bit and + * interrupt the guest if enabled. + */ + buslogicCommandComplete(pBusLogic, false); + } } + LogFlowFunc(("data=%02x, iReply=%d, cbReplyParametersLeft=%u\n", *pu32, + pBusLogic->iReply, pBusLogic->cbReplyParametersLeft)); break; } @@ -1644,5 +1735,5 @@ #ifdef LOG_ENABLED uint32_t cMailboxesReady = ASMAtomicXchgU32(&pBusLogic->cInMailboxesReady, 0); - Log(("%u incoming mailboxes are ready when this interrupt was cleared\n", cMailboxesReady)); + Log(("%u incoming mailboxes were ready when this interrupt was cleared\n", cMailboxesReady)); #endif @@ -1695,4 +1786,5 @@ switch (pBusLogic->uOperationCode) { + case BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT: case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER: case BUSLOGICCOMMAND_INQUIRE_BOARD_ID: @@ -1700,4 +1792,5 @@ case BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION: case BUSLOGICCOMMAND_INQUIRE_CONFIGURATION: + case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7: case BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES: pBusLogic->cbCommandParametersLeft = 0; @@ -1721,4 +1814,8 @@ case BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX: pBusLogic->cbCommandParametersLeft = sizeof(RequestInitializeExtendedMailbox); + break; + case BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS: + /* There must be at least one byte following this command. */ + pBusLogic->cbCommandParametersLeft = 1; break; case BUSLOGICCOMMAND_EXT_BIOS_INFO: @@ -1826,5 +1923,5 @@ { PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);; - unsigned iRegister = Port - pBusLogic->IOPortBase; + unsigned iRegister = Port % 4; Assert(cb == 1); @@ -1849,5 +1946,5 @@ PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC); int rc = VINF_SUCCESS; - unsigned iRegister = Port - pBusLogic->IOPortBase; + unsigned iRegister = Port % 4; uint8_t uVal = (uint8_t)u32; @@ -1874,5 +1971,5 @@ * @param cb Number of bytes read. */ -static int buslogicIsaIOPortRead (PPDMDEVINS pDevIns, void *pvUser, +static int buslogicBIOSIOPortRead (PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb) { @@ -2008,5 +2105,5 @@ * @param cb The value size in bytes. */ -static int buslogicIsaIOPortWrite (PPDMDEVINS pDevIns, void *pvUser, +static int buslogicBIOSIOPortWrite (PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb) { @@ -2038,5 +2135,5 @@ * @see FNIOMIOPORTOUTSTRING for details. */ -static DECLCALLBACK(int) buslogicIsaIOPortWriteStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb) +static DECLCALLBACK(int) buslogicBIOSIOPortWriteStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb) { PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC); @@ -2063,5 +2160,5 @@ * @see FNIOMIOPORTINSTRING for details. */ -static DECLCALLBACK(int) buslogicIsaIOPortReadStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrDst, PRTGCUINTREG pcTransfer, unsigned cb) +static DECLCALLBACK(int) buslogicBIOSIOPortReadStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrDst, PRTGCUINTREG pcTransfer, unsigned cb) { PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC); @@ -2091,5 +2188,5 @@ rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/, IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU, - buslogicMMIOWrite, buslogicMMIORead, "BusLogic"); + buslogicMMIOWrite, buslogicMMIORead, "BusLogic MMIO"); if (RT_FAILURE(rc)) return rc; @@ -2116,5 +2213,5 @@ { rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, 32, - NULL, buslogicIOPortWrite, buslogicIOPortRead, NULL, NULL, "BusLogic"); + NULL, buslogicIOPortWrite, buslogicIOPortRead, NULL, NULL, "BusLogic PCI"); if (RT_FAILURE(rc)) return rc; @@ -2123,5 +2220,5 @@ { rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, 32, - 0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic"); + 0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic PCI"); if (RT_FAILURE(rc)) return rc; @@ -2131,5 +2228,5 @@ { rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, 32, - 0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic"); + 0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic PCI"); if (RT_FAILURE(rc)) return rc; @@ -2203,6 +2300,5 @@ AssertMsgFailed(("invalid completion status %d\n", rcCompletion)); } - - /* Add task to the cache. */ + /* Remove task from the cache. */ RTMemCacheFree(pBusLogic->hTaskCache, pTaskState); } @@ -2235,5 +2331,5 @@ int rc = VINF_SUCCESS; - /* Fetch CCB. */ + /* Fetch the CCB from guest memory. */ RTGCPHYS GCPhysAddrCCB = (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB; PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrCCB, @@ -2371,5 +2467,5 @@ } - LogFlow(("Got loaded mailbox at slot %u, CCB phys %RGp\n", pBusLogic->uMailboxOutgoingPositionCurrent, pTaskState->MailboxGuest.u32PhysAddrCCB)); + LogFlow(("Got loaded mailbox at slot %u, CCB phys %RGp\n", pBusLogic->uMailboxOutgoingPositionCurrent, (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB)); #ifdef DEBUG buslogicDumpMailboxInfo(&pTaskState->MailboxGuest, true); @@ -3128,6 +3224,6 @@ /* Register I/O port space in ISA region for BIOS access. */ rc = PDMDevHlpIOPortRegister(pDevIns, BUSLOGIC_BIOS_IO_PORT, 3, NULL, - buslogicIsaIOPortWrite, buslogicIsaIOPortRead, - buslogicIsaIOPortWriteStr, buslogicIsaIOPortReadStr, + buslogicBIOSIOPortWrite, buslogicBIOSIOPortRead, + buslogicBIOSIOPortWriteStr, buslogicBIOSIOPortReadStr, "BusLogic BIOS"); if (RT_FAILURE(rc))