Index: /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp (revision 42486) +++ /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp (revision 42487) @@ -1078,4 +1078,110 @@ { \ VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8SxU16(pIemCpu, (a_pu16)); \ + if (rcStrict2 != VINF_SUCCESS) \ + return rcStrict2; \ + } while (0) + + +/** + * Deals with the problematic cases that iemOpcodeGetNextS8SxU32 doesn't like. + * + * @returns Strict VBox status code. + * @param pIemCpu The IEM state. + * @param pu32 Where to return the opcode dword. + */ +DECL_NO_INLINE(static, VBOXSTRICTRC) iemOpcodeGetNextS8SxU32Slow(PIEMCPU pIemCpu, uint32_t *pu32) +{ + uint8_t u8; + VBOXSTRICTRC rcStrict = iemOpcodeGetNextU8Slow(pIemCpu, &u8); + if (rcStrict == VINF_SUCCESS) + *pu32 = (int8_t)u8; + return rcStrict; +} + + +/** + * Fetches the next signed byte from the opcode stream, extending it to + * unsigned 32-bit. + * + * @returns Strict VBox status code. + * @param pIemCpu The IEM state. + * @param pu32 Where to return the unsigned dword. + */ +DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS8SxU32(PIEMCPU pIemCpu, uint32_t *pu32) +{ + uint8_t const offOpcode = pIemCpu->offOpcode; + if (RT_UNLIKELY(offOpcode >= pIemCpu->cbOpcode)) + return iemOpcodeGetNextS8SxU32Slow(pIemCpu, pu32); + + *pu32 = (int8_t)pIemCpu->abOpcode[offOpcode]; + pIemCpu->offOpcode = offOpcode + 1; + return VINF_SUCCESS; +} + + +/** + * Fetches the next signed byte from the opcode stream and sign-extending it to + * a word, returning automatically on failure. + * + * @param pu32 Where to return the word. + * @remark Implicitly references pIemCpu. + */ +#define IEM_OPCODE_GET_NEXT_S8_SX_U32(a_pu32) \ + do \ + { \ + VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8SxU32(pIemCpu, (a_pu32)); \ + if (rcStrict2 != VINF_SUCCESS) \ + return rcStrict2; \ + } while (0) + + +/** + * Deals with the problematic cases that iemOpcodeGetNextS8SxU64 doesn't like. + * + * @returns Strict VBox status code. + * @param pIemCpu The IEM state. + * @param pu64 Where to return the opcode qword. + */ +DECL_NO_INLINE(static, VBOXSTRICTRC) iemOpcodeGetNextS8SxU64Slow(PIEMCPU pIemCpu, uint64_t *pu64) +{ + uint8_t u8; + VBOXSTRICTRC rcStrict = iemOpcodeGetNextU8Slow(pIemCpu, &u8); + if (rcStrict == VINF_SUCCESS) + *pu64 = (int8_t)u8; + return rcStrict; +} + + +/** + * Fetches the next signed byte from the opcode stream, extending it to + * unsigned 64-bit. + * + * @returns Strict VBox status code. + * @param pIemCpu The IEM state. + * @param pu64 Where to return the unsigned qword. + */ +DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS8SxU64(PIEMCPU pIemCpu, uint64_t *pu64) +{ + uint8_t const offOpcode = pIemCpu->offOpcode; + if (RT_UNLIKELY(offOpcode >= pIemCpu->cbOpcode)) + return iemOpcodeGetNextS8SxU64Slow(pIemCpu, pu64); + + *pu64 = (int8_t)pIemCpu->abOpcode[offOpcode]; + pIemCpu->offOpcode = offOpcode + 1; + return VINF_SUCCESS; +} + + +/** + * Fetches the next signed byte from the opcode stream and sign-extending it to + * a word, returning automatically on failure. + * + * @param pu64 Where to return the word. + * @remark Implicitly references pIemCpu. + */ +#define IEM_OPCODE_GET_NEXT_S8_SX_U64(a_pu64) \ + do \ + { \ + VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8SxU64(pIemCpu, (a_pu64)); \ if (rcStrict2 != VINF_SUCCESS) \ return rcStrict2; \ Index: /trunk/src/VBox/VMM/VMMAll/IEMAllInstructions.cpp.h =================================================================== --- /trunk/src/VBox/VMM/VMMAll/IEMAllInstructions.cpp.h (revision 42486) +++ /trunk/src/VBox/VMM/VMMAll/IEMAllInstructions.cpp.h (revision 42487) @@ -6494,9 +6494,10 @@ case IEMMODE_16BIT: { - uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm); - IEMOP_HLP_NO_LOCK_PREFIX(); if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) { /* register operand */ + uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEM_MC_BEGIN(3, 1); IEM_MC_ARG(uint16_t *, pu16Dst, 0); @@ -6519,5 +6520,5 @@ IEM_MC_BEGIN(3, 2); IEM_MC_ARG(uint16_t *, pu16Dst, 0); - IEM_MC_ARG_CONST(uint16_t, u16Src,/*=*/ u16Imm,1); + IEM_MC_ARG(uint16_t, u16Src, 1); IEM_MC_ARG(uint32_t *, pEFlags, 2); IEM_MC_LOCAL(uint16_t, u16Tmp); @@ -6525,4 +6526,7 @@ IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm); + uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm); + IEM_MC_ASSIGN(u16Src, u16Imm); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); IEM_MC_FETCH_MEM_U16(u16Tmp, pIemCpu->iEffSeg, GCPtrEffDst); IEM_MC_REF_LOCAL(pu16Dst, u16Tmp); @@ -6539,9 +6543,10 @@ case IEMMODE_32BIT: { - uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm); - IEMOP_HLP_NO_LOCK_PREFIX(); if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) { /* register operand */ + uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEM_MC_BEGIN(3, 1); IEM_MC_ARG(uint32_t *, pu32Dst, 0); @@ -6564,5 +6569,5 @@ IEM_MC_BEGIN(3, 2); IEM_MC_ARG(uint32_t *, pu32Dst, 0); - IEM_MC_ARG_CONST(uint32_t, u32Src,/*=*/ u32Imm,1); + IEM_MC_ARG(uint32_t, u32Src, 1); IEM_MC_ARG(uint32_t *, pEFlags, 2); IEM_MC_LOCAL(uint32_t, u32Tmp); @@ -6570,4 +6575,7 @@ IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm); + uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm); + IEM_MC_ASSIGN(u32Src, u32Imm); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); IEM_MC_FETCH_MEM_U32(u32Tmp, pIemCpu->iEffSeg, GCPtrEffDst); IEM_MC_REF_LOCAL(pu32Dst, u32Tmp); @@ -6584,9 +6592,10 @@ case IEMMODE_64BIT: { - uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm); - IEMOP_HLP_NO_LOCK_PREFIX(); if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) { /* register operand */ + uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEM_MC_BEGIN(3, 1); IEM_MC_ARG(uint64_t *, pu64Dst, 0); @@ -6609,5 +6618,5 @@ IEM_MC_BEGIN(3, 2); IEM_MC_ARG(uint64_t *, pu64Dst, 0); - IEM_MC_ARG_CONST(uint64_t, u64Src,/*=*/ u64Imm,1); + IEM_MC_ARG(uint64_t, u64Src, 1); IEM_MC_ARG(uint32_t *, pEFlags, 2); IEM_MC_LOCAL(uint64_t, u64Tmp); @@ -6615,4 +6624,7 @@ IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm); + uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm); + IEM_MC_ASSIGN(u64Src, u64Imm); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); IEM_MC_FETCH_MEM_U64(u64Tmp, pIemCpu->iEffSeg, GCPtrEffDst); IEM_MC_REF_LOCAL(pu64Dst, u64Tmp); @@ -6662,7 +6674,5 @@ { IEMOP_MNEMONIC("imul Gv,Ev,Ib"); /* Gv = Ev * Iz; */ - uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); - uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); - IEMOP_HLP_NO_LOCK_PREFIX(); + uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF); @@ -6673,4 +6683,7 @@ { /* register operand */ + uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEM_MC_BEGIN(3, 1); IEM_MC_ARG(uint16_t *, pu16Dst, 0); @@ -6693,5 +6706,5 @@ IEM_MC_BEGIN(3, 2); IEM_MC_ARG(uint16_t *, pu16Dst, 0); - IEM_MC_ARG_CONST(uint16_t, u16Src,/*=*/ (int8_t)u8Imm, 1); + IEM_MC_ARG(uint16_t, u16Src, 1); IEM_MC_ARG(uint32_t *, pEFlags, 2); IEM_MC_LOCAL(uint16_t, u16Tmp); @@ -6699,4 +6712,7 @@ IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm); + uint16_t u16Imm; IEM_OPCODE_GET_NEXT_S8_SX_U16(&u16Imm); + IEM_MC_ASSIGN(u16Src, u16Imm); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); IEM_MC_FETCH_MEM_U16(u16Tmp, pIemCpu->iEffSeg, GCPtrEffDst); IEM_MC_REF_LOCAL(pu16Dst, u16Tmp); @@ -6714,4 +6730,7 @@ { /* register operand */ + uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEM_MC_BEGIN(3, 1); IEM_MC_ARG(uint32_t *, pu32Dst, 0); @@ -6734,5 +6753,5 @@ IEM_MC_BEGIN(3, 2); IEM_MC_ARG(uint32_t *, pu32Dst, 0); - IEM_MC_ARG_CONST(uint32_t, u32Src,/*=*/ (int8_t)u8Imm, 1); + IEM_MC_ARG(uint32_t, u32Src, 1); IEM_MC_ARG(uint32_t *, pEFlags, 2); IEM_MC_LOCAL(uint32_t, u32Tmp); @@ -6740,4 +6759,7 @@ IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm); + uint32_t u32Imm; IEM_OPCODE_GET_NEXT_S8_SX_U32(&u32Imm); + IEM_MC_ASSIGN(u32Src, u32Imm); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); IEM_MC_FETCH_MEM_U32(u32Tmp, pIemCpu->iEffSeg, GCPtrEffDst); IEM_MC_REF_LOCAL(pu32Dst, u32Tmp); @@ -6755,4 +6777,7 @@ { /* register operand */ + uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); + IEM_MC_BEGIN(3, 1); IEM_MC_ARG(uint64_t *, pu64Dst, 0); @@ -6775,5 +6800,5 @@ IEM_MC_BEGIN(3, 2); IEM_MC_ARG(uint64_t *, pu64Dst, 0); - IEM_MC_ARG_CONST(uint64_t, u64Src,/*=*/ (int8_t)u8Imm, 1); + IEM_MC_ARG(uint64_t, u64Src, 1); IEM_MC_ARG(uint32_t *, pEFlags, 2); IEM_MC_LOCAL(uint64_t, u64Tmp); @@ -6781,4 +6806,7 @@ IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm); + uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S8_SX_U64(&u64Imm); + IEM_MC_ASSIGN(u64Src, u64Imm); + IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); IEM_MC_FETCH_MEM_U64(u64Tmp, pIemCpu->iEffSeg, GCPtrEffDst); IEM_MC_REF_LOCAL(pu64Dst, u64Tmp); Index: /trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp =================================================================== --- /trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp (revision 42486) +++ /trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp (revision 42487) @@ -82,14 +82,17 @@ #define IEM_OPCODE_GET_NEXT_U8(a_pu8) do { *(a_pu8) = g_bRandom; CHK_PTYPE(uint8_t *, a_pu8); } while (0) +#define IEM_OPCODE_GET_NEXT_S8(a_pi8) do { *(a_pi8) = g_bRandom; CHK_PTYPE(int8_t *, a_pi8); } while (0) +#define IEM_OPCODE_GET_NEXT_S8_SX_U16(a_pu16) do { *(a_pu16) = g_bRandom; CHK_PTYPE(uint16_t *, a_pu16); } while (0) +#define IEM_OPCODE_GET_NEXT_S8_SX_U32(a_pu32) do { *(a_pu32) = g_bRandom; CHK_PTYPE(uint32_t *, a_pu32); } while (0) +#define IEM_OPCODE_GET_NEXT_S8_SX_U64(a_pu64) do { *(a_pu64) = g_bRandom; CHK_PTYPE(uint64_t *, a_pu64); } while (0) #define IEM_OPCODE_GET_NEXT_U16(a_pu16) do { *(a_pu16) = g_bRandom; CHK_PTYPE(uint16_t *, a_pu16); } while (0) #define IEM_OPCODE_GET_NEXT_U16_ZX_U32(a_pu32) do { *(a_pu32) = g_bRandom; CHK_PTYPE(uint32_t *, a_pu32); } while (0) #define IEM_OPCODE_GET_NEXT_U16_ZX_U64(a_pu64) do { *(a_pu64) = g_bRandom; CHK_PTYPE(uint64_t *, a_pu64); } while (0) +#define IEM_OPCODE_GET_NEXT_S16(a_pi16) do { *(a_pi16) = g_bRandom; CHK_PTYPE(int16_t *, a_pi16); } while (0) #define IEM_OPCODE_GET_NEXT_U32(a_pu32) do { *(a_pu32) = g_bRandom; CHK_PTYPE(uint32_t *, a_pu32); } while (0) #define IEM_OPCODE_GET_NEXT_U32_ZX_U64(a_pu64) do { *(a_pu64) = g_bRandom; CHK_PTYPE(uint64_t *, a_pu64); } while (0) +#define IEM_OPCODE_GET_NEXT_S32(a_pi32) do { *(a_pi32) = g_bRandom; CHK_PTYPE(int32_t *, a_pi32); } while (0) #define IEM_OPCODE_GET_NEXT_S32_SX_U64(a_pu64) do { *(a_pu64) = g_bRandom; CHK_PTYPE(uint64_t *, a_pu64); } while (0) #define IEM_OPCODE_GET_NEXT_U64(a_pu64) do { *(a_pu64) = g_bRandom; CHK_PTYPE(uint64_t *, a_pu64); } while (0) -#define IEM_OPCODE_GET_NEXT_S8(a_pi8) do { *(a_pi8) = g_bRandom; CHK_PTYPE(int8_t *, a_pi8); } while (0) -#define IEM_OPCODE_GET_NEXT_S16(a_pi16) do { *(a_pi16) = g_bRandom; CHK_PTYPE(int16_t *, a_pi16); } while (0) -#define IEM_OPCODE_GET_NEXT_S32(a_pi32) do { *(a_pi32) = g_bRandom; CHK_PTYPE(int32_t *, a_pi32); } while (0) #define IEMOP_HLP_NO_LOCK_PREFIX() do { } while (0) #define IEMOP_HLP_NO_64BIT() do { } while (0)