Index: /trunk/include/VBox/err.h =================================================================== --- /trunk/include/VBox/err.h (revision 42419) +++ /trunk/include/VBox/err.h (revision 42420) @@ -592,4 +592,7 @@ /** Incompatible CPUM configuration. */ #define VERR_CPUM_INCOMPATIBLE_CONFIG (-1751) +/** CPUMR3DisasmInstrCPU unexpectedly failed to determin the hidden + * parts of the CS register. */ +#define VERR_CPUM_HIDDEN_CS_LOAD_ERROR (-1752) /** @} */ Index: /trunk/include/VBox/vmm/cpum.h =================================================================== --- /trunk/include/VBox/vmm/cpum.h (revision 42419) +++ /trunk/include/VBox/vmm/cpum.h (revision 42420) @@ -356,5 +356,5 @@ VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu); -/** @name Changed flags +/** @name Changed flags. * These flags are used to keep track of which important register that * have been changed since last they were reset. The only one allowed @@ -370,14 +370,13 @@ #define CPUM_CHANGED_IDTR RT_BIT(6) #define CPUM_CHANGED_LDTR RT_BIT(7) -#define CPUM_CHANGED_TR RT_BIT(8) +#define CPUM_CHANGED_TR RT_BIT(8) /**@< Currently unused. */ #define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9) -#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) +#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) /**@< Currently unused. */ #define CPUM_CHANGED_CPUID RT_BIT(11) -/** All except CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */ #define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \ | CPUM_CHANGED_CR0 \ + | CPUM_CHANGED_CR4 \ | CPUM_CHANGED_GLOBAL_TLB_FLUSH \ | CPUM_CHANGED_CR3 \ - | CPUM_CHANGED_CR4 \ | CPUM_CHANGED_GDTR \ | CPUM_CHANGED_IDTR \ @@ -387,9 +386,4 @@ | CPUM_CHANGED_HIDDEN_SEL_REGS \ | CPUM_CHANGED_CPUID ) -/** This one is used by raw-mode to indicate that the hidden register - * information is not longer reliable and have to be re-determined. - * - * @remarks This must not be part of CPUM_CHANGED_ALL! */ -#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12) /** @} */ @@ -407,5 +401,4 @@ VMMDECL(void) CPUMDeactivateHyperDebugState(PVMCPU pVCpu); VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu); -VMMDECL(bool) CPUMAreHiddenSelRegsValid(PVMCPU pVCpu); VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu); VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu); Index: /trunk/include/VBox/vmm/dbgf.h =================================================================== --- /trunk/include/VBox/vmm/dbgf.h (revision 42419) +++ /trunk/include/VBox/vmm/dbgf.h (revision 42420) @@ -873,7 +873,4 @@ /** No address in the output. */ #define DBGF_DISAS_FLAGS_NO_ADDRESS RT_BIT(5) -/** Set if the hidden selector registers are known to be valid. (REM hack to - * avoid assertions.) */ -#define DBGF_DISAS_FLAGS_HID_SEL_REGS_VALID RT_BIT(6) /** Disassemble in the default mode of the specific context. */ #define DBGF_DISAS_FLAGS_DEFAULT_MODE UINT32_C(0x00000000) Index: /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp (revision 42419) +++ /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp (revision 42420) @@ -2531,20 +2531,4 @@ } -/** - * Checks if the hidden selector registers are valid for the specified CPU. - * - * @returns true if they are. - * @returns false if not. - * @param pVCpu Pointer to the VM. - */ -VMMDECL(bool) CPUMAreHiddenSelRegsValid(PVMCPU pVCpu) -{ - bool const fRc = !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID); - Assert(fRc || !HWACCMIsEnabled(pVCpu->CTX_SUFF(pVM))); - Assert(!pVCpu->cpum.s.fRemEntered); - return fRc; -} - - /** Index: /trunk/src/VBox/VMM/VMMAll/SELMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/SELMAll.cpp (revision 42419) +++ /trunk/src/VBox/VMM/VMMAll/SELMAll.cpp (revision 42420) @@ -104,8 +104,8 @@ { RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff; - if (CPUMAreHiddenSelRegsValid(pVCpu)) + if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg)) uFlat += pSReg->u64Base; else - uFlat += ((RTGCUINTPTR)pSReg->Sel << 4); + uFlat += (RTGCUINTPTR)pSReg->Sel << 4; return (RTGCPTR)uFlat; } Index: /trunk/src/VBox/VMM/VMMR3/CPUM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/CPUM.cpp (revision 42419) +++ /trunk/src/VBox/VMM/VMMR3/CPUM.cpp (revision 42420) @@ -83,5 +83,13 @@ #define CPUM_SAVED_STATE_VERSION_VER1_6 6 -#define CPUM_WITH_CHANGED_CPUMCTX + +/** + * This was used in the saved state up to the early life of version 14. + * + * It indicates that we may have some out-of-sync hidden segement registers. + * It is only relevant for raw-mode. + */ +#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12) + /******************************************************************************* @@ -2498,6 +2506,4 @@ pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID; pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel; - pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID; - pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel; } else @@ -2509,22 +2515,20 @@ } - /** @todo fix this. We can get most of the details from SELM after restore is - * done. */ - pVCpu->cpum.s.Guest.ldtr.fFlags = 0; - pVCpu->cpum.s.Guest.ldtr.ValidSel = 0; - pVCpu->cpum.s.Guest.tr.fFlags = 0; - pVCpu->cpum.s.Guest.tr.ValidSel = 0; + /* This might not be 104% correct, but I think it's close + enough for all practical purposes... (REM always loaded + LDTR registers.) */ + pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID; + pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel; } - + pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID; + pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel; } } - /* Older states does not set CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID for - raw-mode guest, so we have to do it ourselves. */ -/** @todo eliminate CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */ - if ( uVersion <= CPUM_SAVED_STATE_VERSION_VER3_2 - && !HWACCMIsEnabled(pVM)) + /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */ + if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2 + && uVersion <= CPUM_SAVED_STATE_VERSION_MEM) for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++) - pVM->aCpus[iCpu].cpum.s.fChanged |= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID; + pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID; /* @@ -3997,41 +4001,19 @@ && pCtx->eflags.Bits.u1VM == 0) { - if (CPUMAreHiddenSelRegsValid(pVCpu)) + if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs)) { - State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long; - State.GCPtrSegBase = pCtx->cs.u64Base; - State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base; - State.cbSegLimit = pCtx->cs.u32Limit; - enmDisCpuMode = (State.f64Bits) - ? DISCPUMODE_64BIT - : pCtx->cs.Attr.n.u1DefBig - ? DISCPUMODE_32BIT - : DISCPUMODE_16BIT; + CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs); + if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs)) + return VERR_CPUM_HIDDEN_CS_LOAD_ERROR; } - else - { - DBGFSELINFO SelInfo; - - rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs.Sel, &SelInfo); - if (RT_FAILURE(rc)) - { - AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs.Sel, GCPtrPC, rc)); - return rc; - } - - /* - * Validate the selector. - */ - rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss.Sel); - if (RT_FAILURE(rc)) - { - AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs.Sel, GCPtrPC, rc)); - return rc; - } - State.GCPtrSegBase = SelInfo.GCPtrBase; - State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase; - State.cbSegLimit = SelInfo.cbLimit; - enmDisCpuMode = SelInfo.u.Raw.Gen.u1DefBig ? DISCPUMODE_32BIT : DISCPUMODE_16BIT; - } + State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long; + State.GCPtrSegBase = pCtx->cs.u64Base; + State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base; + State.cbSegLimit = pCtx->cs.u32Limit; + enmDisCpuMode = (State.f64Bits) + ? DISCPUMODE_64BIT + : pCtx->cs.Attr.n.u1DefBig + ? DISCPUMODE_32BIT + : DISCPUMODE_16BIT; } else @@ -4205,9 +4187,4 @@ PATMRawEnter(pVM, pCtxCore); } - - /* - * Invalidate the hidden registers. - */ - pVCpu->cpum.s.fChanged |= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID; /* @@ -4330,8 +4307,8 @@ /* - * Get and reset the flags, leaving CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID set. + * Get and reset the flags. */ uint32_t fFlags = pVCpu->cpum.s.fChanged; - pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID; /* leave it set */ + pVCpu->cpum.s.fChanged = 0; /** @todo change the switcher to use the fChanged flags. */ @@ -4348,5 +4325,5 @@ /** - * Leaves REM and works the CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID flag. + * Leaves REM. * * @param pVCpu Pointer to the VMCPU. @@ -4359,9 +4336,4 @@ Assert(pVCpu->cpum.s.fRemEntered); - if (fNoOutOfSyncSels) - pVCpu->cpum.s.fChanged &= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID; - else - pVCpu->cpum.s.fChanged |= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID; - pVCpu->cpum.s.fRemEntered = false; } Index: /trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp (revision 42419) +++ /trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp (revision 42420) @@ -340,4 +340,5 @@ VMCPU_ASSERT_EMT(pVCpu); RTGCPTR GCPtr = *pGCPtr; + int rc; /* @@ -345,21 +346,37 @@ */ PCCPUMCTXCORE pCtxCore = NULL; - PCPUMSELREGHID pHiddenSel = NULL; - int rc; - if (fFlags & (DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_CURRENT_HYPER)) - { - if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST) - pCtxCore = CPUMGetGuestCtxCore(pVCpu); + PCCPUMSELREG pSRegCS = NULL; + if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST) + { + pCtxCore = CPUMGetGuestCtxCore(pVCpu); + Sel = pCtxCore->cs.Sel; + pSRegCS = &pCtxCore->cs; + GCPtr = pCtxCore->rip; + } + else if (fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER) + { + pCtxCore = CPUMGetHyperCtxCore(pVCpu); + Sel = pCtxCore->cs.Sel; + GCPtr = pCtxCore->rip; + } + /* + * Check if the selector matches the guest CS, use the hidden + * registers from that if they are valid. Saves time and effort. + */ + else + { + pCtxCore = CPUMGetGuestCtxCore(pVCpu); + if (pCtxCore->cs.Sel == Sel && Sel != DBGF_SEL_FLAT) + pSRegCS = &pCtxCore->cs; else - pCtxCore = CPUMGetHyperCtxCore(pVCpu); - Sel = pCtxCore->cs.Sel; - pHiddenSel = (PCPUMSELREGHID)&pCtxCore->cs; - GCPtr = pCtxCore->rip; + pCtxCore = NULL; } /* * Read the selector info - assume no stale selectors and nasty stuff like that. - * Since the selector flags in the CPUMCTX structures aren't up to date unless - * we recently visited REM, we'll not search for the selector there. + * + * Note! We CANNOT load invalid hidden selector registers since that would + * mean that log/debug statements or the debug will influence the + * guest state and make things behave differently. */ DBGFSELINFO SelInfo; @@ -367,15 +384,14 @@ bool fRealModeAddress = false; - if ( pHiddenSel - && ( (fFlags & DBGF_DISAS_FLAGS_HID_SEL_REGS_VALID) - || CPUMAreHiddenSelRegsValid(pVCpu))) + if ( pSRegCS + && CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS)) { SelInfo.Sel = Sel; SelInfo.SelGate = 0; - SelInfo.GCPtrBase = pHiddenSel->u64Base; - SelInfo.cbLimit = pHiddenSel->u32Limit; + SelInfo.GCPtrBase = pSRegCS->u64Base; + SelInfo.cbLimit = pSRegCS->u32Limit; SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode) ? DBGFSELINFO_FLAGS_LONG_MODE - : enmMode != PGMMODE_REAL && (!pCtxCore || !pCtxCore->eflags.Bits.u1VM) + : enmMode != PGMMODE_REAL && !pCtxCore->eflags.Bits.u1VM ? DBGFSELINFO_FLAGS_PROT_MODE : DBGFSELINFO_FLAGS_REAL_MODE; @@ -385,10 +401,10 @@ SelInfo.u.Raw.Gen.u16LimitLow = 0xffff; SelInfo.u.Raw.Gen.u4LimitHigh = 0xf; - SelInfo.u.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present; - SelInfo.u.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;; - SelInfo.u.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig; - SelInfo.u.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long; - SelInfo.u.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType; - SelInfo.u.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type; + SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present; + SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;; + SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig; + SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long; + SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType; + SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type; fRealModeAddress = !!(SelInfo.fFlags & DBGFSELINFO_FLAGS_REAL_MODE); } @@ -409,19 +425,18 @@ SelInfo.u.Raw.Gen.u4LimitHigh = 0xf; - if ( (fFlags & DBGF_DISAS_FLAGS_HID_SEL_REGS_VALID) - || CPUMAreHiddenSelRegsValid(pVCpu)) - { /* Assume the current CS defines the execution mode. */ - pCtxCore = CPUMGetGuestCtxCore(pVCpu); - pHiddenSel = (CPUMSELREGHID *)&pCtxCore->cs; - - SelInfo.u.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present; - SelInfo.u.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;; - SelInfo.u.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig; - SelInfo.u.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long; - SelInfo.u.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType; - SelInfo.u.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type; + pSRegCS = &CPUMGetGuestCtxCore(pVCpu)->cs; + if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS)) + { + /* Assume the current CS defines the execution mode. */ + SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present; + SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;; + SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig; + SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long; + SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType; + SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type; } else { + pSRegCS = NULL; SelInfo.u.Raw.Gen.u1Present = 1; SelInfo.u.Raw.Gen.u1Granularity = 1; Index: /trunk/src/recompiler/VBoxREMWrapper.cpp =================================================================== --- /trunk/src/recompiler/VBoxREMWrapper.cpp (revision 42419) +++ /trunk/src/recompiler/VBoxREMWrapper.cpp (revision 42420) @@ -1200,5 +1200,4 @@ static REMFNDESC g_aVMMImports[] = { - { "CPUMAreHiddenSelRegsValid", VMM_FN(CPUMAreHiddenSelRegsValid), &g_aArgsVMCPU[0], RT_ELEMENTS(g_aArgsVMCPU), REMFNDESC_FLAGS_RET_INT, sizeof(bool), NULL }, { "CPUMR3RemEnter", VMM_FN(CPUMR3RemEnter), &g_aArgsCPUMR3RemEnter[0], RT_ELEMENTS(g_aArgsCPUMR3RemEnter), REMFNDESC_FLAGS_RET_INT, sizeof(uint32_t), NULL }, { "CPUMR3RemLeave", VMM_FN(CPUMR3RemLeave), &g_aArgsCPUMR3RemLeave[0], RT_ELEMENTS(g_aArgsCPUMR3RemLeave), REMFNDESC_FLAGS_RET_VOID, 0, NULL }, Index: /trunk/src/recompiler/VBoxRecompiler.c =================================================================== --- /trunk/src/recompiler/VBoxRecompiler.c (revision 42419) +++ /trunk/src/recompiler/VBoxRecompiler.c (revision 42420) @@ -1126,6 +1126,5 @@ 0, /* GCPtr */ DBGF_DISAS_FLAGS_CURRENT_GUEST - | DBGF_DISAS_FLAGS_DEFAULT_MODE - | DBGF_DISAS_FLAGS_HID_SEL_REGS_VALID, + | DBGF_DISAS_FLAGS_DEFAULT_MODE, szBuf, sizeof(szBuf), @@ -2330,11 +2329,16 @@ if (pCtx->ldtr.fFlags & CPUMSELREG_FLAGS_VALID) { - pVM->rem.s.Env.ldt.selector = pCtx->ldtr.Sel; - pVM->rem.s.Env.ldt.base = pCtx->ldtr.u64Base; - pVM->rem.s.Env.ldt.limit = pCtx->ldtr.u32Limit; - pVM->rem.s.Env.ldt.flags = (pCtx->ldtr.Attr.u << 8) & 0xFFFFFF; + pVM->rem.s.Env.ldt.selector = pCtx->ldtr.Sel; + pVM->rem.s.Env.ldt.newselector = 0; + pVM->rem.s.Env.ldt.fVBoxFlags = pCtx->ldtr.fFlags; + pVM->rem.s.Env.ldt.base = pCtx->ldtr.u64Base; + pVM->rem.s.Env.ldt.limit = pCtx->ldtr.u32Limit; + pVM->rem.s.Env.ldt.flags = (pCtx->ldtr.Attr.u << 8) & 0xFFFFFF; } else + { + AssertFailed(); /* Shouldn't happen, see cpumR3LoadExec. */ sync_ldtr(&pVM->rem.s.Env, pCtx->ldtr.Sel); + } } @@ -3997,6 +4001,5 @@ 0, /* GCPtr */ DBGF_DISAS_FLAGS_CURRENT_GUEST - | DBGF_DISAS_FLAGS_DEFAULT_MODE - | DBGF_DISAS_FLAGS_HID_SEL_REGS_VALID, + | DBGF_DISAS_FLAGS_DEFAULT_MODE, szBuf, sizeof(szBuf),