Index: /trunk/include/VBox/vmm/hwacc_vmx.h =================================================================== --- /trunk/include/VBox/vmm/hwacc_vmx.h (revision 42372) +++ /trunk/include/VBox/vmm/hwacc_vmx.h (revision 42373) @@ -475,6 +475,6 @@ /** 13 Guest software attempted to execute INVD. */ #define VMX_EXIT_INVD 13 -/** 14 Guest software attempted to execute INVPG. */ -#define VMX_EXIT_INVPG 14 +/** 14 Guest software attempted to execute INVLPG. */ +#define VMX_EXIT_INVLPG 14 /** 15 Guest software attempted to execute RDPMC. */ #define VMX_EXIT_RDPMC 15 Index: /trunk/src/VBox/VMM/VMMAll/EMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/EMAll.cpp (revision 42372) +++ /trunk/src/VBox/VMM/VMMAll/EMAll.cpp (revision 42373) @@ -201,5 +201,5 @@ /** - * Locks REM execution to a single VCpu + * Locks REM execution to a single VCPU. * * @param pVM Pointer to the VM. @@ -666,5 +666,5 @@ /** - * Interpret CPUID given the parameters in the CPU context + * Interpret CPUID given the parameters in the CPU context. * * @returns VBox status code. @@ -694,5 +694,5 @@ /** - * Interpret RDTSC + * Interpret RDTSC. * * @returns VBox status code. @@ -721,5 +721,5 @@ /** - * Interpret RDTSCP + * Interpret RDTSCP. * * @returns VBox status code. @@ -756,5 +756,5 @@ /** - * Interpret RDPMC + * Interpret RDPMC. * * @returns VBox status code. @@ -856,9 +856,6 @@ - -/* VT-x only: */ - -/** - * Interpret INVLPG +/** + * Interpret INVLPG. * * @returns VBox status code. @@ -866,5 +863,5 @@ * @param pVCpu Pointer to the VMCPU. * @param pRegFrame The register frame. - * @param pAddrGC Operand address + * @param pAddrGC Operand address. * */ @@ -890,6 +887,8 @@ -/** - * Update CRx +/* VT-x only: */ + +/** + * Update CRx. * * @returns VBox status code. @@ -1032,5 +1031,5 @@ /** - * Interpret CRx write + * Interpret CRx write. * * @returns VBox status code. @@ -1064,5 +1063,5 @@ /** - * Interpret LMSW + * Interpret LMSW. * * @returns VBox status code. @@ -1086,7 +1085,6 @@ - -/** - * Interpret CLTS +/** + * Interpret CLTS. * * @returns VBox status code. @@ -1107,5 +1105,5 @@ /** - * Interpret CRx read + * Interpret CRx read. * * @returns VBox status code. @@ -1140,5 +1138,5 @@ /** - * Interpret DRx write + * Interpret DRx write. * * @returns VBox status code. @@ -1179,5 +1177,5 @@ /** - * Interpret DRx read + * Interpret DRx read. * * @returns VBox status code. Index: /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp (revision 42372) +++ /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp (revision 42373) @@ -54,5 +54,5 @@ * Internal Functions * *******************************************************************************/ -static int hmR0SvmInterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID); +static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame); static int hmR0SvmEmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx); static void hmR0SvmSetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite); @@ -2249,13 +2249,13 @@ } - case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */ + case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVLPG. */ { Log2(("SVM: invlpg\n")); - STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg); + STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvlpg); Assert(!pVM->hwaccm.s.fNestedPaging); /* Truly a pita. Why can't SVM give the same information as VT-x? */ - rc = hmR0SvmInterpretInvpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID); + rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx)); if (rc == VINF_SUCCESS) { @@ -2928,5 +2928,5 @@ /** - * Interprets INVLPG. + * Worker for Interprets INVLPG. * * @return VBox status code. @@ -2934,11 +2934,9 @@ * @param pCpu Pointer to the CPU info struct. * @param pRegFrame Pointer to the register frame. - * @param ASID Tagged TLB id for the guest. */ -static int hmR0svmInterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID) +static int hmR0svmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame) { DISQPVPARAMVAL param1; RTGCPTR addr; - NOREF(uASID); int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->Param1, ¶m1, DISQPVWHICH_SRC); @@ -2981,9 +2979,8 @@ * @param pVM Pointer to the VM. * @param pRegFrame Pointer to the register frame. - * @param ASID Tagged TLB id for the guest. * * @remarks Updates the EIP if an instruction was executed successfully. */ -static int hmR0SvmInterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID) +static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame) { /* @@ -2996,5 +2993,5 @@ if (RT_SUCCESS(rc) && pDis->pCurInstr->uOpcode == OP_INVLPG) { - rc = hmR0svmInterpretInvlPg(pVCpu, pDis, pRegFrame, uASID); + rc = hmR0svmInterpretInvlPgEx(pVCpu, pDis, pRegFrame); if (RT_SUCCESS(rc)) pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */ Index: /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (revision 42372) +++ /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (revision 42373) @@ -3660,173 +3660,156 @@ switch (pDis->pCurInstr->uOpcode) { - case OP_CLI: - pCtx->eflags.Bits.u1IF = 0; - STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCli); - break; - - case OP_STI: - pCtx->eflags.Bits.u1IF = 1; - EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + pDis->cbInstr); - Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)); - rc2 = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, - VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI); - AssertRC(rc2); - STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitSti); - break; - - case OP_HLT: - fUpdateRIP = false; - rc = VINF_EM_HALT; - pCtx->rip += pDis->cbInstr; - STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt); - break; - - case OP_POPF: - { - RTGCPTR GCPtrStack; - uint32_t cbParm; - uint32_t uMask; - X86EFLAGS eflags; - - if (pDis->fPrefix & DISPREFIX_OPSIZE) + case OP_CLI: + pCtx->eflags.Bits.u1IF = 0; + STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCli); + break; + + case OP_STI: + pCtx->eflags.Bits.u1IF = 1; + EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + pDis->cbInstr); + Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)); + rc2 = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, + VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI); + AssertRC(rc2); + STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitSti); + break; + + case OP_HLT: + fUpdateRIP = false; + rc = VINF_EM_HALT; + pCtx->rip += pDis->cbInstr; + STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt); + break; + + case OP_POPF: { - cbParm = 4; - uMask = 0xffffffff; - } - else - { - cbParm = 2; - uMask = 0xffff; - } - - rc2 = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack); - if (RT_FAILURE(rc2)) - { - rc = VERR_EM_INTERPRETER; + RTGCPTR GCPtrStack; + uint32_t cbParm; + uint32_t uMask; + X86EFLAGS eflags; + + if (pDis->fPrefix & DISPREFIX_OPSIZE) + { + cbParm = 4; + uMask = 0xffffffff; + } + else + { + cbParm = 2; + uMask = 0xffff; + } + + rc2 = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack); + if (RT_FAILURE(rc2)) + { + rc = VERR_EM_INTERPRETER; + break; + } + eflags.u = 0; + rc2 = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm); + if (RT_FAILURE(rc2)) + { + rc = VERR_EM_INTERPRETER; + break; + } + LogFlow(("POPF %x -> %RGv mask=%x\n", eflags.u, pCtx->rsp, uMask)); + pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) + | (eflags.u & X86_EFL_POPF_BITS & uMask); + /* RF cleared when popped in real mode; see pushf description in AMD manual. */ + pCtx->eflags.Bits.u1RF = 0; + pCtx->esp += cbParm; + pCtx->esp &= uMask; + + STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPopf); break; } - eflags.u = 0; - rc2 = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm); - if (RT_FAILURE(rc2)) + + case OP_PUSHF: { - rc = VERR_EM_INTERPRETER; + RTGCPTR GCPtrStack; + uint32_t cbParm; + uint32_t uMask; + X86EFLAGS eflags; + + if (pDis->fPrefix & DISPREFIX_OPSIZE) + { + cbParm = 4; + uMask = 0xffffffff; + } + else + { + cbParm = 2; + uMask = 0xffff; + } + + rc2 = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, + &GCPtrStack); + if (RT_FAILURE(rc2)) + { + rc = VERR_EM_INTERPRETER; + break; + } + eflags = pCtx->eflags; + /* RF & VM cleared when pushed in real mode; see pushf description in AMD manual. */ + eflags.Bits.u1RF = 0; + eflags.Bits.u1VM = 0; + + rc2 = PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm); + if (RT_FAILURE(rc2)) + { + rc = VERR_EM_INTERPRETER; + break; + } + LogFlow(("PUSHF %x -> %RGv\n", eflags.u, GCPtrStack)); + pCtx->esp -= cbParm; + pCtx->esp &= uMask; + STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPushf); break; } - LogFlow(("POPF %x -> %RGv mask=%x\n", eflags.u, pCtx->rsp, uMask)); - pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (eflags.u & X86_EFL_POPF_BITS & uMask); - /* RF cleared when popped in real mode; see pushf description in AMD manual. */ - pCtx->eflags.Bits.u1RF = 0; - pCtx->esp += cbParm; - pCtx->esp &= uMask; - - STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPopf); - break; - } - - case OP_PUSHF: - { - RTGCPTR GCPtrStack; - uint32_t cbParm; - uint32_t uMask; - X86EFLAGS eflags; - - if (pDis->fPrefix & DISPREFIX_OPSIZE) + + case OP_IRET: { - cbParm = 4; - uMask = 0xffffffff; - } - else - { - cbParm = 2; - uMask = 0xffff; - } - - rc2 = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, - &GCPtrStack); - if (RT_FAILURE(rc2)) - { - rc = VERR_EM_INTERPRETER; + RTGCPTR GCPtrStack; + uint32_t uMask = 0xffff; + uint16_t aIretFrame[3]; + + if (pDis->fPrefix & (DISPREFIX_OPSIZE | DISPREFIX_ADDRSIZE)) + { + rc = VERR_EM_INTERPRETER; + break; + } + + rc2 = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack); + if (RT_FAILURE(rc2)) + { + rc = VERR_EM_INTERPRETER; + break; + } + rc2 = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame)); + if (RT_FAILURE(rc2)) + { + rc = VERR_EM_INTERPRETER; + break; + } + pCtx->ip = aIretFrame[0]; + pCtx->cs.Sel = aIretFrame[1]; + pCtx->cs.ValidSel = aIretFrame[1]; + pCtx->cs.u64Base = (uint32_t)pCtx->cs.Sel << 4; + pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) + | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask); + pCtx->sp += sizeof(aIretFrame); + + LogFlow(("iret to %04x:%x\n", pCtx->cs.Sel, pCtx->ip)); + fUpdateRIP = false; + STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIret); break; } - eflags = pCtx->eflags; - /* RF & VM cleared when pushed in real mode; see pushf description in AMD manual. */ - eflags.Bits.u1RF = 0; - eflags.Bits.u1VM = 0; - - rc2 = PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm); - if (RT_FAILURE(rc2)) - { - rc = VERR_EM_INTERPRETER; - break; - } - LogFlow(("PUSHF %x -> %RGv\n", eflags.u, GCPtrStack)); - pCtx->esp -= cbParm; - pCtx->esp &= uMask; - STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPushf); - break; - } - - case OP_IRET: - { - RTGCPTR GCPtrStack; - uint32_t uMask = 0xffff; - uint16_t aIretFrame[3]; - - if (pDis->fPrefix & (DISPREFIX_OPSIZE | DISPREFIX_ADDRSIZE)) - { - rc = VERR_EM_INTERPRETER; - break; - } - - rc2 = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack); - if (RT_FAILURE(rc2)) - { - rc = VERR_EM_INTERPRETER; - break; - } - rc2 = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame)); - if (RT_FAILURE(rc2)) - { - rc = VERR_EM_INTERPRETER; - break; - } - pCtx->ip = aIretFrame[0]; - pCtx->cs.Sel = aIretFrame[1]; - pCtx->cs.ValidSel = aIretFrame[1]; - pCtx->cs.u64Base = (uint32_t)pCtx->cs.Sel << 4; - pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) - | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask); - pCtx->sp += sizeof(aIretFrame); - - LogFlow(("iret to %04x:%x\n", pCtx->cs.Sel, pCtx->ip)); - fUpdateRIP = false; - STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIret); - break; - } - - case OP_INT: - { - uint32_t intInfo2; - - LogFlow(("Realmode: INT %x\n", pDis->Param1.uValue & 0xff)); - intInfo2 = pDis->Param1.uValue & 0xff; - intInfo2 |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT); - intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT); - - rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0); - AssertRC(VBOXSTRICTRC_VAL(rc)); - fUpdateRIP = false; - STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt); - break; - } - - case OP_INTO: - { - if (pCtx->eflags.Bits.u1OF) + + case OP_INT: { uint32_t intInfo2; - LogFlow(("Realmode: INTO\n")); - intInfo2 = X86_XCPT_OF; + LogFlow(("Realmode: INT %x\n", pDis->Param1.uValue & 0xff)); + intInfo2 = pDis->Param1.uValue & 0xff; intInfo2 |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT); intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT); @@ -3836,28 +3819,46 @@ fUpdateRIP = false; STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt); + break; } - break; - } - - case OP_INT3: - { - uint32_t intInfo2; - - LogFlow(("Realmode: INT 3\n")); - intInfo2 = 3; - intInfo2 |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT); - intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT); - - rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0); - AssertRC(VBOXSTRICTRC_VAL(rc)); - fUpdateRIP = false; - STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt); - break; - } - - default: - rc = EMInterpretInstructionDisasState(pVCpu, pDis, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR); - fUpdateRIP = false; - break; + + case OP_INTO: + { + if (pCtx->eflags.Bits.u1OF) + { + uint32_t intInfo2; + + LogFlow(("Realmode: INTO\n")); + intInfo2 = X86_XCPT_OF; + intInfo2 |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT); + intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT); + + rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0); + AssertRC(VBOXSTRICTRC_VAL(rc)); + fUpdateRIP = false; + STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt); + } + break; + } + + case OP_INT3: + { + uint32_t intInfo2; + + LogFlow(("Realmode: INT 3\n")); + intInfo2 = 3; + intInfo2 |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT); + intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT); + + rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0); + AssertRC(VBOXSTRICTRC_VAL(rc)); + fUpdateRIP = false; + STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt); + break; + } + + default: + rc = EMInterpretInstructionDisasState(pVCpu, pDis, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR); + fUpdateRIP = false; + break; } @@ -3895,19 +3896,9 @@ switch (vector) { - case X86_XCPT_DE: - STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE); - break; - case X86_XCPT_UD: - STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD); - break; - case X86_XCPT_SS: - STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS); - break; - case X86_XCPT_NP: - STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP); - break; - case X86_XCPT_XF: - STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestXF); - break; + case X86_XCPT_DE: STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE); break; + case X86_XCPT_UD: STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD); break; + case X86_XCPT_SS: STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS); break; + case X86_XCPT_NP: STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP); break; + case X86_XCPT_XF: STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestXF); break; } @@ -4167,10 +4158,10 @@ } - case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */ + case VMX_EXIT_INVLPG: /* 14 Guest software attempted to execute INVLPG. */ { Log2(("VMX: invlpg\n")); Assert(!pVM->hwaccm.s.fNestedPaging); - STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg); + STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvlpg); rc = EMInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), exitQualification); if (rc == VINF_SUCCESS) @@ -4735,5 +4726,5 @@ case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */ case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */ - case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */ + case VMX_EXIT_INVLPG: /* 14 Guest software attempted to execute INVLPG. */ case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */ case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */ Index: /trunk/src/VBox/VMM/VMMR3/HWACCM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/HWACCM.cpp (revision 42372) +++ /trunk/src/VBox/VMM/VMMR3/HWACCM.cpp (revision 42373) @@ -1,5 +1,5 @@ /* $Id$ */ /** @file - * HWACCM - Intel/AMD VM Hardware Support Manager + * HWACCM - Intel/AMD VM Hardware Support Manager. */ @@ -73,5 +73,5 @@ EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."), EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."), - EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."), + EXIT_REASON(VMX_EXIT_INVLPG , 14, "Guest software attempted to execute INVLPG."), EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."), EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."), @@ -510,5 +510,5 @@ HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestXF, "/HWACCM/CPU%d/Exit/Trap/Gst/#XF"); HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestXcpUnk, "/HWACCM/CPU%d/Exit/Trap/Gst/Other"); - HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg"); + HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvlpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg"); HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd"); HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid"); Index: /trunk/src/VBox/VMM/include/HWACCMInternal.h =================================================================== --- /trunk/src/VBox/VMM/include/HWACCMInternal.h (revision 42372) +++ /trunk/src/VBox/VMM/include/HWACCMInternal.h (revision 42373) @@ -785,5 +785,5 @@ STAMCOUNTER StatExitGuestXF; STAMCOUNTER StatExitGuestXcpUnk; - STAMCOUNTER StatExitInvpg; + STAMCOUNTER StatExitInvlpg; STAMCOUNTER StatExitInvd; STAMCOUNTER StatExitCpuid;