Index: /trunk/include/VBox/dis.h
===================================================================
--- /trunk/include/VBox/dis.h	(revision 41743)
+++ /trunk/include/VBox/dis.h	(revision 41744)
@@ -194,5 +194,5 @@
 /** @name 64-bit general register indexes.
  * This matches the AMD64 register encoding.  It is found used in
- * DISOPPARAM::base.reg_gen and DISOPPARAM::Index.idxGenReg.
+ * DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
  * @note  Safe to assume same values as the 16-bit and 32-bit general registers.
  * @{
@@ -218,5 +218,5 @@
 /** @name 32-bit general register indexes.
  * This matches the AMD64 register encoding.  It is found used in
- * DISOPPARAM::base.reg_gen and DISOPPARAM::Index.idxGenReg.
+ * DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
  * @note  Safe to assume same values as the 16-bit and 64-bit general registers.
  * @{
@@ -242,5 +242,5 @@
 /** @name 16-bit general register indexes.
  * This matches the AMD64 register encoding.  It is found used in
- * DISOPPARAM::base.reg_gen and DISOPPARAM::Index.idxGenReg.
+ * DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
  * @note  Safe to assume same values as the 32-bit and 64-bit general registers.
  * @{
@@ -266,5 +266,5 @@
 /** @name 8-bit general register indexes.
  * This mostly (?) matches the AMD64 register encoding.  It is found used in
- * DISOPPARAM::base.reg_gen and DISOPPARAM::Index.idxGenReg.
+ * DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
  * @{
  */
@@ -293,5 +293,5 @@
 /** @name Segment registerindexes.
  * This matches the AMD64 register encoding.  It is found used in
- * DISOPPARAM::base.reg_seg.
+ * DISOPPARAM::Base.idxSegReg.
  * @{
  */
@@ -311,5 +311,5 @@
 /** @name FPU register indexes.
  * This matches the AMD64 register encoding.  It is found used in
- * DISOPPARAM::base.reg_fp.
+ * DISOPPARAM::Base.idxFpuReg.
  * @{
  */
@@ -326,5 +326,5 @@
 /** @name Control register indexes.
  * This matches the AMD64 register encoding.  It is found used in
- * DISOPPARAM::base.reg_ctrl.
+ * DISOPPARAM::Base.idxCtrlReg.
  * @{
  */
@@ -339,5 +339,5 @@
 /** @name Debug register indexes.
  * This matches the AMD64 register encoding.  It is found used in
- * DISOPPARAM::base.reg_dbg.
+ * DISOPPARAM::Base.idxDbgReg.
  * @{
  */
@@ -354,5 +354,5 @@
 /** @name MMX register indexes.
  * This matches the AMD64 register encoding.  It is found used in
- * DISOPPARAM::base.reg_mmx.
+ * DISOPPARAM::Base.idxMmxReg.
  * @{
  */
@@ -369,5 +369,5 @@
 /** @name SSE register indexes.
  * This matches the AMD64 register encoding.  It is found used in
- * DISOPPARAM::base.reg_xmm.
+ * DISOPPARAM::Base.idxXmmReg.
  * @{
  */
@@ -380,5 +380,5 @@
 #define DISXREG_XMM6                    UINT8_C(6)
 #define DISXREG_XMM7                    UINT8_C(7)
-/** @}  */
+/** @} */
 
 
@@ -388,42 +388,55 @@
 typedef struct DISOPPARAM
 {
-    /** Immediate value or address, if used. */
-    uint64_t        uValue;
     /** A combination of DISUSE_XXX. */
     uint64_t        fUse;
+    /** Immediate value or address, applicable if any of the flags included in
+     * DISUSE_IMMEDIATE are set in fUse. */
+    uint64_t        uValue;
+    /** Disposition.  */
     union
     {
+        /** 64-bit displacement, applicable if DISUSE_DISPLACEMENT64 is set in fUse.  */
         int64_t     i64;
+        uint64_t    u64;
+        /** 32-bit displacement, applicable if DISUSE_DISPLACEMENT32 or
+         * DISUSE_RIPDISPLACEMENT32  is set in fUse. */
         int32_t     i32;
+        uint32_t    u32;
+        /** 16-bit displacement, applicable if DISUSE_DISPLACEMENT16 is set in fUse.  */
         int32_t     i16;
+        uint32_t    u16;
+        /** 8-bit displacement, applicable if DISUSE_DISPLACEMENT8 is set in fUse.  */
         int32_t     i8;
-        uint64_t    u64;
-        uint32_t    u32;
-        uint32_t    u16;
         uint32_t    u8;
     } uDisp;
-    /** Copy of the corresponding DISOPCODE::fParam1 / DISOPCODE::fParam2 /
-     *  DISOPCODE::fParam3. */
-    uint32_t        fParam;
-
+    /** The base register from ModR/M or SIB, applicable if DISUSE_BASE is
+     * set in fUse. */
     union
     {
-        /** DISGREG_XXX. */
-        uint8_t     reg_gen;
-        /** DISFPREG_XXX */
-        uint8_t     reg_fp;
-        /** DISMREG_XXX. */
-        uint8_t     reg_mmx;
-        /** DISXREG_XXX. */
-        uint8_t     reg_xmm;
-        /** DISSELREG_XXX. */
-        uint8_t     reg_seg;
-        /** TR0-TR7  (no defines for these). */
-        uint8_t     reg_test;
-        /** DISCREG_XXX */
-        uint8_t     reg_ctrl;
-        /** DISDREG_XXX */
-        uint8_t     reg_dbg;
-    } base;
+        /** General register index (DISGREG_XXX), applicable if DISUSE_REG_GEN8,
+         * DISUSE_REG_GEN16, DISUSE_REG_GEN32 or DISUSE_REG_GEN64 is set in fUse. */
+        uint8_t     idxGenReg;
+        /** FPU stack register index (DISFPREG_XXX), applicable if DISUSE_REG_FP is
+         * set in fUse.  1:1 indexes. */
+        uint8_t     idxFpuReg;
+        /** MMX register index (DISMREG_XXX), applicable if DISUSE_REG_MMX is
+         * set in fUse.  1:1 indexes. */
+        uint8_t     idxMmxReg;
+        /** SSE register index (DISXREG_XXX), applicable if DISUSE_REG_XMM is
+         * set in fUse.  1:1 indexes. */
+        uint8_t     idxXmmReg;
+        /** Segment register index (DISSELREG_XXX), applicable if DISUSE_REG_SEG is
+         * set in fUse. */
+        uint8_t     idxSegReg;
+        /** Test register, TR0-TR7, present on early IA32 CPUs, applicable if
+         * DISUSE_REG_TEST is set in fUse.  No index defines for these. */
+        uint8_t     idxTestReg;
+        /** Control register index (DISCREG_XXX), applicable if DISUSE_REG_CR is
+         * set in fUse.  1:1 indexes. */
+        uint8_t     idxCtrlReg;
+        /** Debug register index (DISDREG_XXX), applicable if DISUSE_REG_DBG is
+         * set in fUse.  1:1 indexes. */
+        uint8_t     idxDbgReg;
+    } Base;
     /** The SIB index register meaning, applicable if DISUSE_INDEX is
      * set in fUse. */
@@ -438,4 +451,7 @@
     /** Parameter size. */
     uint8_t         cb;
+    /** Copy of the corresponding DISOPCODE::fParam1 / DISOPCODE::fParam2 /
+     * DISOPCODE::fParam3. */
+    uint32_t        fParam;
 } DISOPPARAM;
 AssertCompileSize(DISOPPARAM, 32);
Index: /trunk/src/VBox/Disassembler/DisasmCore.cpp
===================================================================
--- /trunk/src/VBox/Disassembler/DisasmCore.cpp	(revision 41743)
+++ /trunk/src/VBox/Disassembler/DisasmCore.cpp	(revision 41744)
@@ -643,5 +643,5 @@
     {
         pParam->fUse |= DISUSE_BASE | regtype;
-        pParam->base.reg_gen = base;
+        pParam->Base.idxGenReg = base;
     }
     return;   /* Already fetched everything in ParseSIB; no size returned */
@@ -742,13 +742,13 @@
                 {
                     pCpu->fPrefix &= ~DISPREFIX_LOCK;
-                    pParam->base.reg_ctrl = DISCREG_CR8;
+                    pParam->Base.idxCtrlReg = DISCREG_CR8;
                 }
                 else
-                    pParam->base.reg_ctrl = reg;
+                    pParam->Base.idxCtrlReg = reg;
                 return 0;
 
             case OP_PARM_D: //debug register
                 pParam->fUse |= DISUSE_REG_DBG;
-                pParam->base.reg_dbg = reg;
+                pParam->Base.idxDbgReg = reg;
                 return 0;
 
@@ -756,5 +756,5 @@
                 reg &= 7;   /* REX.R has no effect here */
                 pParam->fUse |= DISUSE_REG_MMX;
-                pParam->base.reg_mmx = reg;
+                pParam->Base.idxMmxReg = reg;
                 return 0;
 
@@ -768,5 +768,5 @@
                 reg &= 7;   /* REX.R has no effect here */
                 pParam->fUse |= DISUSE_REG_TEST;
-                pParam->base.reg_test = reg;
+                pParam->Base.idxTestReg = reg;
                 return 0;
 
@@ -779,5 +779,5 @@
             case OP_PARM_V: //XMM register
                 pParam->fUse |= DISUSE_REG_XMM;
-                pParam->base.reg_xmm = reg;
+                pParam->Base.idxXmmReg = reg;
                 return 0;
             }
@@ -1559,5 +1559,5 @@
         {
             /* Use 32-bit registers. */
-            pParam->base.reg_gen = pParam->fParam - OP_PARM_REG_GEN32_START;
+            pParam->Base.idxGenReg = pParam->fParam - OP_PARM_REG_GEN32_START;
             pParam->fUse  |= DISUSE_REG_GEN32;
             pParam->cb     = 4;
@@ -1567,10 +1567,10 @@
         {
             /* Use 64-bit registers. */
-            pParam->base.reg_gen = pParam->fParam - OP_PARM_REG_GEN32_START;
+            pParam->Base.idxGenReg = pParam->fParam - OP_PARM_REG_GEN32_START;
             if (    (pOp->fOpType & DISOPTYPE_REXB_EXTENDS_OPREG)
                 &&  pParam == &pCpu->Param1             /* ugly assumption that it only applies to the first parameter */
                 &&  (pCpu->fPrefix & DISPREFIX_REX)
                 &&  (pCpu->fRexPrefix & DISPREFIX_REX_FLAGS))
-                pParam->base.reg_gen += 8;
+                pParam->Base.idxGenReg += 8;
 
             pParam->fUse  |= DISUSE_REG_GEN64;
@@ -1580,5 +1580,5 @@
         {
             /* Use 16-bit registers. */
-            pParam->base.reg_gen = pParam->fParam - OP_PARM_REG_GEN32_START;
+            pParam->Base.idxGenReg = pParam->fParam - OP_PARM_REG_GEN32_START;
             pParam->fUse  |= DISUSE_REG_GEN16;
             pParam->cb     = 2;
@@ -1590,5 +1590,5 @@
     {
         /* Segment ES..GS registers. */
-        pParam->base.reg_seg = (DISSELREG)(pParam->fParam - OP_PARM_REG_SEG_START);
+        pParam->Base.idxSegReg = (DISSELREG)(pParam->fParam - OP_PARM_REG_SEG_START);
         pParam->fUse  |= DISUSE_REG_SEG;
         pParam->cb     = 2;
@@ -1598,5 +1598,5 @@
     {
         /* 16-bit AX..DI registers. */
-        pParam->base.reg_gen = pParam->fParam - OP_PARM_REG_GEN16_START;
+        pParam->Base.idxGenReg = pParam->fParam - OP_PARM_REG_GEN16_START;
         pParam->fUse  |= DISUSE_REG_GEN16;
         pParam->cb     = 2;
@@ -1606,5 +1606,5 @@
     {
         /* 8-bit AL..DL, AH..DH registers. */
-        pParam->base.reg_gen = pParam->fParam - OP_PARM_REG_GEN8_START;
+        pParam->Base.idxGenReg = pParam->fParam - OP_PARM_REG_GEN8_START;
         pParam->fUse  |= DISUSE_REG_GEN8;
         pParam->cb     = 1;
@@ -1616,5 +1616,5 @@
                 &&  (pCpu->fPrefix & DISPREFIX_REX)
                 &&  (pCpu->fRexPrefix & DISPREFIX_REX_FLAGS))
-                pParam->base.reg_gen += 8;              /* least significant byte of R8-R15 */
+                pParam->Base.idxGenReg += 8;              /* least significant byte of R8-R15 */
         }
     }
@@ -1623,5 +1623,5 @@
     {
         /* FPU registers. */
-        pParam->base.reg_fp = pParam->fParam - OP_PARM_REG_FP_START;
+        pParam->Base.idxFpuReg = pParam->fParam - OP_PARM_REG_FP_START;
         pParam->fUse  |= DISUSE_REG_FP;
         pParam->cb     = 10;
@@ -1642,5 +1642,5 @@
     if (pCpu->uAddrMode == DISCPUMODE_32BIT)
     {
-        pParam->base.reg_gen = DISGREG_ESI;
+        pParam->Base.idxGenReg = DISGREG_ESI;
         pParam->fUse |= DISUSE_REG_GEN32;
     }
@@ -1648,10 +1648,10 @@
     if (pCpu->uAddrMode == DISCPUMODE_64BIT)
     {
-        pParam->base.reg_gen = DISGREG_RSI;
+        pParam->Base.idxGenReg = DISGREG_RSI;
         pParam->fUse |= DISUSE_REG_GEN64;
     }
     else
     {
-        pParam->base.reg_gen = DISGREG_SI;
+        pParam->Base.idxGenReg = DISGREG_SI;
         pParam->fUse |= DISUSE_REG_GEN16;
     }
@@ -1667,5 +1667,5 @@
     if (pCpu->uAddrMode == DISCPUMODE_32BIT)
     {
-        pParam->base.reg_gen = DISGREG_ESI;
+        pParam->Base.idxGenReg = DISGREG_ESI;
         pParam->fUse |= DISUSE_REG_GEN32;
     }
@@ -1673,10 +1673,10 @@
     if (pCpu->uAddrMode == DISCPUMODE_64BIT)
     {
-        pParam->base.reg_gen = DISGREG_RSI;
+        pParam->Base.idxGenReg = DISGREG_RSI;
         pParam->fUse |= DISUSE_REG_GEN64;
     }
     else
     {
-        pParam->base.reg_gen = DISGREG_SI;
+        pParam->Base.idxGenReg = DISGREG_SI;
         pParam->fUse |= DISUSE_REG_GEN16;
     }
@@ -1692,5 +1692,5 @@
     if (pCpu->uAddrMode == DISCPUMODE_32BIT)
     {
-        pParam->base.reg_gen = DISGREG_EDI;
+        pParam->Base.idxGenReg = DISGREG_EDI;
         pParam->fUse |= DISUSE_REG_GEN32;
     }
@@ -1698,10 +1698,10 @@
     if (pCpu->uAddrMode == DISCPUMODE_64BIT)
     {
-        pParam->base.reg_gen = DISGREG_RDI;
+        pParam->Base.idxGenReg = DISGREG_RDI;
         pParam->fUse |= DISUSE_REG_GEN64;
     }
     else
     {
-        pParam->base.reg_gen = DISGREG_DI;
+        pParam->Base.idxGenReg = DISGREG_DI;
         pParam->fUse |= DISUSE_REG_GEN16;
     }
@@ -1717,5 +1717,5 @@
     if (pCpu->uAddrMode == DISCPUMODE_32BIT)
     {
-        pParam->base.reg_gen = DISGREG_EDI;
+        pParam->Base.idxGenReg = DISGREG_EDI;
         pParam->fUse |= DISUSE_REG_GEN32;
     }
@@ -1723,10 +1723,10 @@
     if (pCpu->uAddrMode == DISCPUMODE_64BIT)
     {
-        pParam->base.reg_gen = DISGREG_RDI;
+        pParam->Base.idxGenReg = DISGREG_RDI;
         pParam->fUse |= DISUSE_REG_GEN64;
     }
     else
     {
-        pParam->base.reg_gen = DISGREG_DI;
+        pParam->Base.idxGenReg = DISGREG_DI;
         pParam->fUse |= DISUSE_REG_GEN16;
     }
@@ -2341,5 +2341,5 @@
 
         pParam->fUse |= DISUSE_REG_GEN8;
-        pParam->base.reg_gen = idx;
+        pParam->Base.idxGenReg = idx;
         break;
 
@@ -2348,5 +2348,5 @@
 
         pParam->fUse |= DISUSE_REG_GEN16;
-        pParam->base.reg_gen = idx;
+        pParam->Base.idxGenReg = idx;
         break;
 
@@ -2355,10 +2355,10 @@
 
         pParam->fUse |= DISUSE_REG_GEN32;
-        pParam->base.reg_gen = idx;
+        pParam->Base.idxGenReg = idx;
         break;
 
     case OP_PARM_q:
         pParam->fUse |= DISUSE_REG_GEN64;
-        pParam->base.reg_gen = idx;
+        pParam->Base.idxGenReg = idx;
         break;
 
@@ -2375,5 +2375,5 @@
     NOREF(pCpu); NOREF(pOp);
     pParam->fUse |= DISUSE_REG_GEN16;
-    pParam->base.reg_gen = BaseModRMReg16[idx];
+    pParam->Base.idxGenReg = BaseModRMReg16[idx];
     if (idx < 4)
     {
@@ -2395,5 +2395,5 @@
 
     pParam->fUse |= DISUSE_REG_SEG;
-    pParam->base.reg_seg = (DISSELREG)idx;
+    pParam->Base.idxSegReg = (DISSELREG)idx;
 }
 
Index: /trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp
===================================================================
--- /trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp	(revision 41743)
+++ /trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp	(revision 41744)
@@ -100,6 +100,6 @@
         case DISUSE_REG_GEN8:
         {
-            Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen8));
-            const char *psz = g_aszYasmRegGen8[pParam->base.reg_gen];
+            Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen8));
+            const char *psz = g_aszYasmRegGen8[pParam->Base.idxGenReg];
             *pcchReg = 2 + !!psz[2] + !!psz[3];
             return psz;
@@ -108,6 +108,6 @@
         case DISUSE_REG_GEN16:
         {
-            Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen16));
-            const char *psz = g_aszYasmRegGen16[pParam->base.reg_gen];
+            Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
+            const char *psz = g_aszYasmRegGen16[pParam->Base.idxGenReg];
             *pcchReg = 2 + !!psz[2] + !!psz[3];
             return psz;
@@ -116,6 +116,6 @@
         case DISUSE_REG_GEN32:
         {
-            Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen32));
-            const char *psz = g_aszYasmRegGen32[pParam->base.reg_gen];
+            Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
+            const char *psz = g_aszYasmRegGen32[pParam->Base.idxGenReg];
             *pcchReg = 2 + !!psz[2] + !!psz[3];
             return psz;
@@ -124,6 +124,6 @@
         case DISUSE_REG_GEN64:
         {
-            Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen64));
-            const char *psz = g_aszYasmRegGen64[pParam->base.reg_gen];
+            Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
+            const char *psz = g_aszYasmRegGen64[pParam->Base.idxGenReg];
             *pcchReg = 2 + !!psz[2] + !!psz[3];
             return psz;
@@ -132,6 +132,6 @@
         case DISUSE_REG_FP:
         {
-            Assert(pParam->base.reg_fp < RT_ELEMENTS(g_aszYasmRegFP));
-            const char *psz = g_aszYasmRegFP[pParam->base.reg_fp];
+            Assert(pParam->Base.idxFpuReg < RT_ELEMENTS(g_aszYasmRegFP));
+            const char *psz = g_aszYasmRegFP[pParam->Base.idxFpuReg];
             *pcchReg = 3;
             return psz;
@@ -140,6 +140,6 @@
         case DISUSE_REG_MMX:
         {
-            Assert(pParam->base.reg_mmx < RT_ELEMENTS(g_aszYasmRegMMX));
-            const char *psz = g_aszYasmRegMMX[pParam->base.reg_mmx];
+            Assert(pParam->Base.idxMmxReg < RT_ELEMENTS(g_aszYasmRegMMX));
+            const char *psz = g_aszYasmRegMMX[pParam->Base.idxMmxReg];
             *pcchReg = 3;
             return psz;
@@ -148,6 +148,6 @@
         case DISUSE_REG_XMM:
         {
-            Assert(pParam->base.reg_xmm < RT_ELEMENTS(g_aszYasmRegXMM));
-            const char *psz = g_aszYasmRegXMM[pParam->base.reg_mmx];
+            Assert(pParam->Base.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
+            const char *psz = g_aszYasmRegXMM[pParam->Base.idxMmxReg];
             *pcchReg = 4 + !!psz[4];
             return psz;
@@ -156,6 +156,6 @@
         case DISUSE_REG_CR:
         {
-            Assert(pParam->base.reg_ctrl < RT_ELEMENTS(g_aszYasmRegCRx));
-            const char *psz = g_aszYasmRegCRx[pParam->base.reg_ctrl];
+            Assert(pParam->Base.idxCtrlReg < RT_ELEMENTS(g_aszYasmRegCRx));
+            const char *psz = g_aszYasmRegCRx[pParam->Base.idxCtrlReg];
             *pcchReg = 3;
             return psz;
@@ -164,6 +164,6 @@
         case DISUSE_REG_DBG:
         {
-            Assert(pParam->base.reg_dbg < RT_ELEMENTS(g_aszYasmRegDRx));
-            const char *psz = g_aszYasmRegDRx[pParam->base.reg_dbg];
+            Assert(pParam->Base.idxDbgReg < RT_ELEMENTS(g_aszYasmRegDRx));
+            const char *psz = g_aszYasmRegDRx[pParam->Base.idxDbgReg];
             *pcchReg = 3;
             return psz;
@@ -172,6 +172,6 @@
         case DISUSE_REG_SEG:
         {
-            Assert(pParam->base.reg_seg < RT_ELEMENTS(g_aszYasmRegCRx));
-            const char *psz = g_aszYasmRegSeg[pParam->base.reg_seg];
+            Assert(pParam->Base.idxSegReg < RT_ELEMENTS(g_aszYasmRegCRx));
+            const char *psz = g_aszYasmRegSeg[pParam->Base.idxSegReg];
             *pcchReg = 2;
             return psz;
@@ -180,6 +180,6 @@
         case DISUSE_REG_TEST:
         {
-            Assert(pParam->base.reg_test < RT_ELEMENTS(g_aszYasmRegTRx));
-            const char *psz = g_aszYasmRegTRx[pParam->base.reg_test];
+            Assert(pParam->Base.idxTestReg < RT_ELEMENTS(g_aszYasmRegTRx));
+            const char *psz = g_aszYasmRegTRx[pParam->Base.idxTestReg];
             *pcchReg = 3;
             return psz;
Index: /trunk/src/VBox/Disassembler/DisasmReg.cpp
===================================================================
--- /trunk/src/VBox/Disassembler/DisasmReg.cpp	(revision 41743)
+++ /trunk/src/VBox/Disassembler/DisasmReg.cpp	(revision 41744)
@@ -270,5 +270,5 @@
         AssertCompile(DISGREG_ESP == DISGREG_SP);
         AssertCompile(DISGREG_EBP == DISGREG_BP);
-        if (pParam->base.reg_gen == DISGREG_ESP || pParam->base.reg_gen == DISGREG_EBP)
+        if (pParam->Base.idxGenReg == DISGREG_ESP || pParam->Base.idxGenReg == DISGREG_EBP)
             return DISSELREG_SS;
     }
@@ -515,5 +515,5 @@
             {
                 pParamVal->flags |= DISQPV_FLAG_8;
-                if (RT_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
+                if (RT_FAILURE(DISFetchReg8(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
             }
             else
@@ -521,5 +521,5 @@
             {
                 pParamVal->flags |= DISQPV_FLAG_16;
-                if (RT_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
+                if (RT_FAILURE(DISFetchReg16(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
             }
             else
@@ -527,5 +527,5 @@
             {
                 pParamVal->flags |= DISQPV_FLAG_32;
-                if (RT_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
+                if (RT_FAILURE(DISFetchReg32(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
             }
             else
@@ -533,5 +533,5 @@
             {
                 pParamVal->flags |= DISQPV_FLAG_64;
-                if (RT_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
+                if (RT_FAILURE(DISFetchReg64(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
             }
             else
@@ -647,5 +647,5 @@
             pParamVal->flags |= DISQPV_FLAG_8;
             pParamVal->size   = sizeof(uint8_t);
-            if (RT_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
+            if (RT_FAILURE(DISFetchReg8(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
         }
         else
@@ -654,5 +654,5 @@
             pParamVal->flags |= DISQPV_FLAG_16;
             pParamVal->size   = sizeof(uint16_t);
-            if (RT_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
+            if (RT_FAILURE(DISFetchReg16(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
         }
         else
@@ -661,5 +661,5 @@
             pParamVal->flags |= DISQPV_FLAG_32;
             pParamVal->size   = sizeof(uint32_t);
-            if (RT_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
+            if (RT_FAILURE(DISFetchReg32(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
         }
         else
@@ -668,5 +668,5 @@
             pParamVal->flags |= DISQPV_FLAG_64;
             pParamVal->size   = sizeof(uint64_t);
-            if (RT_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
+            if (RT_FAILURE(DISFetchReg64(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
         }
         else
@@ -767,5 +767,5 @@
         {
             uint8_t *pu8Reg;
-            if (RT_SUCCESS(DISPtrReg8(pCtx, pParam->base.reg_gen, &pu8Reg)))
+            if (RT_SUCCESS(DISPtrReg8(pCtx, pParam->Base.idxGenReg, &pu8Reg)))
             {
                 *pcbSize = sizeof(uint8_t);
@@ -778,5 +778,5 @@
         {
             uint16_t *pu16Reg;
-            if (RT_SUCCESS(DISPtrReg16(pCtx, pParam->base.reg_gen, &pu16Reg)))
+            if (RT_SUCCESS(DISPtrReg16(pCtx, pParam->Base.idxGenReg, &pu16Reg)))
             {
                 *pcbSize = sizeof(uint16_t);
@@ -789,5 +789,5 @@
         {
             uint32_t *pu32Reg;
-            if (RT_SUCCESS(DISPtrReg32(pCtx, pParam->base.reg_gen, &pu32Reg)))
+            if (RT_SUCCESS(DISPtrReg32(pCtx, pParam->Base.idxGenReg, &pu32Reg)))
             {
                 *pcbSize = sizeof(uint32_t);
@@ -800,5 +800,5 @@
         {
             uint64_t *pu64Reg;
-            if (RT_SUCCESS(DISPtrReg64(pCtx, pParam->base.reg_gen, &pu64Reg)))
+            if (RT_SUCCESS(DISPtrReg64(pCtx, pParam->Base.idxGenReg, &pu64Reg)))
             {
                 *pcbSize = sizeof(uint64_t);
Index: /trunk/src/VBox/VMM/VMMAll/EMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/EMAll.cpp	(revision 41743)
+++ /trunk/src/VBox/VMM/VMMAll/EMAll.cpp	(revision 41744)
@@ -879,8 +879,8 @@
                 {
                 case 1: //special case for AH etc
-                        rc = DISWriteReg8(pRegFrame, pDis->Param1.base.reg_gen,  (uint8_t )valpar2); break;
-                case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.base.reg_gen, (uint16_t)valpar2); break;
-                case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.base.reg_gen, (uint32_t)valpar2); break;
-                case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.base.reg_gen, valpar2); break;
+                        rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg,  (uint8_t )valpar2); break;
+                case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)valpar2); break;
+                case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)valpar2); break;
+                case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, valpar2); break;
                 default: AssertFailedReturn(VERR_EM_INTERPRETER);
                 }
@@ -905,8 +905,8 @@
                 {
                 case 1: //special case for AH etc
-                        rc = DISWriteReg8(pRegFrame, pDis->Param2.base.reg_gen,  (uint8_t )valpar1);    break;
-                case 2: rc = DISWriteReg16(pRegFrame, pDis->Param2.base.reg_gen, (uint16_t)valpar1);    break;
-                case 4: rc = DISWriteReg32(pRegFrame, pDis->Param2.base.reg_gen, (uint32_t)valpar1);    break;
-                case 8: rc = DISWriteReg64(pRegFrame, pDis->Param2.base.reg_gen, valpar1);              break;
+                        rc = DISWriteReg8(pRegFrame, pDis->Param2.Base.idxGenReg,  (uint8_t )valpar1);    break;
+                case 2: rc = DISWriteReg16(pRegFrame, pDis->Param2.Base.idxGenReg, (uint16_t)valpar1);    break;
+                case 4: rc = DISWriteReg32(pRegFrame, pDis->Param2.Base.idxGenReg, (uint32_t)valpar1);    break;
+                case 8: rc = DISWriteReg64(pRegFrame, pDis->Param2.Base.idxGenReg, valpar1);              break;
                 default: AssertFailedReturn(VERR_EM_INTERPRETER);
                 }
@@ -1051,5 +1051,5 @@
                 if (    (pDis->Param1.fUse & DISUSE_BASE)
                     &&  (pDis->Param1.fUse & (DISUSE_REG_GEN16|DISUSE_REG_GEN32))
-                    &&  pDis->Param1.base.reg_gen == DISGREG_ESP
+                    &&  pDis->Param1.Base.idxGenReg == DISGREG_ESP
                    )
                    pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
@@ -1609,8 +1609,8 @@
                 switch(param1.size)
                 {
-                case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.base.reg_gen,  (uint8_t) val64); break;
-                case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.base.reg_gen, (uint16_t)val64); break;
-                case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.base.reg_gen, (uint32_t)val64); break;
-                case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.base.reg_gen, val64); break;
+                case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg,  (uint8_t) val64); break;
+                case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)val64); break;
+                case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)val64); break;
+                case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, val64); break;
                 default:
                     return VERR_EM_INTERPRETER;
@@ -2428,6 +2428,6 @@
         if(param1.size != sizeof(uint16_t))
             return VERR_EM_INTERPRETER;
-        LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDis->Param1.base.reg_gen, cr0));
-        rc = DISWriteReg16(pRegFrame, pDis->Param1.base.reg_gen, cr0);
+        LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDis->Param1.Base.idxGenReg, cr0));
+        rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, cr0);
         break;
 
@@ -2469,8 +2469,8 @@
     NOREF(pvFault); NOREF(pcbSize);
     if ((pDis->Param1.fUse == DISUSE_REG_GEN32 || pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_CR)
-        return EMInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.base.reg_gen, pDis->Param2.base.reg_ctrl);
+        return EMInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxCtrlReg);
 
     if (pDis->Param1.fUse == DISUSE_REG_CR && (pDis->Param2.fUse == DISUSE_REG_GEN32 || pDis->Param2.fUse == DISUSE_REG_GEN64))
-        return EMInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.base.reg_ctrl, pDis->Param2.base.reg_gen);
+        return EMInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxCtrlReg, pDis->Param2.Base.idxGenReg);
 
     AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
@@ -2560,10 +2560,10 @@
     if((pDis->Param1.fUse == DISUSE_REG_GEN32 || pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_DBG)
     {
-        rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.base.reg_gen, pDis->Param2.base.reg_dbg);
+        rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxDbgReg);
     }
     else
     if(pDis->Param1.fUse == DISUSE_REG_DBG && (pDis->Param2.fUse == DISUSE_REG_GEN32 || pDis->Param2.fUse == DISUSE_REG_GEN64))
     {
-        rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.base.reg_dbg, pDis->Param2.base.reg_gen);
+        rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxDbgReg, pDis->Param2.Base.idxGenReg);
     }
     else
Index: /trunk/src/VBox/VMM/VMMAll/IOMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IOMAll.cpp	(revision 41743)
+++ /trunk/src/VBox/VMM/VMMAll/IOMAll.cpp	(revision 41744)
@@ -81,5 +81,5 @@
         {
             *pcbSize  = 4;
-            DISFetchReg32(pRegFrame, pParam->base.reg_gen, (uint32_t *)pu64Data);
+            DISFetchReg32(pRegFrame, pParam->Base.idxGenReg, (uint32_t *)pu64Data);
             return true;
         }
@@ -88,5 +88,5 @@
         {
             *pcbSize  = 2;
-            DISFetchReg16(pRegFrame, pParam->base.reg_gen, (uint16_t *)pu64Data);
+            DISFetchReg16(pRegFrame, pParam->Base.idxGenReg, (uint16_t *)pu64Data);
             return true;
         }
@@ -95,5 +95,5 @@
         {
             *pcbSize  = 1;
-            DISFetchReg8(pRegFrame, pParam->base.reg_gen, (uint8_t *)pu64Data);
+            DISFetchReg8(pRegFrame, pParam->Base.idxGenReg, (uint8_t *)pu64Data);
             return true;
         }
@@ -101,5 +101,5 @@
         Assert(pParam->fUse & DISUSE_REG_GEN64);
         *pcbSize  = 8;
-        DISFetchReg64(pRegFrame, pParam->base.reg_gen, pu64Data);
+        DISFetchReg64(pRegFrame, pParam->Base.idxGenReg, pu64Data);
         return true;
     }
@@ -137,5 +137,5 @@
         {
             *pcbSize  = 2;
-            DISFetchRegSeg(pRegFrame, (DISSELREG)pParam->base.reg_seg, (RTSEL *)pu64Data);
+            DISFetchRegSeg(pRegFrame, (DISSELREG)pParam->Base.idxSegReg, (RTSEL *)pu64Data);
             return true;
         } /* Else - error. */
@@ -169,5 +169,5 @@
     if (pParam->fUse & DISUSE_REG_GEN32)
     {
-        DISWriteReg32(pRegFrame, pParam->base.reg_gen, (uint32_t)u64Data);
+        DISWriteReg32(pRegFrame, pParam->Base.idxGenReg, (uint32_t)u64Data);
         return true;
     }
@@ -175,5 +175,5 @@
     if (pParam->fUse & DISUSE_REG_GEN64)
     {
-        DISWriteReg64(pRegFrame, pParam->base.reg_gen, u64Data);
+        DISWriteReg64(pRegFrame, pParam->Base.idxGenReg, u64Data);
         return true;
     }
@@ -181,5 +181,5 @@
     if (pParam->fUse & DISUSE_REG_GEN16)
     {
-        DISWriteReg16(pRegFrame, pParam->base.reg_gen, (uint16_t)u64Data);
+        DISWriteReg16(pRegFrame, pParam->Base.idxGenReg, (uint16_t)u64Data);
         return true;
     }
@@ -187,5 +187,5 @@
     if (pParam->fUse & DISUSE_REG_GEN8)
     {
-        DISWriteReg8(pRegFrame, pParam->base.reg_gen, (uint8_t)u64Data);
+        DISWriteReg8(pRegFrame, pParam->Base.idxGenReg, (uint8_t)u64Data);
         return true;
     }
@@ -193,5 +193,5 @@
     if (pParam->fUse & DISUSE_REG_SEG)
     {
-        DISWriteRegSeg(pRegFrame, (DISSELREG)pParam->base.reg_seg, (RTSEL)u64Data);
+        DISWriteRegSeg(pRegFrame, (DISSELREG)pParam->Base.idxSegReg, (RTSEL)u64Data);
         return true;
     }
Index: /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp	(revision 41743)
+++ /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp	(revision 41744)
@@ -761,5 +761,5 @@
 #endif
 
-    LogFlow(("Reused instr %RGv %d at %RGv param1.fUse=%llx param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->uOpcode, pvFault, pDis->Param1.fUse,  pDis->Param1.base.reg_gen));
+    LogFlow(("Reused instr %RGv %d at %RGv param1.fUse=%llx param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->uOpcode, pvFault, pDis->Param1.fUse,  pDis->Param1.Base.idxGenReg));
 
     /* Non-supervisor mode write means it's used for something else. */
@@ -806,5 +806,5 @@
     if (    (    (pDis->Param1.fUse & DISUSE_REG_GEN32)
              ||  (pDis->Param1.fUse & DISUSE_REG_GEN64))
-        &&  (pDis->Param1.base.reg_gen == DISGREG_ESP))
+        &&  (pDis->Param1.Base.idxGenReg == DISGREG_ESP))
     {
         Log4(("pgmPoolMonitorIsReused: ESP\n"));
Index: /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp	(revision 41743)
+++ /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp	(revision 41744)
@@ -994,6 +994,6 @@
                     //read
                     Assert(Cpu.Param2.fUse & DISUSE_REG_CR);
-                    Assert(Cpu.Param2.base.reg_ctrl <= DISCREG_CR4);
-                    STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.Param2.base.reg_ctrl]);
+                    Assert(Cpu.Param2.Base.idxCtrlReg <= DISCREG_CR4);
+                    STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.Param2.Base.idxCtrlReg]);
                 }
                 else
@@ -1001,6 +1001,6 @@
                     //write
                     Assert(Cpu.Param1.fUse & DISUSE_REG_CR);
-                    Assert(Cpu.Param1.base.reg_ctrl <= DISCREG_CR4);
-                    STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.Param1.base.reg_ctrl]);
+                    Assert(Cpu.Param1.Base.idxCtrlReg <= DISCREG_CR4);
+                    STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.Param1.Base.idxCtrlReg]);
                 }
                 break;
Index: /trunk/src/VBox/VMM/VMMR3/HWACCM.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/HWACCM.cpp	(revision 41743)
+++ /trunk/src/VBox/VMM/VMMR3/HWACCM.cpp	(revision 41744)
@@ -1839,5 +1839,5 @@
             {
                 pPatch->enmType     = HWACCMTPRINSTR_WRITE_REG;
-                pPatch->uSrcOperand = pDis->Param2.base.reg_gen;
+                pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
             }
             else
@@ -1857,5 +1857,5 @@
             RTGCPTR  oldrip   = pCtx->rip;
             uint32_t oldcbOp  = cbOp;
-            uint32_t uMmioReg = pDis->Param1.base.reg_gen;
+            uint32_t uMmioReg = pDis->Param1.Base.idxGenReg;
 
             /* read */
@@ -1873,5 +1873,5 @@
                 &&  pDis->pCurInstr->uOpcode == OP_SHR
                 &&  pDis->Param1.fUse == DISUSE_REG_GEN32
-                &&  pDis->Param1.base.reg_gen == uMmioReg
+                &&  pDis->Param1.Base.idxGenReg == uMmioReg
                 &&  pDis->Param2.fUse == DISUSE_IMMEDIATE8
                 &&  pDis->Param2.uValue == 4
@@ -1890,5 +1890,5 @@
                 szInstr[1] = 0x0F;
                 szInstr[2] = 0x20;
-                szInstr[3] = 0xC0 | pDis->Param1.base.reg_gen;
+                szInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
                 for (unsigned i = 4; i < pPatch->cbOp; i++)
                     szInstr[i] = 0x90;  /* nop */
@@ -1906,5 +1906,5 @@
             {
                 pPatch->enmType     = HWACCMTPRINSTR_READ;
-                pPatch->uDstOperand = pDis->Param1.base.reg_gen;
+                pPatch->uDstOperand = pDis->Param1.Base.idxGenReg;
 
                 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
@@ -2028,5 +2028,5 @@
                 *
                 */
-            bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.base.reg_gen == DISGREG_EAX);
+            bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
 
             aPatch[off++] = 0x51;    /* push ecx */
@@ -2041,5 +2041,5 @@
                 {
                     aPatch[off++] = 0x89;    /* mov eax, src_reg */
-                    aPatch[off++] = MAKE_MODRM(3, pDis->Param2.base.reg_gen, DISGREG_EAX);
+                    aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
                 }
             }
@@ -2081,9 +2081,9 @@
             Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
 
-            if (pDis->Param1.base.reg_gen != DISGREG_ECX)
+            if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
                 aPatch[off++] = 0x51;    /* push ecx */
-            if (pDis->Param1.base.reg_gen != DISGREG_EDX )
+            if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
                 aPatch[off++] = 0x52;    /* push edx */
-            if (pDis->Param1.base.reg_gen != DISGREG_EAX)
+            if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
                 aPatch[off++] = 0x50;    /* push eax */
 
@@ -2098,15 +2098,15 @@
             aPatch[off++] = 0x32;
 
-            if (pDis->Param1.base.reg_gen != DISGREG_EAX)
+            if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
             {
                 aPatch[off++] = 0x89;    /* mov dst_reg, eax */
-                aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.base.reg_gen);
+                aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
             }
 
-            if (pDis->Param1.base.reg_gen != DISGREG_EAX)
+            if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
                 aPatch[off++] = 0x58;    /* pop eax */
-            if (pDis->Param1.base.reg_gen != DISGREG_EDX )
+            if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
                 aPatch[off++] = 0x5A;    /* pop edx */
-            if (pDis->Param1.base.reg_gen != DISGREG_ECX)
+            if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
                 aPatch[off++] = 0x59;    /* pop ecx */
         }
Index: /trunk/src/VBox/VMM/VMMR3/PATM.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/PATM.cpp	(revision 41743)
+++ /trunk/src/VBox/VMM/VMMR3/PATM.cpp	(revision 41744)
@@ -1749,5 +1749,5 @@
             /* mov ss, src? */
             if (    (pCpu->Param1.fUse & DISUSE_REG_SEG)
-                &&  (pCpu->Param1.base.reg_seg == DISSELREG_SS))
+                &&  (pCpu->Param1.Base.idxSegReg == DISSELREG_SS))
             {
                 Log(("Force recompilation of next instruction for OP_MOV at %RRv\n", pCurInstrGC));
@@ -1758,5 +1758,5 @@
             else
             if (    (pCpu->Param2.fUse & DISUSE_REG_SEG)
-                &&  (pCpu->Param2.base.reg_seg == USE_REG_SS)
+                &&  (pCpu->Param2.Base.idxSegReg == USE_REG_SS)
                 &&  (pCpu->Param1.fUse & (DISUSE_REG_GEN32|DISUSE_REG_GEN16)))     /** @todo memory operand must in theory be handled too */
             {
Index: /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp	(revision 41743)
+++ /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp	(revision 41744)
@@ -1167,6 +1167,6 @@
         Assert(pCpu->Param2.fUse & DISUSE_REG_GEN32);
 
-        dbgreg = pCpu->Param1.base.reg_dbg;
-        reg    = pCpu->Param2.base.reg_gen;
+        dbgreg = pCpu->Param1.Base.idxDbgReg;
+        reg    = pCpu->Param2.Base.idxGenReg;
     }
     else
@@ -1177,6 +1177,6 @@
 
         pPB[0] = 0x8B;      // mov GPR, disp32
-        reg    = pCpu->Param1.base.reg_gen;
-        dbgreg = pCpu->Param2.base.reg_dbg;
+        reg    = pCpu->Param1.Base.idxGenReg;
+        dbgreg = pCpu->Param2.Base.idxDbgReg;
     }
 
@@ -1214,6 +1214,6 @@
         // mov CRx, GPR
         pPB[0] = 0x89;      //mov disp32, GPR
-        ctrlreg = pCpu->Param1.base.reg_ctrl;
-        reg     = pCpu->Param2.base.reg_gen;
+        ctrlreg = pCpu->Param1.Base.idxCtrlReg;
+        reg     = pCpu->Param2.Base.idxGenReg;
         Assert(pCpu->Param1.fUse & DISUSE_REG_CR);
         Assert(pCpu->Param2.fUse & DISUSE_REG_GEN32);
@@ -1226,6 +1226,6 @@
 
         pPB[0]  = 0x8B;      // mov GPR, disp32
-        reg     = pCpu->Param1.base.reg_gen;
-        ctrlreg = pCpu->Param2.base.reg_ctrl;
+        reg     = pCpu->Param1.Base.idxGenReg;
+        ctrlreg = pCpu->Param2.Base.idxCtrlReg;
     }
 
@@ -1292,5 +1292,5 @@
     if (pCpu->fPrefix & DISPREFIX_OPSIZE)
         pPB[offset++] = 0x66; /* size override -> 16 bits pop */
-    pPB[offset++] = 0x58 + pCpu->Param1.base.reg_gen;
+    pPB[offset++] = 0x58 + pCpu->Param1.Base.idxGenReg;
     PATCHGEN_EPILOG(pPatch, offset);
 
@@ -1335,5 +1335,5 @@
         pPB[offset++] = 0x8B;              // mov       destreg, CPUMCTX.tr/ldtr
         /* Modify REG part according to destination of original instruction */
-        pPB[offset++] = MAKE_MODRM(0, pCpu->Param1.base.reg_gen, 5);
+        pPB[offset++] = MAKE_MODRM(0, pCpu->Param1.Base.idxGenReg, 5);
         if (pCpu->pCurInstr->uOpcode == OP_STR)
         {