Index: /trunk/include/VBox/dis.h
===================================================================
--- /trunk/include/VBox/dis.h	(revision 41737)
+++ /trunk/include/VBox/dis.h	(revision 41738)
@@ -91,5 +91,5 @@
 /** @} */
 
-/** @name Operand type.
+/** @name Operand type (DISOPCODE::fOpType).
  * @{
  */
@@ -449,15 +449,23 @@
     const char  *pszOpcode;
 #endif
+    /** Parameter \#1 parser index. */
     uint8_t     idxParse1;
+    /** Parameter \#2 parser index. */
     uint8_t     idxParse2;
+    /** Parameter \#3 parser index. */
     uint8_t     idxParse3;
+    /** Unused padding.  */
     uint8_t     uUnused;
     /** The opcode identifier. This DIS specific, @see grp_dis_opcodes and
      * VBox/disopcode.h. */
     uint16_t    uOpcode;
-    uint16_t    param1;
-    uint16_t    param2;
-    uint16_t    param3;
-    uint32_t    optype;
+    /** Parameter \#1 info, @see grp_dis_opparam. */
+    uint16_t    fParam1;
+    /** Parameter \#2 info, @see grp_dis_opparam. */
+    uint16_t    fParam2;
+    /** Parameter \#3 info, @see grp_dis_opparam. */
+    uint16_t    fParam3;
+    /** Operand type flags, DISOPTYPE_XXX. */
+    uint32_t    fOpType;
 } DISOPCODE;
 /** Pointer to const opcode. */
Index: /trunk/include/VBox/disopcode.h
===================================================================
--- /trunk/include/VBox/disopcode.h	(revision 41737)
+++ /trunk/include/VBox/disopcode.h	(revision 41738)
@@ -629,7 +629,10 @@
 
 
-/** @name Opcode parameters
+/** @defgroup grp_dis_opparam Opcode parameters (DISOPCODE::fParam1,
+ *            DISOPCODE::fParam2, DISOPCODE::fParam3)
+ * @ingroup grp_dis
  * @{
  */
+
 /* NOTE: Register order is important for translations!! */
 #define OP_PARM_NONE            0
Index: /trunk/src/VBox/Disassembler/DisasmCore.cpp
===================================================================
--- /trunk/src/VBox/Disassembler/DisasmCore.cpp	(revision 41737)
+++ /trunk/src/VBox/Disassembler/DisasmCore.cpp	(revision 41738)
@@ -358,5 +358,5 @@
             // segment override prefix byte
             case OP_SEG:
-                pCpu->idxSegPrefix = (DISSELREG)(paOneByteMap[codebyte].param1 - OP_PARM_REG_SEG_START);
+                pCpu->idxSegPrefix = (DISSELREG)(paOneByteMap[codebyte].fParam1 - OP_PARM_REG_SEG_START);
                 /* Segment prefixes for CS, DS, ES and SS are ignored in long mode. */
                 if (   pCpu->uCpuMode != DISCPUMODE_64BIT
@@ -414,5 +414,5 @@
                 /* REX prefix byte */
                 pCpu->fPrefix   |= DISPREFIX_REX;
-                pCpu->fRexPrefix = DISPREFIX_REX_OP_2_FLAGS(paOneByteMap[codebyte].param1);
+                pCpu->fRexPrefix = DISPREFIX_REX_OP_2_FLAGS(paOneByteMap[codebyte].fParam1);
                 iByte           += sizeof(uint8_t);
 
@@ -459,5 +459,5 @@
      * Note! Multibyte opcodes are always marked harmless until the final byte.
      */
-    if ((pOp->optype & pCpu->fFilter) == 0)
+    if ((pOp->fOpType & pCpu->fFilter) == 0)
     {
         fFiltered = true;
@@ -471,20 +471,20 @@
 
     // Should contain the parameter type on input
-    pCpu->param1.param = pOp->param1;
-    pCpu->param2.param = pOp->param2;
-    pCpu->param3.param = pOp->param3;
+    pCpu->param1.param = pOp->fParam1;
+    pCpu->param2.param = pOp->fParam2;
+    pCpu->param3.param = pOp->fParam3;
 
     /* Correct the operand size if the instruction is marked as forced or default 64 bits */
     if (pCpu->uCpuMode == DISCPUMODE_64BIT)
     {
-        if (pOp->optype & DISOPTYPE_FORCED_64_OP_SIZE)
+        if (pOp->fOpType & DISOPTYPE_FORCED_64_OP_SIZE)
             pCpu->uOpMode = DISCPUMODE_64BIT;
         else
-        if (    (pOp->optype & DISOPTYPE_DEFAULT_64_OP_SIZE)
+        if (    (pOp->fOpType & DISOPTYPE_DEFAULT_64_OP_SIZE)
             &&  !(pCpu->fPrefix & DISPREFIX_OPSIZE))
             pCpu->uOpMode = DISCPUMODE_64BIT;
     }
     else
-    if (pOp->optype & DISOPTYPE_FORCED_32_OP_SIZE_X86)
+    if (pOp->fOpType & DISOPTYPE_FORCED_32_OP_SIZE_X86)
     {
         /* Forced 32 bits operand size for certain instructions (mov crx, mov drx). */
@@ -534,6 +534,6 @@
 
         // Should contain the parameter type on input
-        pCpu->param1.param = fpop->param1;
-        pCpu->param2.param = fpop->param2;
+        pCpu->param1.param = fpop->fParam1;
+        pCpu->param2.param = fpop->fParam2;
     }
     else
@@ -547,5 +547,5 @@
      * @note Multibyte opcodes are always marked harmless until the final byte.
      */
-    if ((fpop->optype & pCpu->fFilter) == 0)
+    if ((fpop->fOpType & pCpu->fFilter) == 0)
         pCpu->pfnDisasmFnTable = g_apfnCalcSize;
     else
@@ -557,8 +557,8 @@
     {
         /* Note: redundant, but just in case this ever changes */
-        if (fpop->optype & DISOPTYPE_FORCED_64_OP_SIZE)
+        if (fpop->fOpType & DISOPTYPE_FORCED_64_OP_SIZE)
             pCpu->uOpMode = DISCPUMODE_64BIT;
         else
-        if (    (fpop->optype & DISOPTYPE_DEFAULT_64_OP_SIZE)
+        if (    (fpop->fOpType & DISOPTYPE_DEFAULT_64_OP_SIZE)
             &&  !(pCpu->fPrefix & DISPREFIX_OPSIZE))
             pCpu->uOpMode = DISCPUMODE_64BIT;
@@ -1077,5 +1077,5 @@
      * encoding of the MOD field in the MODR/M byte.
      */
-    if (pOp->optype & DISOPTYPE_MOD_FIXED_11)
+    if (pOp->fOpType & DISOPTYPE_MOD_FIXED_11)
         pCpu->ModRM.Bits.Mod = 3;
 
@@ -1123,5 +1123,5 @@
      * encoding of the MOD field in the MODR/M byte.
      */
-    if (pOp->optype & DISOPTYPE_MOD_FIXED_11)
+    if (pOp->fOpType & DISOPTYPE_MOD_FIXED_11)
         pCpu->ModRM.Bits.Mod = 3;
 
@@ -1568,5 +1568,5 @@
             /* Use 64-bit registers. */
             pParam->base.reg_gen = pParam->param - OP_PARM_REG_GEN32_START;
-            if (    (pOp->optype & DISOPTYPE_REXB_EXTENDS_OPREG)
+            if (    (pOp->fOpType & DISOPTYPE_REXB_EXTENDS_OPREG)
                 &&  pParam == &pCpu->param1             /* ugly assumption that it only applies to the first parameter */
                 &&  (pCpu->fPrefix & DISPREFIX_REX)
@@ -1612,5 +1612,5 @@
         if (pCpu->uOpMode == DISCPUMODE_64BIT)
         {
-            if (    (pOp->optype & DISOPTYPE_REXB_EXTENDS_OPREG)
+            if (    (pOp->fOpType & DISOPTYPE_REXB_EXTENDS_OPREG)
                 &&  pParam == &pCpu->param1             /* ugly assumption that it only applies to the first parameter */
                 &&  (pCpu->fPrefix & DISPREFIX_REX)
Index: /trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp
===================================================================
--- /trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp	(revision 41737)
+++ /trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp	(revision 41738)
@@ -675,6 +675,6 @@
                             if (    pParam->param != OP_PARM_Ev
                                 ||  pOp->uOpcode != OP_MOV
-                                ||  (   pOp->param1 != OP_PARM_Sw
-                                     && pOp->param2 != OP_PARM_Sw))
+                                ||  (   pOp->fParam1 != OP_PARM_Sw
+                                     && pOp->fParam2 != OP_PARM_Sw))
                                 PUT_SIZE_OVERRIDE();
                             PUT_C('[');
@@ -792,6 +792,6 @@
                             case DISUSE_IMMEDIATE8:
                                 if (    (fFlags & DIS_FMT_FLAGS_STRICT)
-                                    &&  (   (pOp->param1 >= OP_PARM_REG_GEN8_START && pOp->param1 <= OP_PARM_REG_GEN8_END)
-                                         || (pOp->param2 >= OP_PARM_REG_GEN8_START && pOp->param2 <= OP_PARM_REG_GEN8_END))
+                                    &&  (   (pOp->fParam1 >= OP_PARM_REG_GEN8_START && pOp->fParam1 <= OP_PARM_REG_GEN8_END)
+                                         || (pOp->fParam2 >= OP_PARM_REG_GEN8_START && pOp->fParam2 <= OP_PARM_REG_GEN8_END))
                                    )
                                     PUT_SZ("strict byte ");
@@ -803,6 +803,6 @@
                                     ||  (   (fFlags & DIS_FMT_FLAGS_STRICT)
                                          && (   (int8_t)pParam->parval == (int16_t)pParam->parval
-                                             || (pOp->param1 >= OP_PARM_REG_GEN16_START && pOp->param1 <= OP_PARM_REG_GEN16_END)
-                                             || (pOp->param2 >= OP_PARM_REG_GEN16_START && pOp->param2 <= OP_PARM_REG_GEN16_END))
+                                             || (pOp->fParam1 >= OP_PARM_REG_GEN16_START && pOp->fParam1 <= OP_PARM_REG_GEN16_END)
+                                             || (pOp->fParam2 >= OP_PARM_REG_GEN16_START && pOp->fParam2 <= OP_PARM_REG_GEN16_END))
                                         )
                                    )
@@ -826,6 +826,6 @@
                                     ||  (   (fFlags & DIS_FMT_FLAGS_STRICT)
                                          && (   (int8_t)pParam->parval == (int32_t)pParam->parval
-                                             || (pOp->param1 >= OP_PARM_REG_GEN32_START && pOp->param1 <= OP_PARM_REG_GEN32_END)
-                                             || (pOp->param2 >= OP_PARM_REG_GEN32_START && pOp->param2 <= OP_PARM_REG_GEN32_END))
+                                             || (pOp->fParam1 >= OP_PARM_REG_GEN32_START && pOp->fParam1 <= OP_PARM_REG_GEN32_END)
+                                             || (pOp->fParam2 >= OP_PARM_REG_GEN32_START && pOp->fParam2 <= OP_PARM_REG_GEN32_END))
                                         )
                                     )
@@ -1302,8 +1302,8 @@
     {
         Assert(pCpu->fPrefix & DISPREFIX_ADDRSIZE);
-        if (    pCpu->pCurInstr->param3 == OP_PARM_NONE
-            &&  pCpu->pCurInstr->param2 == OP_PARM_NONE
-            &&  (   pCpu->pCurInstr->param1 >= OP_PARM_REG_GEN32_START
-                 && pCpu->pCurInstr->param1 <= OP_PARM_REG_GEN32_END))
+        if (    pCpu->pCurInstr->fParam3 == OP_PARM_NONE
+            &&  pCpu->pCurInstr->fParam2 == OP_PARM_NONE
+            &&  (   pCpu->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
+                 && pCpu->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END))
             return true;
     }
@@ -1319,6 +1319,6 @@
 
             case OP_JMP:
-                if (    pCpu->pCurInstr->param1 != OP_PARM_Jb
-                    &&  pCpu->pCurInstr->param1 != OP_PARM_Jv)
+                if (    pCpu->pCurInstr->fParam1 != OP_PARM_Jb
+                    &&  pCpu->pCurInstr->fParam1 != OP_PARM_Jv)
                     break;
                 /* fall thru */
@@ -1352,10 +1352,10 @@
             case OP_POP:
             case OP_PUSH:
-                if (    pCpu->pCurInstr->param1 >= OP_PARM_REG_SEG_START
-                    &&  pCpu->pCurInstr->param1 <= OP_PARM_REG_SEG_END)
+                if (    pCpu->pCurInstr->fParam1 >= OP_PARM_REG_SEG_START
+                    &&  pCpu->pCurInstr->fParam1 <= OP_PARM_REG_SEG_END)
                     return true;
                 if (    (fPrefixes & ~DISPREFIX_OPSIZE)
-                    &&  pCpu->pCurInstr->param1 >= OP_PARM_REG_GEN32_START
-                    &&  pCpu->pCurInstr->param1 <= OP_PARM_REG_GEN32_END)
+                    &&  pCpu->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
+                    &&  pCpu->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END)
                     return true;
                 break;
@@ -1373,8 +1373,8 @@
     /* Implicit 8-bit register instructions doesn't mix with operand size. */
     if (    (fPrefixes & DISPREFIX_OPSIZE)
-        &&  (   (   pCpu->pCurInstr->param1 == OP_PARM_Gb /* r8 */
-                 && pCpu->pCurInstr->param2 == OP_PARM_Eb /* r8/mem8 */)
-             || (   pCpu->pCurInstr->param2 == OP_PARM_Gb /* r8 */
-                 && pCpu->pCurInstr->param1 == OP_PARM_Eb /* r8/mem8 */))
+        &&  (   (   pCpu->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
+                 && pCpu->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
+             || (   pCpu->pCurInstr->fParam2 == OP_PARM_Gb /* r8 */
+                 && pCpu->pCurInstr->fParam1 == OP_PARM_Eb /* r8/mem8 */))
        )
     {
@@ -1415,8 +1415,8 @@
             case OP_XOR:
             case OP_CMP:
-                if (    (    pCpu->pCurInstr->param1 == OP_PARM_Gb /* r8 */
-                         && pCpu->pCurInstr->param2 == OP_PARM_Eb /* r8/mem8 */)
-                    ||  (    pCpu->pCurInstr->param1 == OP_PARM_Gv /* rX */
-                         && pCpu->pCurInstr->param2 == OP_PARM_Ev /* rX/memX */))
+                if (    (    pCpu->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
+                         && pCpu->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
+                    ||  (    pCpu->pCurInstr->fParam1 == OP_PARM_Gv /* rX */
+                         && pCpu->pCurInstr->fParam2 == OP_PARM_Ev /* rX/memX */))
                     return true;
 
@@ -1448,5 +1448,5 @@
 
     /* shl eax,1 will be assembled to the form without the immediate byte. */
-    if (    pCpu->pCurInstr->param2 == OP_PARM_Ib
+    if (    pCpu->pCurInstr->fParam2 == OP_PARM_Ib
         &&  (uint8_t)pCpu->param2.parval == 1)
     {
Index: /trunk/src/VBox/VMM/VMMR3/CSAM.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/CSAM.cpp	(revision 41737)
+++ /trunk/src/VBox/VMM/VMMR3/CSAM.cpp	(revision 41738)
@@ -881,5 +881,5 @@
 
     case OP_PUSH:
-        if (pCpu->pCurInstr->param1 != OP_PARM_REG_CS)
+        if (pCpu->pCurInstr->fParam1 != OP_PARM_REG_CS)
             break;
 
@@ -956,5 +956,5 @@
     {
         // return or jump/call through a jump table
-        if (OP_PARM_VTYPE(pCpu->pCurInstr->param1) != OP_PARM_J)
+        if (OP_PARM_VTYPE(pCpu->pCurInstr->fParam1) != OP_PARM_J)
         {
 #ifdef DEBUG
@@ -1304,5 +1304,5 @@
          * If it's harmless, then don't bother checking it (the disasm tables had better be accurate!)
          */
-        if ((cpu.pCurInstr->optype & ~DISOPTYPE_RRM_MASK) == DISOPTYPE_HARMLESS)
+        if ((cpu.pCurInstr->fOpType & ~DISOPTYPE_RRM_MASK) == DISOPTYPE_HARMLESS)
         {
             AssertMsg(pfnCSAMR3Analyse(pVM, &cpu, pInstrGC, pCurInstrGC, pCacheRec, (void *)pPage) == VWRN_CONTINUE_ANALYSIS, ("Instruction incorrectly marked harmless?!?!?\n"));
@@ -1327,5 +1327,5 @@
 
         // For our first attempt, we'll handle only simple relative jumps and calls (immediate offset coded in instruction)
-        if (    ((cpu.pCurInstr->optype & DISOPTYPE_CONTROLFLOW) && (OP_PARM_VTYPE(cpu.pCurInstr->param1) == OP_PARM_J))
+        if (    ((cpu.pCurInstr->fOpType & DISOPTYPE_CONTROLFLOW) && (OP_PARM_VTYPE(cpu.pCurInstr->fParam1) == OP_PARM_J))
             ||  (cpu.pCurInstr->uOpcode == OP_CALL && cpu.param1.fUse == DISUSE_DISPLACEMENT32))  /* simple indirect call (call dword ptr [address]) */
         {
@@ -1395,5 +1395,5 @@
 
             rc = VWRN_CONTINUE_ANALYSIS;
-        } //if ((cpu.pCurInstr->optype & DISOPTYPE_CONTROLFLOW) && (OP_PARM_VTYPE(cpu.pCurInstr->param1) == OP_PARM_J))
+        } //if ((cpu.pCurInstr->fOpType & DISOPTYPE_CONTROLFLOW) && (OP_PARM_VTYPE(cpu.pCurInstr->fParam1) == OP_PARM_J))
 #ifdef CSAM_SCAN_JUMP_TABLE
         else
@@ -2567,5 +2567,5 @@
                     if (    rc == VINF_SUCCESS
                         &&  cpu.pCurInstr->uOpcode == OP_PUSH
-                        &&  cpu.pCurInstr->param1 == OP_PARM_REG_CS)
+                        &&  cpu.pCurInstr->fParam1 == OP_PARM_REG_CS)
                     {
                         rc = PATMR3InstallPatch(pVM, pHandler - aOpenBsdPushCSOffset[i], PATMFL_CODE32 | PATMFL_GUEST_SPECIFIC);
Index: /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp	(revision 41737)
+++ /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp	(revision 41738)
@@ -622,5 +622,5 @@
         rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
         if (    RT_SUCCESS(rc)
-            &&  (cpu.pCurInstr->optype & DISOPTYPE_PORTIO))
+            &&  (cpu.pCurInstr->fOpType & DISOPTYPE_PORTIO))
         {
             /*
Index: /trunk/src/VBox/VMM/VMMR3/PATM.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/PATM.cpp	(revision 41737)
+++ /trunk/src/VBox/VMM/VMMR3/PATM.cpp	(revision 41738)
@@ -1395,5 +1395,5 @@
     {
         /* No unconditional jumps or calls without fixed displacements. */
-        if (    (pCpu->pCurInstr->optype & DISOPTYPE_CONTROLFLOW)
+        if (    (pCpu->pCurInstr->fOpType & DISOPTYPE_CONTROLFLOW)
              && (pCpu->pCurInstr->uOpcode == OP_JMP || pCpu->pCurInstr->uOpcode == OP_CALL)
            )
@@ -1402,5 +1402,5 @@
             if (    pCpu->param1.cb == 6 /* far call/jmp */
                 ||  (pCpu->pCurInstr->uOpcode == OP_CALL && !(pPatch->flags & PATMFL_SUPPORT_CALLS))
-                ||  (OP_PARM_VTYPE(pCpu->pCurInstr->param1) != OP_PARM_J && !(pPatch->flags & PATMFL_SUPPORT_INDIRECT_CALLS))
+                ||  (OP_PARM_VTYPE(pCpu->pCurInstr->fParam1) != OP_PARM_J && !(pPatch->flags & PATMFL_SUPPORT_INDIRECT_CALLS))
                )
             {
@@ -1502,5 +1502,5 @@
 
     default:
-        if (pCpu->pCurInstr->optype & (DISOPTYPE_PRIVILEGED_NOTRAP))
+        if (pCpu->pCurInstr->fOpType & (DISOPTYPE_PRIVILEGED_NOTRAP))
         {
             patmAddIllegalInstrRecord(pVM, pPatch, pCurInstrGC);
@@ -1511,5 +1511,5 @@
 
     /* If single instruction patch, we've copied enough instructions *and* the current instruction is not a relative jump. */
-    if ((pPatch->flags & PATMFL_CHECK_SIZE) && pPatch->cbPatchBlockSize > SIZEOF_NEARJUMP32 && !(pCpu->pCurInstr->optype & DISOPTYPE_RELATIVE_CONTROLFLOW))
+    if ((pPatch->flags & PATMFL_CHECK_SIZE) && pPatch->cbPatchBlockSize > SIZEOF_NEARJUMP32 && !(pCpu->pCurInstr->fOpType & DISOPTYPE_RELATIVE_CONTROLFLOW))
     {
         /* The end marker for this kind of patch is any instruction at a location outside our patch jump. */
@@ -1554,5 +1554,5 @@
     {
         // no unconditional jumps or calls without fixed displacements
-        if (    (pCpu->pCurInstr->optype & DISOPTYPE_CONTROLFLOW)
+        if (    (pCpu->pCurInstr->fOpType & DISOPTYPE_CONTROLFLOW)
              && (pCpu->pCurInstr->uOpcode == OP_JMP || pCpu->pCurInstr->uOpcode == OP_CALL)
            )
@@ -1561,5 +1561,5 @@
             if (    pCpu->param1.cb == 6 /* far call/jmp */
                 ||  (pCpu->pCurInstr->uOpcode == OP_CALL && !(pPatch->flags & PATMFL_SUPPORT_CALLS))
-                ||  (OP_PARM_VTYPE(pCpu->pCurInstr->param1) != OP_PARM_J && !(pPatch->flags & PATMFL_SUPPORT_INDIRECT_CALLS))
+                ||  (OP_PARM_VTYPE(pCpu->pCurInstr->fParam1) != OP_PARM_J && !(pPatch->flags & PATMFL_SUPPORT_INDIRECT_CALLS))
                )
             {
@@ -1583,5 +1583,5 @@
     #if 0
         ///@todo we can handle certain in/out and privileged instructions in the guest context
-        if (pCpu->pCurInstr->optype & DISOPTYPE_PRIVILEGED && pCpu->pCurInstr->uOpcode != OP_STI)
+        if (pCpu->pCurInstr->fOpType & DISOPTYPE_PRIVILEGED && pCpu->pCurInstr->uOpcode != OP_STI)
         {
             Log(("Illegal instructions for function patch!!\n"));
@@ -1616,5 +1616,5 @@
         return VWRN_CONTINUE_ANALYSIS;
     default:
-        if (pCpu->pCurInstr->optype & (DISOPTYPE_PRIVILEGED_NOTRAP))
+        if (pCpu->pCurInstr->fOpType & (DISOPTYPE_PRIVILEGED_NOTRAP))
         {
             patmAddIllegalInstrRecord(pVM, pPatch, pCurInstrGC);
@@ -1694,7 +1694,7 @@
      * Indirect calls are handled below.
      */
-    if (   (pCpu->pCurInstr->optype & DISOPTYPE_CONTROLFLOW)
+    if (   (pCpu->pCurInstr->fOpType & DISOPTYPE_CONTROLFLOW)
         && (pCpu->pCurInstr->uOpcode != OP_CALL || (pPatch->flags & PATMFL_SUPPORT_CALLS))
-        && (OP_PARM_VTYPE(pCpu->pCurInstr->param1) == OP_PARM_J))
+        && (OP_PARM_VTYPE(pCpu->pCurInstr->fParam1) == OP_PARM_J))
     {
         RCPTRTYPE(uint8_t *) pTargetGC = PATMResolveBranch(pCpu, pCurInstrGC);
@@ -1745,5 +1745,5 @@
 
     case OP_MOV:
-        if (pCpu->pCurInstr->optype & DISOPTYPE_POTENTIALLY_DANGEROUS)
+        if (pCpu->pCurInstr->fOpType & DISOPTYPE_POTENTIALLY_DANGEROUS)
         {
             /* mov ss, src? */
@@ -1772,7 +1772,7 @@
 
     case OP_POP:
-        if (pCpu->pCurInstr->param1 == OP_PARM_REG_SS)
-        {
-            Assert(pCpu->pCurInstr->optype & DISOPTYPE_INHIBIT_IRQS);
+        if (pCpu->pCurInstr->fParam1 == OP_PARM_REG_SS)
+        {
+            Assert(pCpu->pCurInstr->fOpType & DISOPTYPE_INHIBIT_IRQS);
 
             Log(("Force recompilation of next instruction for OP_MOV at %RRv\n", pCurInstrGC));
@@ -1879,5 +1879,5 @@
 
     case OP_PUSH:
-        if (pCpu->pCurInstr->param1 == OP_PARM_REG_CS)
+        if (pCpu->pCurInstr->fParam1 == OP_PARM_REG_CS)
         {
             rc = patmPatchGenPushCS(pVM, pPatch);
@@ -1979,5 +1979,5 @@
     case OP_MOV_DR:
         /* Note: currently we let DRx writes cause a trap d; our trap handler will decide to interpret it or not. */
-        if (pCpu->pCurInstr->param2 == OP_PARM_Dd)
+        if (pCpu->pCurInstr->fParam2 == OP_PARM_Dd)
         {
             rc = patmPatchGenMovDebug(pVM, pPatch, pCpu);
@@ -1990,5 +1990,5 @@
     case OP_MOV_CR:
         /* Note: currently we let CRx writes cause a trap d; our trap handler will decide to interpret it or not. */
-        if (pCpu->pCurInstr->param2 == OP_PARM_Cd)
+        if (pCpu->pCurInstr->fParam2 == OP_PARM_Cd)
         {
             rc = patmPatchGenMovControl(pVM, pPatch, pCpu);
@@ -2000,5 +2000,5 @@
 
     default:
-        if (pCpu->pCurInstr->optype & (DISOPTYPE_CONTROLFLOW | DISOPTYPE_PRIVILEGED_NOTRAP))
+        if (pCpu->pCurInstr->fOpType & (DISOPTYPE_CONTROLFLOW | DISOPTYPE_PRIVILEGED_NOTRAP))
         {
 gen_illegal_instr:
@@ -2049,5 +2049,5 @@
         if (    (pPatch->flags & PATMFL_CHECK_SIZE)
              &&  pCurInstrGC + pCpu->cbInstr - pInstrGC >= SIZEOF_NEARJUMP32
-             &&  !(pCpu->pCurInstr->optype & DISOPTYPE_RELATIVE_CONTROLFLOW)
+             &&  !(pCpu->pCurInstr->fOpType & DISOPTYPE_RELATIVE_CONTROLFLOW)
              &&  !(pPatch->flags & PATMFL_RECOMPILE_NEXT) /* do not do this when the next instruction *must* be executed! */
            )
@@ -2232,6 +2232,6 @@
 
         /* For our first attempt, we'll handle only simple relative jumps and calls (immediate offset coded in instruction) */
-        if (   (cpu.pCurInstr->optype & DISOPTYPE_CONTROLFLOW)
-            && (OP_PARM_VTYPE(cpu.pCurInstr->param1) == OP_PARM_J)
+        if (   (cpu.pCurInstr->fOpType & DISOPTYPE_CONTROLFLOW)
+            && (OP_PARM_VTYPE(cpu.pCurInstr->fParam1) == OP_PARM_J)
             &&  cpu.pCurInstr->uOpcode != OP_CALL /* complete functions are replaced; don't bother here. */
            )
@@ -2419,5 +2419,5 @@
 
                 default:
-                    if (cpunext.pCurInstr->optype & DISOPTYPE_CONTROLFLOW)
+                    if (cpunext.pCurInstr->fOpType & DISOPTYPE_CONTROLFLOW)
                     {
                         Log(("Unexpected control flow instruction after inhibit irq instruction\n"));
@@ -2453,6 +2453,6 @@
 
         /* For our first attempt, we'll handle only simple relative jumps and calls (immediate offset coded in instruction). */
-        if (   (cpu.pCurInstr->optype & DISOPTYPE_CONTROLFLOW)
-            && (OP_PARM_VTYPE(cpu.pCurInstr->param1) == OP_PARM_J)
+        if (   (cpu.pCurInstr->fOpType & DISOPTYPE_CONTROLFLOW)
+            && (OP_PARM_VTYPE(cpu.pCurInstr->fParam1) == OP_PARM_J)
             &&  cpu.pCurInstr->uOpcode != OP_CALL /* complete functions are replaced; don't bother here. */
            )
@@ -2469,5 +2469,5 @@
 
             /* We don't check if the branch target lies in a valid page as we've already done that in the analysis phase. */
-            if (!(cpu.pCurInstr->optype & DISOPTYPE_UNCOND_CONTROLFLOW))
+            if (!(cpu.pCurInstr->fOpType & DISOPTYPE_UNCOND_CONTROLFLOW))
             {
                 Log(("patmRecompileCodeStream continue passed conditional jump\n"));
@@ -2517,5 +2517,5 @@
         }
         else
-        if (cpu.pCurInstr->optype & DISOPTYPE_UNCOND_CONTROLFLOW)
+        if (cpu.pCurInstr->fOpType & DISOPTYPE_UNCOND_CONTROLFLOW)
         {
             rc = VINF_SUCCESS;
@@ -5198,5 +5198,5 @@
     if (    disret == true
         && (pConflictPatch->flags & PATMFL_CODE32)
-        && (cpu.pCurInstr->uOpcode == OP_JMP || (cpu.pCurInstr->optype & DISOPTYPE_COND_CONTROLFLOW))
+        && (cpu.pCurInstr->uOpcode == OP_JMP || (cpu.pCurInstr->fOpType & DISOPTYPE_COND_CONTROLFLOW))
         && (cpu.param1.fUse & DISUSE_IMMEDIATE32_REL))
     {
@@ -6014,5 +6014,5 @@
         rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCurPatchInstrGC, &CpuOld, 0);
         if (    RT_FAILURE(rc)
-            ||  !(CpuOld.pCurInstr->optype & DISOPTYPE_HARMLESS))
+            ||  !(CpuOld.pCurInstr->fOpType & DISOPTYPE_HARMLESS))
         {
             if (RT_SUCCESS(rc))
@@ -6050,5 +6050,5 @@
 
     if (    RT_SUCCESS(rc)
-        &&  (CpuOld.pCurInstr->optype & DISOPTYPE_HARMLESS)
+        &&  (CpuOld.pCurInstr->fOpType & DISOPTYPE_HARMLESS)
        )
     {
@@ -6065,7 +6065,7 @@
             rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCurInstrGC, &CpuNew, 0);
 
-            fValidInstr = !!(CpuNew.pCurInstr->optype & DISOPTYPE_HARMLESS);
+            fValidInstr = !!(CpuNew.pCurInstr->fOpType & DISOPTYPE_HARMLESS);
             if (    !fValidInstr
-                &&  (CpuNew.pCurInstr->optype & DISOPTYPE_RELATIVE_CONTROLFLOW)
+                &&  (CpuNew.pCurInstr->fOpType & DISOPTYPE_RELATIVE_CONTROLFLOW)
                )
             {
Index: /trunk/src/VBox/VMM/VMMR3/PATMGuest.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/PATMGuest.cpp	(revision 41737)
+++ /trunk/src/VBox/VMM/VMMR3/PATMGuest.cpp	(revision 41738)
@@ -235,5 +235,5 @@
          *  cli
          */
-        if (pCpu->pCurInstr->param1 == OP_PARM_REG_CS)
+        if (pCpu->pCurInstr->fParam1 == OP_PARM_REG_CS)
             return PATMPatchOpenBSDHandlerPrefix(pVM, pCpu, pInstrGC, pInstrHC, pPatchRec);
 
Index: /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp	(revision 41737)
+++ /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp	(revision 41738)
@@ -695,5 +695,5 @@
         Log(("patmPatchGenIndirectCall\n"));
         Assert(pCpu->param1.cb == 4);
-        Assert(OP_PARM_VTYPE(pCpu->pCurInstr->param1) != OP_PARM_J);
+        Assert(OP_PARM_VTYPE(pCpu->pCurInstr->fParam1) != OP_PARM_J);
 
         /* We push it onto the stack here, so the guest's context isn't ruined when this happens to cause
@@ -720,5 +720,5 @@
         AssertMsg(PATMIsPatchGCAddr(pVM, pTargetGC) == false, ("Target is already a patch address (%RRv)?!?\n", pTargetGC));
         Assert(pTargetGC);
-        Assert(OP_PARM_VTYPE(pCpu->pCurInstr->param1) == OP_PARM_J);
+        Assert(OP_PARM_VTYPE(pCpu->pCurInstr->fParam1) == OP_PARM_J);
 
         /** @todo wasting memory as the complex search is overkill and we need only one lookup slot... */
@@ -791,5 +791,5 @@
     Log(("patmPatchGenIndirectJump\n"));
     Assert(pCpu->param1.cb == 4);
-    Assert(OP_PARM_VTYPE(pCpu->pCurInstr->param1) != OP_PARM_J);
+    Assert(OP_PARM_VTYPE(pCpu->pCurInstr->fParam1) != OP_PARM_J);
 
     /* We push it onto the stack here, so the guest's context isn't ruined when this happens to cause
@@ -1158,5 +1158,5 @@
     mod = 0;            //effective address (only)
     rm  = 5;            //disp32
-    if (pCpu->pCurInstr->param1 == OP_PARM_Dd)
+    if (pCpu->pCurInstr->fParam1 == OP_PARM_Dd)
     {
         Assert(0);  // You not come here. Illegal!
@@ -1208,5 +1208,5 @@
     mod = 0;            //effective address (only)
     rm  = 5;            //disp32
-    if (pCpu->pCurInstr->param1 == OP_PARM_Cd)
+    if (pCpu->pCurInstr->fParam1 == OP_PARM_Cd)
     {
         Assert(0);  // You not come here. Illegal!
Index: /trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp	(revision 41737)
+++ /trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp	(revision 41738)
@@ -992,5 +992,5 @@
      */
     if (    pVCpu->trpm.s.uActiveErrorCode == 0
-        &&  (Cpu.pCurInstr->optype & DISOPTYPE_PORTIO))
+        &&  (Cpu.pCurInstr->fOpType & DISOPTYPE_PORTIO))
     {
         VBOXSTRICTRC rcStrict = IOMRCIOPortHandler(pVM, pRegFrame, &Cpu);