Index: /trunk/include/VBox/dis.h
===================================================================
--- /trunk/include/VBox/dis.h	(revision 41736)
+++ /trunk/include/VBox/dis.h	(revision 41737)
@@ -453,5 +453,7 @@
     uint8_t     idxParse3;
     uint8_t     uUnused;
-    uint16_t    opcode;
+    /** The opcode identifier. This DIS specific, @see grp_dis_opcodes and
+     * VBox/disopcode.h. */
+    uint16_t    uOpcode;
     uint16_t    param1;
     uint16_t    param2;
Index: /trunk/include/VBox/disopcode.h
===================================================================
--- /trunk/include/VBox/disopcode.h	(revision 41736)
+++ /trunk/include/VBox/disopcode.h	(revision 41737)
@@ -4,5 +4,5 @@
 
 /*
- * Copyright (C) 2006-2007 Oracle Corporation
+ * Copyright (C) 2006-2012 Oracle Corporation
  *
  * This file is part of VirtualBox Open Source Edition (OSE), as
@@ -37,7 +37,11 @@
 
 
-/** Full Intel X86 opcode list
+/** @defgroup grp_dis_opcodes Opcodes (DISOPCODE::uOpCode)
+ * @ingroup grp_dis
  * @{
  */
+
+/** @name  Full Intel X86 opcode list
+ * @{ */
 #define OP_INVALID      0
 #define OP_OPSIZE       1
@@ -439,5 +443,5 @@
 /** @} */
 
-/** Floating point ops
+/** @name Floating point ops
  * @{
  */
@@ -528,5 +532,5 @@
 /** @} */
 
-/** 3DNow!
+/** @name 3DNow!
  * @{
  */
@@ -601,5 +605,6 @@
 #define OP_SWAPGS       610
 
-/* VT-x instructions */
+/** @name VT-x instructions
+ * @{ */
 #define OP_VMREAD       650
 #define OP_VMWRITE      651
@@ -614,12 +619,15 @@
 #define OP_INVEPT       660
 #define OP_INVVPID      661
-
-/* 64 bits instruction */
+/** @}  */
+
+/** @name 64 bits instruction
+ * @{ */
 #define OP_MOVSXD       700
+/** @}  */
 
 /** @} */
 
 
-/** Opcode parameters
+/** @name Opcode parameters
  * @{
  */
Index: /trunk/src/VBox/Disassembler/DisasmCore.cpp
===================================================================
--- /trunk/src/VBox/Disassembler/DisasmCore.cpp	(revision 41736)
+++ /trunk/src/VBox/Disassembler/DisasmCore.cpp	(revision 41737)
@@ -336,5 +336,5 @@
     {
         uint8_t codebyte = disReadByte(pCpu, uInstrAddr+iByte);
-        uint8_t opcode   = paOneByteMap[codebyte].opcode;
+        uint8_t opcode   = paOneByteMap[codebyte].uOpcode;
 
         /* Hardcoded assumption about OP_* values!! */
@@ -737,5 +737,5 @@
                 pParam->fUse |= DISUSE_REG_CR;
 
-                if (    pCpu->pCurInstr->opcode == OP_MOV_CR
+                if (    pCpu->pCurInstr->uOpcode == OP_MOV_CR
                     &&  pCpu->uOpMode == DISCPUMODE_32BIT
                     &&  (pCpu->fPrefix & DISPREFIX_LOCK))
@@ -1754,5 +1754,5 @@
         {
         case OP_OPSIZE: /* 0x66 */
-            if (g_aTwoByteMapX86_PF66[pCpu->bOpCode].opcode != OP_INVALID)
+            if (g_aTwoByteMapX86_PF66[pCpu->bOpCode].uOpcode != OP_INVALID)
             {
                 /* Table entry is valid, so use the extension table. */
@@ -1766,5 +1766,5 @@
 
         case OP_REPNE:   /* 0xF2 */
-            if (g_aTwoByteMapX86_PFF2[pCpu->bOpCode].opcode != OP_INVALID)
+            if (g_aTwoByteMapX86_PFF2[pCpu->bOpCode].uOpcode != OP_INVALID)
             {
                 /* Table entry is valid, so use the extension table. */
@@ -1777,5 +1777,5 @@
 
         case OP_REPE:  /* 0xF3 */
-            if (g_aTwoByteMapX86_PFF3[pCpu->bOpCode].opcode != OP_INVALID)
+            if (g_aTwoByteMapX86_PFF3[pCpu->bOpCode].uOpcode != OP_INVALID)
             {
                 /* Table entry is valid, so use the extension table. */
@@ -1822,5 +1822,5 @@
             pOpcode = &pOpcode[pCpu->bOpCode & 0xf];
 
-            if (pOpcode->opcode != OP_INVALID)
+            if (pOpcode->uOpcode != OP_INVALID)
             {
                 /* Table entry is valid, so use the extension table. */
@@ -1839,5 +1839,5 @@
             pOpcode = &pOpcode[pCpu->bOpCode & 0xf];
 
-            if (pOpcode->opcode != OP_INVALID)
+            if (pOpcode->uOpcode != OP_INVALID)
             {
                 /* Table entry is valid, so use the extension table. */
@@ -1873,5 +1873,5 @@
         pOpcode = &pOpcode[pCpu->bOpCode & 0xf];
 
-        if (pOpcode->opcode != OP_INVALID)
+        if (pOpcode->uOpcode != OP_INVALID)
         {
             /* Table entry is valid, so use the extension table. */
@@ -2623,5 +2623,5 @@
      * Filter out the valid lock sequences.
      */
-    switch (pCpu->pCurInstr->opcode)
+    switch (pCpu->pCurInstr->uOpcode)
     {
         /* simple: no variations */
@@ -2668,5 +2668,5 @@
      */
     pCpu->pCurInstr = &g_aTwoByteMapX86[11];
-    Assert(pCpu->pCurInstr->opcode == OP_ILLUD2);
-}
-
+    Assert(pCpu->pCurInstr->uOpcode == OP_ILLUD2);
+}
+
Index: /trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp
===================================================================
--- /trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp	(revision 41736)
+++ /trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp	(revision 41737)
@@ -390,6 +390,6 @@
      */
     size_t const offInstruction = cchOutput;
-    if (    pOp->opcode == OP_INVALID
-        ||  (   pOp->opcode == OP_ILLUD2
+    if (    pOp->uOpcode == OP_INVALID
+        ||  (   pOp->uOpcode == OP_ILLUD2
              && (pCpu->fPrefix & DISPREFIX_LOCK)))
     {
@@ -414,5 +414,5 @@
         char szTmpFmt[48];
         const char *pszFmt = pOp->pszOpcode;
-        switch (pOp->opcode)
+        switch (pOp->uOpcode)
         {
             case OP_JECXZ:
@@ -560,9 +560,9 @@
             do { \
                 if (    OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_p \
-                    &&  pOp->opcode != OP_LDS /* table bugs? */ \
-                    &&  pOp->opcode != OP_LES \
-                    &&  pOp->opcode != OP_LFS \
-                    &&  pOp->opcode != OP_LGS \
-                    &&  pOp->opcode != OP_LSS ) \
+                    &&  pOp->uOpcode != OP_LDS /* table bugs? */ \
+                    &&  pOp->uOpcode != OP_LES \
+                    &&  pOp->uOpcode != OP_LFS \
+                    &&  pOp->uOpcode != OP_LGS \
+                    &&  pOp->uOpcode != OP_LSS ) \
                     PUT_SZ("far "); \
             } while (0)
@@ -595,5 +595,5 @@
                     case OP_PARM_NONE: \
                         if (    OP_PARM_VTYPE(pParam->param) == OP_PARM_M \
-                            &&  ((pParam->fUse & DISUSE_REG_FP) || pOp->opcode == OP_FLD)) \
+                            &&  ((pParam->fUse & DISUSE_REG_FP) || pOp->uOpcode == OP_FLD)) \
                             PUT_SZ("tword "); \
                         break; \
@@ -674,5 +674,5 @@
                                while the register variants deals with 16, 32 & 64 in the normal fashion. */
                             if (    pParam->param != OP_PARM_Ev
-                                ||  pOp->opcode != OP_MOV
+                                ||  pOp->uOpcode != OP_MOV
                                 ||  (   pOp->param1 != OP_PARM_Sw
                                      && pOp->param2 != OP_PARM_Sw))
@@ -865,10 +865,10 @@
                         Assert(iParam == 1);
                         bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
-                                    && pOp->opcode != OP_CALL
-                                    && pOp->opcode != OP_LOOP
-                                    && pOp->opcode != OP_LOOPE
-                                    && pOp->opcode != OP_LOOPNE
-                                    && pOp->opcode != OP_JECXZ;
-                        if (pOp->opcode == OP_CALL)
+                                    && pOp->uOpcode != OP_CALL
+                                    && pOp->uOpcode != OP_LOOP
+                                    && pOp->uOpcode != OP_LOOPE
+                                    && pOp->uOpcode != OP_LOOPNE
+                                    && pOp->uOpcode != OP_JECXZ;
+                        if (pOp->uOpcode == OP_CALL)
                             fFlags &= ~DIS_FMT_FLAGS_RELATIVE_BRANCH;
 
@@ -1232,5 +1232,5 @@
      * Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
      */
-    if (    pCpu->pCurInstr->opcode == OP_SHL
+    if (    pCpu->pCurInstr->uOpcode == OP_SHL
         &&  pCpu->ModRM.Bits.Reg == 6)
         return true;
@@ -1312,5 +1312,5 @@
     if (fPrefixes)
     {
-        switch (pCpu->pCurInstr->opcode)
+        switch (pCpu->pCurInstr->uOpcode)
         {
             /* nop w/ prefix(es). */
@@ -1348,5 +1348,5 @@
     if (fPrefixes & ~DISPREFIX_SEG)
     {
-        switch (pCpu->pCurInstr->opcode)
+        switch (pCpu->pCurInstr->uOpcode)
         {
             case OP_POP:
@@ -1379,5 +1379,5 @@
        )
     {
-        switch (pCpu->pCurInstr->opcode)
+        switch (pCpu->pCurInstr->uOpcode)
         {
             case OP_ADD:
@@ -1405,5 +1405,5 @@
     if (pCpu->ModRM.Bits.Mod == 3 /* reg,reg */)
     {
-        switch (pCpu->pCurInstr->opcode)
+        switch (pCpu->pCurInstr->uOpcode)
         {
             case OP_ADD:
@@ -1451,5 +1451,5 @@
         &&  (uint8_t)pCpu->param2.parval == 1)
     {
-        switch (pCpu->pCurInstr->opcode)
+        switch (pCpu->pCurInstr->uOpcode)
         {
             case OP_SHL:
@@ -1467,5 +1467,5 @@
     if (pCpu->bOpCode == 0x82)
     {
-        switch (pCpu->pCurInstr->opcode)
+        switch (pCpu->pCurInstr->uOpcode)
         {
             case OP_ADD:
@@ -1487,5 +1487,5 @@
     /* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
        says (intel doesn't appear to care). */
-    switch (pCpu->pCurInstr->opcode)
+    switch (pCpu->pCurInstr->uOpcode)
     {
         case OP_SETO:
@@ -1515,5 +1515,5 @@
      * doesn't quite make sense...
      */
-    if (    pCpu->pCurInstr->opcode == OP_MOVZX
+    if (    pCpu->pCurInstr->uOpcode == OP_MOVZX
         &&  pCpu->bOpCode == 0xB7
         &&  (pCpu->uCpuMode == DISCPUMODE_16BIT) != !!(fPrefixes & DISPREFIX_OPSIZE))
Index: /trunk/src/VBox/Disassembler/testcase/tstDisasm-2.cpp
===================================================================
--- /trunk/src/VBox/Disassembler/testcase/tstDisasm-2.cpp	(revision 41736)
+++ /trunk/src/VBox/Disassembler/testcase/tstDisasm-2.cpp	(revision 41737)
@@ -132,5 +132,5 @@
 static bool MyDisasIsValidInstruction(DISCPUSTATE const *pCpu)
 {
-    switch (pCpu->pCurInstr->opcode)
+    switch (pCpu->pCurInstr->uOpcode)
     {
         /* These doesn't take memory operands. */
@@ -338,6 +338,6 @@
             State.fUndefOp = rc == VERR_DIS_INVALID_OPCODE
                           || rc == VERR_DIS_GEN_FAILURE
-                          || State.Cpu.pCurInstr->opcode == OP_INVALID
-                          || State.Cpu.pCurInstr->opcode == OP_ILLUD2
+                          || State.Cpu.pCurInstr->uOpcode == OP_INVALID
+                          || State.Cpu.pCurInstr->uOpcode == OP_ILLUD2
                           || (    State.enmUndefOp == kUndefOp_DefineByte
                               && !MyDisasIsValidInstruction(&State.Cpu));
@@ -357,5 +357,5 @@
             else if (!State.fUndefOp && State.enmUndefOp == kUndefOp_All)
             {
-                RTPrintf("%s: error at %#RX64: unexpected valid instruction (op=%d)\n", argv0, State.uAddress, State.Cpu.pCurInstr->opcode);
+                RTPrintf("%s: error at %#RX64: unexpected valid instruction (op=%d)\n", argv0, State.uAddress, State.Cpu.pCurInstr->uOpcode);
                 pfnFormatter(&State);
                 rcRet = VERR_GENERAL_FAILURE;
@@ -363,5 +363,5 @@
             else if (State.fUndefOp && State.enmUndefOp == kUndefOp_Fail)
             {
-                RTPrintf("%s: error at %#RX64: undefined opcode (op=%d)\n", argv0, State.uAddress, State.Cpu.pCurInstr->opcode);
+                RTPrintf("%s: error at %#RX64: undefined opcode (op=%d)\n", argv0, State.uAddress, State.Cpu.pCurInstr->uOpcode);
                 pfnFormatter(&State);
                 rcRet = VERR_GENERAL_FAILURE;
Index: /trunk/src/VBox/Runtime/testcase/tstLdrDisasmTest.cpp
===================================================================
--- /trunk/src/VBox/Runtime/testcase/tstLdrDisasmTest.cpp	(revision 41736)
+++ /trunk/src/VBox/Runtime/testcase/tstLdrDisasmTest.cpp	(revision 41737)
@@ -128,5 +128,5 @@
             if (RT_FAILURE(rc)) \
                 return CodeIndex | 0xf000; \
-            if (Cpu.pCurInstr->opcode != (enmOp)) \
+            if (Cpu.pCurInstr->uOpcode != (enmOp)) \
                 return CodeIndex| 0xe000; \
             if (cb != (cbInstr)) \
Index: /trunk/src/VBox/VMM/VMMAll/EMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/EMAll.cpp	(revision 41736)
+++ /trunk/src/VBox/VMM/VMMAll/EMAll.cpp	(revision 41737)
@@ -749,5 +749,5 @@
 static const char *emGetMnemonic(PDISCPUSTATE pDis)
 {
-    switch (pDis->pCurInstr->opcode)
+    switch (pDis->pCurInstr->uOpcode)
     {
         case OP_XCHG:       return "Xchg";
@@ -793,5 +793,5 @@
 
         default:
-            Log(("Unknown opcode %d\n", pDis->pCurInstr->opcode));
+            Log(("Unknown opcode %d\n", pDis->pCurInstr->uOpcode));
             return "???";
     }
@@ -2657,5 +2657,5 @@
         dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
 
-    if (pDis->pCurInstr->opcode == OP_LIDT)
+    if (pDis->pCurInstr->uOpcode == OP_LIDT)
         CPUMSetGuestIDTR(pVCpu, dtr32.uAddr, dtr32.cb);
     else
@@ -3093,5 +3093,5 @@
         uint32_t cpl = CPUMGetGuestCPL(pVCpu, pRegFrame);
         if (    cpl != 0
-            &&  pDis->pCurInstr->opcode != OP_RDTSC)    /* rdtsc requires emulation in ring 3 as well */
+            &&  pDis->pCurInstr->uOpcode != OP_RDTSC)    /* rdtsc requires emulation in ring 3 as well */
         {
             Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
@@ -3106,11 +3106,11 @@
     if (    (pDis->fPrefix & (DISPREFIX_REPNE | DISPREFIX_REP))
         ||  (   (pDis->fPrefix & DISPREFIX_LOCK)
-             && pDis->pCurInstr->opcode != OP_CMPXCHG
-             && pDis->pCurInstr->opcode != OP_CMPXCHG8B
-             && pDis->pCurInstr->opcode != OP_XADD
-             && pDis->pCurInstr->opcode != OP_OR
-             && pDis->pCurInstr->opcode != OP_AND
-             && pDis->pCurInstr->opcode != OP_XOR
-             && pDis->pCurInstr->opcode != OP_BTR
+             && pDis->pCurInstr->uOpcode != OP_CMPXCHG
+             && pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
+             && pDis->pCurInstr->uOpcode != OP_XADD
+             && pDis->pCurInstr->uOpcode != OP_OR
+             && pDis->pCurInstr->uOpcode != OP_AND
+             && pDis->pCurInstr->uOpcode != OP_XOR
+             && pDis->pCurInstr->uOpcode != OP_BTR
             )
        )
@@ -3118,13 +3118,13 @@
     if (    (pDis->fPrefix & DISPREFIX_REPNE)
         ||  (   (pDis->fPrefix & DISPREFIX_REP)
-             && pDis->pCurInstr->opcode != OP_STOSWD
+             && pDis->pCurInstr->uOpcode != OP_STOSWD
             )
         ||  (   (pDis->fPrefix & DISPREFIX_LOCK)
-             && pDis->pCurInstr->opcode != OP_OR
-             && pDis->pCurInstr->opcode != OP_AND
-             && pDis->pCurInstr->opcode != OP_XOR
-             && pDis->pCurInstr->opcode != OP_BTR
-             && pDis->pCurInstr->opcode != OP_CMPXCHG
-             && pDis->pCurInstr->opcode != OP_CMPXCHG8B
+             && pDis->pCurInstr->uOpcode != OP_OR
+             && pDis->pCurInstr->uOpcode != OP_AND
+             && pDis->pCurInstr->uOpcode != OP_XOR
+             && pDis->pCurInstr->uOpcode != OP_BTR
+             && pDis->pCurInstr->uOpcode != OP_CMPXCHG
+             && pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
             )
        )
@@ -3144,5 +3144,5 @@
         &&  CPUMIsGuestIn64BitCode(pVCpu, pRegFrame))
     {
-        uint32_t uOpCode = pDis->pCurInstr->opcode;
+        uint32_t uOpCode = pDis->pCurInstr->uOpcode;
         if (    uOpCode != OP_STOSWD
             &&  uOpCode != OP_MOV
@@ -3165,5 +3165,5 @@
         {
 # ifdef VBOX_WITH_STATISTICS
-            switch (pDis->pCurInstr->opcode)
+            switch (pDis->pCurInstr->uOpcode)
             {
 #  define INTERPRET_FAILED_CASE(opcode, Instr) \
@@ -3221,5 +3221,5 @@
     LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pDis)));
 #endif
-    switch (pDis->pCurInstr->opcode)
+    switch (pDis->pCurInstr->uOpcode)
     {
         /*
@@ -3329,5 +3329,5 @@
 
         default:
-            Log3(("emInterpretInstructionCPU: opcode=%d\n", pDis->pCurInstr->opcode));
+            Log3(("emInterpretInstructionCPU: opcode=%d\n", pDis->pCurInstr->uOpcode));
             STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
             return VERR_EM_INTERPRETER;
Index: /trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp	(revision 41736)
+++ /trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp	(revision 41737)
@@ -549,5 +549,5 @@
          */
         /** @todo checkup MOVSX implementation! */
-        if (pCpu->pCurInstr->opcode == OP_MOVSX)
+        if (pCpu->pCurInstr->uOpcode == OP_MOVSX)
         {
             if (cb == 1)
@@ -1177,9 +1177,9 @@
     const char *pszInstr;
 
-    if (pCpu->pCurInstr->opcode == OP_XOR)
+    if (pCpu->pCurInstr->uOpcode == OP_XOR)
         pszInstr = "Xor";
-    else if (pCpu->pCurInstr->opcode == OP_OR)
+    else if (pCpu->pCurInstr->uOpcode == OP_OR)
         pszInstr = "Or";
-    else if (pCpu->pCurInstr->opcode == OP_AND)
+    else if (pCpu->pCurInstr->uOpcode == OP_AND)
         pszInstr = "And";
     else
@@ -1528,5 +1528,5 @@
         return rc;
     }
-    switch (pDis->pCurInstr->opcode)
+    switch (pDis->pCurInstr->uOpcode)
     {
         case OP_MOV:
@@ -2144,5 +2144,5 @@
     RTIOPORT    Port = pRegFrame->edx & 0xffff;
     unsigned    cb = 0;
-    if (pCpu->pCurInstr->opcode == OP_INSB)
+    if (pCpu->pCurInstr->uOpcode == OP_INSB)
         cb = 1;
     else
@@ -2313,5 +2313,5 @@
     bool fRc = iomGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &Port, &cb);
     AssertMsg(fRc, ("Failed to get reg/imm port number!\n")); NOREF(fRc);
-    if (pCpu->pCurInstr->opcode == OP_OUTSB)
+    if (pCpu->pCurInstr->uOpcode == OP_OUTSB)
         cb = 1;
     else
Index: /trunk/src/VBox/VMM/VMMAll/PATMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/PATMAll.cpp	(revision 41736)
+++ /trunk/src/VBox/VMM/VMMAll/PATMAll.cpp	(revision 41737)
@@ -381,5 +381,5 @@
     PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpu0(pVM));
 
-    if (pCpu->pCurInstr->opcode == OP_SYSENTER)
+    if (pCpu->pCurInstr->uOpcode == OP_SYSENTER)
     {
         if (    pCtx->SysEnter.cs == 0
@@ -409,5 +409,5 @@
     }
     else
-    if (pCpu->pCurInstr->opcode == OP_SYSEXIT)
+    if (pCpu->pCurInstr->uOpcode == OP_SYSEXIT)
     {
         if (    pCtx->SysEnter.cs == 0
@@ -429,10 +429,10 @@
     }
     else
-    if (pCpu->pCurInstr->opcode == OP_SYSCALL)
+    if (pCpu->pCurInstr->uOpcode == OP_SYSCALL)
     {
         /** @todo implement syscall */
     }
     else
-    if (pCpu->pCurInstr->opcode == OP_SYSRET)
+    if (pCpu->pCurInstr->uOpcode == OP_SYSRET)
     {
         /** @todo implement sysret */
Index: /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp	(revision 41736)
+++ /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp	(revision 41737)
@@ -721,5 +721,5 @@
      *      do_fork
      */
-    if (    pDis->pCurInstr->opcode == OP_BTR
+    if (    pDis->pCurInstr->uOpcode == OP_BTR
         &&  !(offFault & 4)
         /** @todo Validate that the bit index is X86_PTE_RW. */
@@ -761,5 +761,5 @@
 #endif
 
-    LogFlow(("Reused instr %RGv %d at %RGv param1.fUse=%llx param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->opcode, pvFault, pDis->param1.fUse,  pDis->param1.base.reg_gen));
+    LogFlow(("Reused instr %RGv %d at %RGv param1.fUse=%llx param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->uOpcode, pvFault, pDis->param1.fUse,  pDis->param1.base.reg_gen));
 
     /* Non-supervisor mode write means it's used for something else. */
@@ -767,5 +767,5 @@
         return true;
 
-    switch (pDis->pCurInstr->opcode)
+    switch (pDis->pCurInstr->uOpcode)
     {
         /* call implies the actual push of the return address faulted */
@@ -990,5 +990,5 @@
     {
         LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
-                  pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode));
+                  pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->uOpcode));
         rc = VINF_EM_RAW_EMULATE_INSTR;
         STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
@@ -1166,5 +1166,5 @@
             if (   rc == VINF_SUCCESS
                 && !pPage->cLocked                      /* only applies to unlocked pages as we can't free locked ones (e.g. cr3 root). */
-                && pDis->pCurInstr->opcode == OP_MOV
+                && pDis->pCurInstr->uOpcode == OP_MOV
                 && (pvFault & PAGE_OFFSET_MASK) == 0)
             {
@@ -1196,5 +1196,5 @@
          * We have to deal with these or we'll kill the cache and performance.
          */
-        if (    pDis->pCurInstr->opcode == OP_STOSWD
+        if (    pDis->pCurInstr->uOpcode == OP_STOSWD
             &&  !pRegFrame->eflags.Bits.u1DF
             &&  pDis->uOpMode == pDis->uCpuMode
@@ -1238,5 +1238,5 @@
         STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
         Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
-              pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode, pDis->fPrefix));
+              pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->uOpcode, pDis->fPrefix));
         fNotReusedNotForking = true;
     }
Index: /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp	(revision 41736)
+++ /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp	(revision 41737)
@@ -2984,6 +2984,6 @@
             pDis->uCpuMode = enmMode;
             rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, pDis, &cbOp);
-            Assert(RT_FAILURE(rc) || pDis->pCurInstr->opcode == OP_INVLPG);
-            if (RT_SUCCESS(rc) && pDis->pCurInstr->opcode == OP_INVLPG)
+            Assert(RT_FAILURE(rc) || pDis->pCurInstr->uOpcode == OP_INVLPG);
+            if (RT_SUCCESS(rc) && pDis->pCurInstr->uOpcode == OP_INVLPG)
             {
                 Assert(cbOp == pDis->cbInstr);
Index: /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp	(revision 41736)
+++ /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp	(revision 41737)
@@ -3554,5 +3554,5 @@
                     rc = VINF_SUCCESS;
                     Assert(cbOp == pDis->cbInstr);
-                    switch (pDis->pCurInstr->opcode)
+                    switch (pDis->pCurInstr->uOpcode)
                     {
                     case OP_CLI:
Index: /trunk/src/VBox/VMM/VMMR3/CSAM.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/CSAM.cpp	(revision 41736)
+++ /trunk/src/VBox/VMM/VMMR3/CSAM.cpp	(revision 41737)
@@ -797,5 +797,5 @@
     NOREF(pInstrGC);
 
-    switch (pCpu->pCurInstr->opcode)
+    switch (pCpu->pCurInstr->uOpcode)
     {
     case OP_INT:
@@ -821,5 +821,5 @@
 
     // Check for exit points
-    switch (pCpu->pCurInstr->opcode)
+    switch (pCpu->pCurInstr->uOpcode)
     {
     /* It's not a good idea to patch pushf instructions:
@@ -897,5 +897,5 @@
     case OP_IRET:
 #ifdef DEBUG
-        switch(pCpu->pCurInstr->opcode)
+        switch(pCpu->pCurInstr->uOpcode)
         {
         case OP_STR:
@@ -947,5 +947,5 @@
             }
         }
-        if (pCpu->pCurInstr->opcode == OP_IRET)
+        if (pCpu->pCurInstr->uOpcode == OP_IRET)
             return VINF_SUCCESS;    /* Look no further in this branch. */
 
@@ -959,5 +959,5 @@
         {
 #ifdef DEBUG
-            switch(pCpu->pCurInstr->opcode)
+            switch(pCpu->pCurInstr->uOpcode)
             {
             case OP_JMP:
@@ -1084,5 +1084,5 @@
                 }
 
-                switch (cpu.pCurInstr->opcode)
+                switch (cpu.pCurInstr->uOpcode)
                 {
                 case OP_NOP:
@@ -1314,5 +1314,5 @@
         /* Remember the address of the instruction following the ret in case the parent instruction was a call. */
         if (    pCacheRec->pCallExitRec
-            &&  cpu.pCurInstr->opcode == OP_RETN
+            &&  cpu.pCurInstr->uOpcode == OP_RETN
             &&  pCacheRec->pCallExitRec->cInstrAfterRet < CSAM_MAX_CALLEXIT_RET)
         {
@@ -1328,8 +1328,8 @@
         // For our first attempt, we'll handle only simple relative jumps and calls (immediate offset coded in instruction)
         if (    ((cpu.pCurInstr->optype & DISOPTYPE_CONTROLFLOW) && (OP_PARM_VTYPE(cpu.pCurInstr->param1) == OP_PARM_J))
-            ||  (cpu.pCurInstr->opcode == OP_CALL && cpu.param1.fUse == DISUSE_DISPLACEMENT32))  /* simple indirect call (call dword ptr [address]) */
+            ||  (cpu.pCurInstr->uOpcode == OP_CALL && cpu.param1.fUse == DISUSE_DISPLACEMENT32))  /* simple indirect call (call dword ptr [address]) */
         {
             /* We need to parse 'call dword ptr [address]' type of calls to catch cpuid instructions in some recent Linux distributions (e.g. OpenSuse 10.3) */
-            if (    cpu.pCurInstr->opcode == OP_CALL
+            if (    cpu.pCurInstr->uOpcode == OP_CALL
                 &&  cpu.param1.fUse == DISUSE_DISPLACEMENT32)
             {
@@ -1379,5 +1379,5 @@
                     Assert(pPage);
                 }
-                if (cpu.pCurInstr->opcode == OP_CALL)
+                if (cpu.pCurInstr->uOpcode == OP_CALL)
                     rc = csamAnalyseCallCodeStream(pVM, pInstrGC, addr, fCode32, pfnCSAMR3Analyse, (void *)pJmpPage, pCacheRec);
                 else
@@ -1388,5 +1388,5 @@
                 }
             }
-            if (cpu.pCurInstr->opcode == OP_JMP)
+            if (cpu.pCurInstr->uOpcode == OP_JMP)
             {//unconditional jump; return to caller
                 rc = VINF_SUCCESS;
@@ -1398,5 +1398,5 @@
 #ifdef CSAM_SCAN_JUMP_TABLE
         else
-        if (    cpu.pCurInstr->opcode == OP_JMP
+        if (    cpu.pCurInstr->uOpcode == OP_JMP
             &&  (cpu.param1.fUse & (DISUSE_DISPLACEMENT32|DISUSE_INDEX|DISUSE_SCALE)) == (DISUSE_DISPLACEMENT32|DISUSE_INDEX|DISUSE_SCALE)
            )
@@ -1458,5 +1458,5 @@
         }
 next_please:
-        if (cpu.pCurInstr->opcode == OP_JMP)
+        if (cpu.pCurInstr->uOpcode == OP_JMP)
         {
             rc = VINF_SUCCESS;
@@ -2566,5 +2566,5 @@
                     rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pHandler - aOpenBsdPushCSOffset[i], &cpu, NULL);
                     if (    rc == VINF_SUCCESS
-                        &&  cpu.pCurInstr->opcode == OP_PUSH
+                        &&  cpu.pCurInstr->uOpcode == OP_PUSH
                         &&  cpu.pCurInstr->param1 == OP_PARM_REG_CS)
                     {
Index: /trunk/src/VBox/VMM/VMMR3/EMHwaccm.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/EMHwaccm.cpp	(revision 41736)
+++ /trunk/src/VBox/VMM/VMMR3/EMHwaccm.cpp	(revision 41737)
@@ -201,5 +201,5 @@
     if (RT_SUCCESS(rc))
     {
-        switch (Cpu.pCurInstr->opcode)
+        switch (Cpu.pCurInstr->uOpcode)
         {
         /* @todo we can do more now */
@@ -309,5 +309,5 @@
         if (!(Cpu.fPrefix & (DISPREFIX_REP | DISPREFIX_REPNE)))
         {
-            switch (Cpu.pCurInstr->opcode)
+            switch (Cpu.pCurInstr->uOpcode)
             {
                 case OP_IN:
@@ -328,5 +328,5 @@
         else if (Cpu.fPrefix & DISPREFIX_REP)
         {
-            switch (Cpu.pCurInstr->opcode)
+            switch (Cpu.pCurInstr->uOpcode)
             {
                 case OP_INSB:
Index: /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp	(revision 41736)
+++ /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp	(revision 41737)
@@ -430,5 +430,5 @@
         if (!(Cpu.fPrefix & (DISPREFIX_REP | DISPREFIX_REPNE)))
         {
-            switch (Cpu.pCurInstr->opcode)
+            switch (Cpu.pCurInstr->uOpcode)
             {
                 case OP_IN:
@@ -449,5 +449,5 @@
         else if (Cpu.fPrefix & DISPREFIX_REP)
         {
-            switch (Cpu.pCurInstr->opcode)
+            switch (Cpu.pCurInstr->uOpcode)
             {
                 case OP_INSB:
@@ -596,5 +596,5 @@
         rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
         if (    RT_SUCCESS(rc)
-            && (cpu.pCurInstr->opcode == OP_MONITOR || cpu.pCurInstr->opcode == OP_MWAIT))
+            && (cpu.pCurInstr->uOpcode == OP_MONITOR || cpu.pCurInstr->uOpcode == OP_MWAIT))
         {
             uint32_t u32Dummy, u32Features, u32ExtFeatures;
@@ -679,5 +679,5 @@
     if (RT_SUCCESS(rc))
     {
-        if (Cpu.pCurInstr->opcode == OP_SYSENTER)
+        if (Cpu.pCurInstr->uOpcode == OP_SYSENTER)
         {
             if (pCtx->SysEnter.cs != 0)
@@ -694,5 +694,5 @@
 
 #ifdef VBOX_WITH_STATISTICS
-        switch (Cpu.pCurInstr->opcode)
+        switch (Cpu.pCurInstr->uOpcode)
         {
             case OP_SYSENTER:
@@ -776,5 +776,5 @@
         rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
         if (    RT_SUCCESS(rc)
-            &&  Cpu.pCurInstr->opcode == OP_IRET)
+            &&  Cpu.pCurInstr->uOpcode == OP_IRET)
         {
             uint32_t eip, selCS, uEFlags;
@@ -965,5 +965,5 @@
 #ifdef VBOX_WITH_STATISTICS
         PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
-        switch (Cpu.pCurInstr->opcode)
+        switch (Cpu.pCurInstr->uOpcode)
         {
             case OP_INVLPG:
@@ -1035,5 +1035,5 @@
             default:
                 STAM_COUNTER_INC(&pStats->StatMisc);
-                Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
+                Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->uOpcode));
                 break;
         }
@@ -1044,5 +1044,5 @@
         {
             STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
-            switch (Cpu.pCurInstr->opcode)
+            switch (Cpu.pCurInstr->uOpcode)
             {
                 case OP_CLI:
@@ -1099,5 +1099,5 @@
                         STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
 
-                        if (    Cpu.pCurInstr->opcode == OP_MOV_CR
+                        if (    Cpu.pCurInstr->uOpcode == OP_MOV_CR
                             &&  Cpu.param1.fUse == DISUSE_REG_CR /* write */
                            )
Index: /trunk/src/VBox/VMM/VMMR3/HWACCM.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/HWACCM.cpp	(revision 41736)
+++ /trunk/src/VBox/VMM/VMMR3/HWACCM.cpp	(revision 41737)
@@ -1820,5 +1820,5 @@
     AssertRC(rc);
     if (    rc == VINF_SUCCESS
-        &&  pDis->pCurInstr->opcode == OP_MOV
+        &&  pDis->pCurInstr->uOpcode == OP_MOV
         &&  cbOp >= 3)
     {
@@ -1871,5 +1871,5 @@
             pCtx->rip = oldrip;
             if (    rc == VINF_SUCCESS
-                &&  pDis->pCurInstr->opcode == OP_SHR
+                &&  pDis->pCurInstr->uOpcode == OP_SHR
                 &&  pDis->param1.fUse == DISUSE_REG_GEN32
                 &&  pDis->param1.base.reg_gen == uMmioReg
@@ -1986,5 +1986,5 @@
     AssertRC(rc);
     if (    rc == VINF_SUCCESS
-        &&  pDis->pCurInstr->opcode == OP_MOV
+        &&  pDis->pCurInstr->uOpcode == OP_MOV
         &&  cbOp >= 5)
     {
Index: /trunk/src/VBox/VMM/VMMR3/PATM.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/PATM.cpp	(revision 41736)
+++ /trunk/src/VBox/VMM/VMMR3/PATM.cpp	(revision 41737)
@@ -1396,10 +1396,10 @@
         /* No unconditional jumps or calls without fixed displacements. */
         if (    (pCpu->pCurInstr->optype & DISOPTYPE_CONTROLFLOW)
-             && (pCpu->pCurInstr->opcode == OP_JMP || pCpu->pCurInstr->opcode == OP_CALL)
+             && (pCpu->pCurInstr->uOpcode == OP_JMP || pCpu->pCurInstr->uOpcode == OP_CALL)
            )
         {
             Assert(pCpu->param1.cb <= 4 || pCpu->param1.cb == 6);
             if (    pCpu->param1.cb == 6 /* far call/jmp */
-                ||  (pCpu->pCurInstr->opcode == OP_CALL && !(pPatch->flags & PATMFL_SUPPORT_CALLS))
+                ||  (pCpu->pCurInstr->uOpcode == OP_CALL && !(pPatch->flags & PATMFL_SUPPORT_CALLS))
                 ||  (OP_PARM_VTYPE(pCpu->pCurInstr->param1) != OP_PARM_J && !(pPatch->flags & PATMFL_SUPPORT_INDIRECT_CALLS))
                )
@@ -1411,5 +1411,5 @@
 
         /* An unconditional (short) jump right after a cli is a potential problem; we will overwrite whichever function comes afterwards */
-        if (pPatch->opcode == OP_CLI && pCpu->pCurInstr->opcode == OP_JMP)
+        if (pPatch->opcode == OP_CLI && pCpu->pCurInstr->uOpcode == OP_JMP)
         {
             if (   pCurInstrGC > pPatch->pPrivInstrGC
@@ -1425,5 +1425,5 @@
         if (pPatch->opcode == OP_PUSHF)
         {
-            if (pCurInstrGC != pInstrGC && pCpu->pCurInstr->opcode == OP_PUSHF)
+            if (pCurInstrGC != pInstrGC && pCpu->pCurInstr->uOpcode == OP_PUSHF)
             {
                 fIllegalInstr = true;
@@ -1433,5 +1433,5 @@
 
         /* no far returns */
-        if (pCpu->pCurInstr->opcode == OP_RETF)
+        if (pCpu->pCurInstr->uOpcode == OP_RETF)
         {
             pPatch->pTempInfo->nrRetInstr++;
@@ -1439,7 +1439,7 @@
             patmAddIllegalInstrRecord(pVM, pPatch, pCurInstrGC);
         }
-        else if (   pCpu->pCurInstr->opcode == OP_INT3
-                 || pCpu->pCurInstr->opcode == OP_INT
-                 || pCpu->pCurInstr->opcode == OP_INTO)
+        else if (   pCpu->pCurInstr->uOpcode == OP_INT3
+                 || pCpu->pCurInstr->uOpcode == OP_INT
+                 || pCpu->pCurInstr->uOpcode == OP_INTO)
         {
             /* No int xx or into either. */
@@ -1456,5 +1456,5 @@
 
     /* Check for exit points. */
-    switch (pCpu->pCurInstr->opcode)
+    switch (pCpu->pCurInstr->uOpcode)
     {
     case OP_SYSEXIT:
@@ -1478,5 +1478,5 @@
         if (pPatch->opcode == OP_PUSHF)
         {
-            if (pCpu->pCurInstr->opcode == OP_POPF)
+            if (pCpu->pCurInstr->uOpcode == OP_POPF)
             {
                 if (pPatch->cbPatchBlockSize >= SIZEOF_NEARJUMP32)
@@ -1555,10 +1555,10 @@
         // no unconditional jumps or calls without fixed displacements
         if (    (pCpu->pCurInstr->optype & DISOPTYPE_CONTROLFLOW)
-             && (pCpu->pCurInstr->opcode == OP_JMP || pCpu->pCurInstr->opcode == OP_CALL)
+             && (pCpu->pCurInstr->uOpcode == OP_JMP || pCpu->pCurInstr->uOpcode == OP_CALL)
            )
         {
             Assert(pCpu->param1.cb <= 4 || pCpu->param1.cb == 6);
             if (    pCpu->param1.cb == 6 /* far call/jmp */
-                ||  (pCpu->pCurInstr->opcode == OP_CALL && !(pPatch->flags & PATMFL_SUPPORT_CALLS))
+                ||  (pCpu->pCurInstr->uOpcode == OP_CALL && !(pPatch->flags & PATMFL_SUPPORT_CALLS))
                 ||  (OP_PARM_VTYPE(pCpu->pCurInstr->param1) != OP_PARM_J && !(pPatch->flags & PATMFL_SUPPORT_INDIRECT_CALLS))
                )
@@ -1569,5 +1569,5 @@
         }
         else /* no far returns */
-        if (pCpu->pCurInstr->opcode == OP_RETF)
+        if (pCpu->pCurInstr->uOpcode == OP_RETF)
         {
             patmAddIllegalInstrRecord(pVM, pPatch, pCurInstrGC);
@@ -1575,5 +1575,5 @@
         }
         else /* no int xx or into either */
-        if (pCpu->pCurInstr->opcode == OP_INT3 || pCpu->pCurInstr->opcode == OP_INT || pCpu->pCurInstr->opcode == OP_INTO)
+        if (pCpu->pCurInstr->uOpcode == OP_INT3 || pCpu->pCurInstr->uOpcode == OP_INT || pCpu->pCurInstr->uOpcode == OP_INTO)
         {
             patmAddIllegalInstrRecord(pVM, pPatch, pCurInstrGC);
@@ -1583,5 +1583,5 @@
     #if 0
         ///@todo we can handle certain in/out and privileged instructions in the guest context
-        if (pCpu->pCurInstr->optype & DISOPTYPE_PRIVILEGED && pCpu->pCurInstr->opcode != OP_STI)
+        if (pCpu->pCurInstr->optype & DISOPTYPE_PRIVILEGED && pCpu->pCurInstr->uOpcode != OP_STI)
         {
             Log(("Illegal instructions for function patch!!\n"));
@@ -1600,5 +1600,5 @@
 
     // Check for exit points
-    switch (pCpu->pCurInstr->opcode)
+    switch (pCpu->pCurInstr->uOpcode)
     {
     case OP_ILLUD2:
@@ -1695,5 +1695,5 @@
      */
     if (   (pCpu->pCurInstr->optype & DISOPTYPE_CONTROLFLOW)
-        && (pCpu->pCurInstr->opcode != OP_CALL || (pPatch->flags & PATMFL_SUPPORT_CALLS))
+        && (pCpu->pCurInstr->uOpcode != OP_CALL || (pPatch->flags & PATMFL_SUPPORT_CALLS))
         && (OP_PARM_VTYPE(pCpu->pCurInstr->param1) == OP_PARM_J))
     {
@@ -1705,5 +1705,5 @@
         }
 
-        if (pCpu->pCurInstr->opcode == OP_CALL)
+        if (pCpu->pCurInstr->uOpcode == OP_CALL)
         {
             Assert(!PATMIsPatchGCAddr(pVM, pTargetGC));
@@ -1713,5 +1713,5 @@
         }
         else
-            rc = patmPatchGenRelJump(pVM, pPatch, pTargetGC, pCpu->pCurInstr->opcode, !!(pCpu->fPrefix & DISPREFIX_OPSIZE));
+            rc = patmPatchGenRelJump(pVM, pPatch, pTargetGC, pCpu->pCurInstr->uOpcode, !!(pCpu->fPrefix & DISPREFIX_OPSIZE));
 
         if (RT_SUCCESS(rc))
@@ -1721,5 +1721,5 @@
     }
 
-    switch (pCpu->pCurInstr->opcode)
+    switch (pCpu->pCurInstr->uOpcode)
     {
     case OP_CLI:
@@ -2121,5 +2121,5 @@
     NOREF(pInstrGC);
 
-    if (pCpu->pCurInstr->opcode == OP_INT3)
+    if (pCpu->pCurInstr->uOpcode == OP_INT3)
     {
         /* Could be an int3 inserted in a call patch. Check to be sure */
@@ -2133,5 +2133,5 @@
 
             bool disret = patmR3DisInstr(pVM, pPatch, pOrgJumpGC, pOrgJumpHC, PATMREAD_ORGCODE, &cpu, NULL);
-            if (!disret || cpu.pCurInstr->opcode != OP_CALL || cpu.param1.cb != 4 /* only near calls */)
+            if (!disret || cpu.pCurInstr->uOpcode != OP_CALL || cpu.param1.cb != 4 /* only near calls */)
                 return VINF_SUCCESS;
         }
@@ -2139,5 +2139,5 @@
     }
 
-    if (    pCpu->pCurInstr->opcode == OP_ILLUD2
+    if (    pCpu->pCurInstr->uOpcode == OP_ILLUD2
         &&  PATMIsPatchGCAddr(pVM, pCurInstrGC))
     {
@@ -2146,9 +2146,9 @@
     }
 
-    if (   (pCpu->pCurInstr->opcode == OP_CALL && !(pPatch->flags & PATMFL_SUPPORT_CALLS))
-        || pCpu->pCurInstr->opcode == OP_INT
-        || pCpu->pCurInstr->opcode == OP_IRET
-        || pCpu->pCurInstr->opcode == OP_RETN
-        || pCpu->pCurInstr->opcode == OP_RETF
+    if (   (pCpu->pCurInstr->uOpcode == OP_CALL && !(pPatch->flags & PATMFL_SUPPORT_CALLS))
+        || pCpu->pCurInstr->uOpcode == OP_INT
+        || pCpu->pCurInstr->uOpcode == OP_IRET
+        || pCpu->pCurInstr->uOpcode == OP_RETN
+        || pCpu->pCurInstr->uOpcode == OP_RETF
        )
     {
@@ -2156,5 +2156,5 @@
     }
 
-    if (pCpu->pCurInstr->opcode == OP_ILLUD2)
+    if (pCpu->pCurInstr->uOpcode == OP_ILLUD2)
         return VINF_SUCCESS;
 
@@ -2234,5 +2234,5 @@
         if (   (cpu.pCurInstr->optype & DISOPTYPE_CONTROLFLOW)
             && (OP_PARM_VTYPE(cpu.pCurInstr->param1) == OP_PARM_J)
-            &&  cpu.pCurInstr->opcode != OP_CALL /* complete functions are replaced; don't bother here. */
+            &&  cpu.pCurInstr->uOpcode != OP_CALL /* complete functions are replaced; don't bother here. */
            )
         {
@@ -2266,7 +2266,7 @@
                 patmPatchAddDisasmJump(pVM, pPatch, pTargetGC);
 
-                if (cpu.pCurInstr->opcode == OP_CALL)  pPatch->pTempInfo->nrCalls++;
+                if (cpu.pCurInstr->uOpcode == OP_CALL)  pPatch->pTempInfo->nrCalls++;
                 rc = patmr3DisasmCode(pVM, pInstrGC, pTargetGC, pfnPATMR3Disasm, pCacheRec);
-                if (cpu.pCurInstr->opcode == OP_CALL)  pPatch->pTempInfo->nrCalls--;
+                if (cpu.pCurInstr->uOpcode == OP_CALL)  pPatch->pTempInfo->nrCalls--;
 
                 if (rc != VINF_SUCCESS) {
@@ -2274,5 +2274,5 @@
                 }
             }
-            if (cpu.pCurInstr->opcode == OP_JMP)
+            if (cpu.pCurInstr->uOpcode == OP_JMP)
             {
                 /* Unconditional jump; return to caller. */
@@ -2411,5 +2411,5 @@
                     goto end;
                 }
-                switch(cpunext.pCurInstr->opcode)
+                switch(cpunext.pCurInstr->uOpcode)
                 {
                 case OP_IRET:       /* inhibit cleared in generated code */
@@ -2432,5 +2432,5 @@
 
                 /* Note: after a cli we must continue to a proper exit point */
-                if (cpunext.pCurInstr->opcode != OP_CLI)
+                if (cpunext.pCurInstr->uOpcode != OP_CLI)
                 {
                     rc = pfnPATMR3Recompile(pVM, &cpunext, pInstrGC, pNextInstrGC, pCacheRec);
@@ -2455,5 +2455,5 @@
         if (   (cpu.pCurInstr->optype & DISOPTYPE_CONTROLFLOW)
             && (OP_PARM_VTYPE(cpu.pCurInstr->param1) == OP_PARM_J)
-            &&  cpu.pCurInstr->opcode != OP_CALL /* complete functions are replaced; don't bother here. */
+            &&  cpu.pCurInstr->uOpcode != OP_CALL /* complete functions are replaced; don't bother here. */
            )
         {
@@ -2499,7 +2499,7 @@
                 }
 
-                if (cpu.pCurInstr->opcode == OP_CALL)  pPatch->pTempInfo->nrCalls++;
+                if (cpu.pCurInstr->uOpcode == OP_CALL)  pPatch->pTempInfo->nrCalls++;
                 rc = patmRecompileCodeStream(pVM, pInstrGC, addr, pfnPATMR3Recompile, pCacheRec);
-                if (cpu.pCurInstr->opcode == OP_CALL)  pPatch->pTempInfo->nrCalls--;
+                if (cpu.pCurInstr->uOpcode == OP_CALL)  pPatch->pTempInfo->nrCalls--;
 
                 if(pTargetPatch)
@@ -2978,5 +2978,5 @@
     disret = patmR3DisInstr(pVM, pPatch, pCurInstrGC, pCurInstrHC, PATMREAD_ORGCODE, &cpuPush, &cbInstr);
     Assert(disret);
-    if (disret && cpuPush.pCurInstr->opcode == OP_PUSH)
+    if (disret && cpuPush.pCurInstr->uOpcode == OP_PUSH)
     {
         RTRCPTR  pJmpInstrGC;
@@ -2986,5 +2986,5 @@
         disret = patmR3DisInstr(pVM, pPatch, pCurInstrGC, pCurInstrHC, PATMREAD_ORGCODE, &cpuJmp, &cbInstr);
         if (   disret
-            && cpuJmp.pCurInstr->opcode == OP_JMP
+            && cpuJmp.pCurInstr->uOpcode == OP_JMP
             && (pJmpInstrGC = PATMResolveBranch(&cpuJmp, pCurInstrGC))
            )
@@ -3570,7 +3570,7 @@
 
     Assert(pPatch->flags & PATMFL_REPLACE_FUNCTION_CALL);
-    Assert((pCpu->pCurInstr->opcode == OP_CALL || pCpu->pCurInstr->opcode == OP_JMP) && pCpu->cbInstr == SIZEOF_NEARJUMP32);
-
-    if ((pCpu->pCurInstr->opcode != OP_CALL && pCpu->pCurInstr->opcode != OP_JMP) || pCpu->cbInstr != SIZEOF_NEARJUMP32)
+    Assert((pCpu->pCurInstr->uOpcode == OP_CALL || pCpu->pCurInstr->uOpcode == OP_JMP) && pCpu->cbInstr == SIZEOF_NEARJUMP32);
+
+    if ((pCpu->pCurInstr->uOpcode != OP_CALL && pCpu->pCurInstr->uOpcode != OP_JMP) || pCpu->cbInstr != SIZEOF_NEARJUMP32)
     {
         rc = VERR_PATCHING_REFUSED;
@@ -3602,5 +3602,5 @@
 
             disret = patmR3DisInstr(pVM, pPatch, pTargetGC, pTmpInstrHC, PATMREAD_ORGCODE, &cpu, &cbInstr);
-            if (disret == false || cpu.pCurInstr->opcode != OP_JMP)
+            if (disret == false || cpu.pCurInstr->uOpcode != OP_JMP)
                 break;
 
@@ -3894,5 +3894,5 @@
      * make sure this never happens. (unless a trap is triggered (intentionally or not))
      */
-    switch (pCpu->pCurInstr->opcode)
+    switch (pCpu->pCurInstr->uOpcode)
     {
     case OP_JO:
@@ -4251,8 +4251,8 @@
 
     pPatchRec->patch.cbPrivInstr = cbInstr;
-    pPatchRec->patch.opcode      = cpu.pCurInstr->opcode;
+    pPatchRec->patch.opcode      = cpu.pCurInstr->uOpcode;
 
     /* Restricted hinting for now. */
-    Assert(!(flags & PATMFL_INSTR_HINT) || cpu.pCurInstr->opcode == OP_CLI);
+    Assert(!(flags & PATMFL_INSTR_HINT) || cpu.pCurInstr->uOpcode == OP_CLI);
 
     /* Initialize cache record patch pointer. */
@@ -4317,5 +4317,5 @@
     if (pPatchRec->patch.flags & PATMFL_GUEST_SPECIFIC)
     {
-        switch (cpu.pCurInstr->opcode)
+        switch (cpu.pCurInstr->uOpcode)
         {
         case OP_SYSENTER:
@@ -4337,5 +4337,5 @@
     else
     {
-        switch (cpu.pCurInstr->opcode)
+        switch (cpu.pCurInstr->uOpcode)
         {
         case OP_SYSENTER:
@@ -4381,5 +4381,5 @@
         case OP_CLI:
             Log(("PATMR3InstallPatch %s %RRv code32=%d\n", patmGetInstructionString(pPatchRec->patch.opcode, pPatchRec->patch.flags), pInstrGC, (flags & PATMFL_CODE32) ? 1 : 0));
-            rc = PATMR3PatchBlock(pVM, pInstrGC, pInstrHC, cpu.pCurInstr->opcode, cbInstr, pPatchRec);
+            rc = PATMR3PatchBlock(pVM, pInstrGC, pInstrHC, cpu.pCurInstr->uOpcode, cbInstr, pPatchRec);
             break;
 
@@ -5198,5 +5198,5 @@
     if (    disret == true
         && (pConflictPatch->flags & PATMFL_CODE32)
-        && (cpu.pCurInstr->opcode == OP_JMP || (cpu.pCurInstr->optype & DISOPTYPE_COND_CONTROLFLOW))
+        && (cpu.pCurInstr->uOpcode == OP_JMP || (cpu.pCurInstr->optype & DISOPTYPE_COND_CONTROLFLOW))
         && (cpu.param1.fUse & DISUSE_IMMEDIATE32_REL))
     {
@@ -6280,7 +6280,7 @@
 
         if (    rc == VINF_SUCCESS
-            &&  (   Cpu.pCurInstr->opcode == OP_PUSHF
-                 || Cpu.pCurInstr->opcode == OP_PUSH
-                 || Cpu.pCurInstr->opcode == OP_CALL)
+            &&  (   Cpu.pCurInstr->uOpcode == OP_PUSHF
+                 || Cpu.pCurInstr->uOpcode == OP_PUSH
+                 || Cpu.pCurInstr->uOpcode == OP_CALL)
            )
         {
@@ -6289,5 +6289,5 @@
             STAM_COUNTER_INC(&pVM->patm.s.StatPushTrap);
 
-            if (Cpu.pCurInstr->opcode == OP_PUSH)
+            if (Cpu.pCurInstr->uOpcode == OP_PUSH)
             {
                 rc = PGMShwGetPage(pVCpu, pCtx->esp, &fFlags, NULL);
@@ -6409,5 +6409,5 @@
             PGMPhysReleasePageMappingLock(pVM, &cacheRec.Lock);
 
-        if (disret && cpu.pCurInstr->opcode == OP_RETN)
+        if (disret && cpu.pCurInstr->uOpcode == OP_RETN)
         {
             RTRCPTR retaddr;
@@ -6448,5 +6448,5 @@
             PGMPhysReleasePageMappingLock(pVM, &cacheRec.Lock);
 
-        if (disret && (cpu.pCurInstr->opcode == OP_SYSEXIT || cpu.pCurInstr->opcode == OP_HLT || cpu.pCurInstr->opcode == OP_INT3))
+        if (disret && (cpu.pCurInstr->uOpcode == OP_SYSEXIT || cpu.pCurInstr->uOpcode == OP_HLT || cpu.pCurInstr->uOpcode == OP_INT3))
         {
             disret = patmR3DisInstr(pVM, &pPatch->patch, pNewEip, PATMGCVirtToHCVirt(pVM, &cacheRec, pNewEip), PATMREAD_RAWCODE,
@@ -6455,5 +6455,5 @@
                 PGMPhysReleasePageMappingLock(pVM, &cacheRec.Lock);
 
-            Assert(cpu.pCurInstr->opcode == OP_SYSEXIT || cpu.pCurInstr->opcode == OP_HLT || cpu.pCurInstr->opcode == OP_IRET);
+            Assert(cpu.pCurInstr->uOpcode == OP_SYSEXIT || cpu.pCurInstr->uOpcode == OP_HLT || cpu.pCurInstr->uOpcode == OP_IRET);
         }
 #endif
Index: /trunk/src/VBox/VMM/VMMR3/PATMGuest.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/PATMGuest.cpp	(revision 41736)
+++ /trunk/src/VBox/VMM/VMMR3/PATMGuest.cpp	(revision 41737)
@@ -215,5 +215,5 @@
 
     /** @todo might have to check if the patch crosses a page boundary. Currently not necessary, but that might change in the future!! */
-    switch (pCpu->pCurInstr->opcode)
+    switch (pCpu->pCurInstr->uOpcode)
     {
     case OP_SYSENTER:
@@ -241,5 +241,5 @@
 
     default:
-        AssertMsgFailed(("PATMInstallGuestSpecificPatch: unknown opcode %d\n", pCpu->pCurInstr->opcode));
+        AssertMsgFailed(("PATMInstallGuestSpecificPatch: unknown opcode %d\n", pCpu->pCurInstr->uOpcode));
         return VERR_PATCHING_REFUSED;
     }
Index: /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp	(revision 41736)
+++ /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp	(revision 41737)
@@ -859,5 +859,5 @@
         &&  pPatch->pTempInfo->uPatchRetParam1 == (uint32_t)pCpu->param1.parval) /* nr of bytes popped off the stack should be identical of course! */
     {
-        Assert(pCpu->pCurInstr->opcode == OP_RETN);
+        Assert(pCpu->pCurInstr->uOpcode == OP_RETN);
         STAM_COUNTER_INC(&pVM->patm.s.StatGenRetReused);
 
@@ -1336,5 +1336,5 @@
         /* Modify REG part according to destination of original instruction */
         pPB[offset++] = MAKE_MODRM(0, pCpu->param1.base.reg_gen, 5);
-        if (pCpu->pCurInstr->opcode == OP_STR)
+        if (pCpu->pCurInstr->uOpcode == OP_STR)
         {
             *(RTRCPTR *)&pPB[offset] = pVM->patm.s.pCPUMCtxGC + RT_OFFSETOF(CPUMCTX, tr);
@@ -1381,5 +1381,5 @@
         pPB[offset++] = 0x66;              // mov       ax, CPUMCTX.tr/ldtr
         pPB[offset++] = 0xA1;
-        if (pCpu->pCurInstr->opcode == OP_STR)
+        if (pCpu->pCurInstr->uOpcode == OP_STR)
         {
             *(RTRCPTR *)&pPB[offset] = pVM->patm.s.pCPUMCtxGC + RT_OFFSETOF(CPUMCTX, tr);
@@ -1426,5 +1426,5 @@
     // sidt %Ms
 
-    switch (pCpu->pCurInstr->opcode)
+    switch (pCpu->pCurInstr->uOpcode)
     {
     case OP_SGDT:
Index: /trunk/src/VBox/VMM/VMMRC/IOMRC.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMRC/IOMRC.cpp	(revision 41736)
+++ /trunk/src/VBox/VMM/VMMRC/IOMRC.cpp	(revision 41737)
@@ -67,5 +67,5 @@
 VMMRCDECL(VBOXSTRICTRC) IOMRCIOPortHandler(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu)
 {
-    switch (pCpu->pCurInstr->opcode)
+    switch (pCpu->pCurInstr->uOpcode)
     {
         case OP_IN:
@@ -87,5 +87,5 @@
          */
         default:
-            AssertMsgFailed(("Unknown I/O port access opcode %d.\n", pCpu->pCurInstr->opcode));
+            AssertMsgFailed(("Unknown I/O port access opcode %d.\n", pCpu->pCurInstr->uOpcode));
             return VERR_IOM_IOPORT_UNKNOWN_OPCODE;
     }
Index: /trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp	(revision 41736)
+++ /trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp	(revision 41737)
@@ -521,5 +521,5 @@
          * Note! PATMGCHandleIllegalInstrTrap doesn't always return.
          */
-        if (    Cpu.pCurInstr->opcode == OP_ILLUD2
+        if (    Cpu.pCurInstr->uOpcode == OP_ILLUD2
             &&  PATMIsPatchGCAddr(pVM, pRegFrame->eip))
         {
@@ -544,5 +544,5 @@
         else if (Cpu.fPrefix & DISPREFIX_LOCK)
         {
-            Log(("TRPMGCTrap06Handler: pc=%08x op=%d\n", pRegFrame->eip, Cpu.pCurInstr->opcode));
+            Log(("TRPMGCTrap06Handler: pc=%08x op=%d\n", pRegFrame->eip, Cpu.pCurInstr->uOpcode));
 #ifdef DTRACE_EXPERIMENT /** @todo fix/remove/permanent-enable this when DIS/PATM handles invalid lock sequences. */
             Assert(!PATMIsPatchGCAddr(pVM, pRegFrame->eip));
@@ -556,5 +556,5 @@
          * Handle MONITOR - it causes an #UD exception instead of #GP when not executed in ring 0.
          */
-        else if (Cpu.pCurInstr->opcode == OP_MONITOR)
+        else if (Cpu.pCurInstr->uOpcode == OP_MONITOR)
         {
             LogFlow(("TRPMGCTrap06Handler: -> EMInterpretInstructionCPU\n"));
@@ -732,5 +732,5 @@
      * Try handle it here, if not return to HC and emulate/interpret it there.
      */
-    switch (pCpu->pCurInstr->opcode)
+    switch (pCpu->pCurInstr->uOpcode)
     {
         case OP_INT3:
@@ -830,5 +830,5 @@
     Assert(!pRegFrame->eflags.Bits.u1VM);
 
-    switch (pCpu->pCurInstr->opcode)
+    switch (pCpu->pCurInstr->uOpcode)
     {
         /*
@@ -985,5 +985,5 @@
      * Note: it's no longer safe to access the instruction opcode directly due to possible stale code TLB entries
      */
-    if (Cpu.pCurInstr->opcode == OP_RDTSC)
+    if (Cpu.pCurInstr->uOpcode == OP_RDTSC)
         return trpmGCTrap0dHandlerRdTsc(pVM, pVCpu, pRegFrame);