Index: /trunk/include/VBox/dis.h =================================================================== --- /trunk/include/VBox/dis.h (revision 41727) +++ /trunk/include/VBox/dis.h (revision 41728) @@ -309,47 +309,76 @@ /** @} */ -#define USE_REG_FP0 0 -#define USE_REG_FP1 1 -#define USE_REG_FP2 2 -#define USE_REG_FP3 3 -#define USE_REG_FP4 4 -#define USE_REG_FP5 5 -#define USE_REG_FP6 6 -#define USE_REG_FP7 7 - -#define USE_REG_CR0 0 -#define USE_REG_CR1 1 -#define USE_REG_CR2 2 -#define USE_REG_CR3 3 -#define USE_REG_CR4 4 -#define USE_REG_CR8 8 - -#define USE_REG_DR0 0 -#define USE_REG_DR1 1 -#define USE_REG_DR2 2 -#define USE_REG_DR3 3 -#define USE_REG_DR4 4 -#define USE_REG_DR5 5 -#define USE_REG_DR6 6 -#define USE_REG_DR7 7 - -#define USE_REG_MMX0 0 -#define USE_REG_MMX1 1 -#define USE_REG_MMX2 2 -#define USE_REG_MMX3 3 -#define USE_REG_MMX4 4 -#define USE_REG_MMX5 5 -#define USE_REG_MMX6 6 -#define USE_REG_MMX7 7 - -#define USE_REG_XMM0 0 -#define USE_REG_XMM1 1 -#define USE_REG_XMM2 2 -#define USE_REG_XMM3 3 -#define USE_REG_XMM4 4 -#define USE_REG_XMM5 5 -#define USE_REG_XMM6 6 -#define USE_REG_XMM7 7 -/** @todo missing XMM8-XMM15 */ +/** @name FPU register indexes. + * This matches the AMD64 register encoding. It is found used in + * DISOPPARAM::base.reg_fp. + * @{ + */ +#define DISFPREG_ST0 UINT8_C(0) +#define DISFPREG_ST1 UINT8_C(1) +#define DISFPREG_ST2 UINT8_C(2) +#define DISFPREG_ST3 UINT8_C(3) +#define DISFPREG_ST4 UINT8_C(4) +#define DISFPREG_ST5 UINT8_C(5) +#define DISFPREG_ST6 UINT8_C(6) +#define DISFPREG_ST7 UINT8_C(7) +/** @} */ + +/** @name Control register indexes. + * This matches the AMD64 register encoding. It is found used in + * DISOPPARAM::base.reg_ctrl. + * @{ + */ +#define DISCREG_CR0 UINT8_C(0) +#define DISCREG_CR1 UINT8_C(1) +#define DISCREG_CR2 UINT8_C(2) +#define DISCREG_CR3 UINT8_C(3) +#define DISCREG_CR4 UINT8_C(4) +#define DISCREG_CR8 UINT8_C(8) +/** @} */ + +/** @name Debug register indexes. + * This matches the AMD64 register encoding. It is found used in + * DISOPPARAM::base.reg_dbg. + * @{ + */ +#define DISDREG_DR0 UINT8_C(0) +#define DISDREG_DR1 UINT8_C(1) +#define DISDREG_DR2 UINT8_C(2) +#define DISDREG_DR3 UINT8_C(3) +#define DISDREG_DR4 UINT8_C(4) +#define DISDREG_DR5 UINT8_C(5) +#define DISDREG_DR6 UINT8_C(6) +#define DISDREG_DR7 UINT8_C(7) +/** @} */ + +/** @name MMX register indexes. + * This matches the AMD64 register encoding. It is found used in + * DISOPPARAM::base.reg_mmx. + * @{ + */ +#define DISMREG_MMX0 UINT8_C(0) +#define DISMREG_MMX1 UINT8_C(1) +#define DISMREG_MMX2 UINT8_C(2) +#define DISMREG_MMX3 UINT8_C(3) +#define DISMREG_MMX4 UINT8_C(4) +#define DISMREG_MMX5 UINT8_C(5) +#define DISMREG_MMX6 UINT8_C(6) +#define DISMREG_MMX7 UINT8_C(7) +/** @} */ + +/** @name SSE register indexes. + * This matches the AMD64 register encoding. It is found used in + * DISOPPARAM::base.reg_xmm. + * @{ + */ +#define DISXREG_XMM0 UINT8_C(0) +#define DISXREG_XMM1 UINT8_C(1) +#define DISXREG_XMM2 UINT8_C(2) +#define DISXREG_XMM3 UINT8_C(3) +#define DISXREG_XMM4 UINT8_C(4) +#define DISXREG_XMM5 UINT8_C(5) +#define DISXREG_XMM6 UINT8_C(6) +#define DISXREG_XMM7 UINT8_C(7) +/** @} */ /** Used by DISQueryParamVal & EMIQueryParamVal @@ -424,17 +453,17 @@ /** DISGREG_XXX. */ uint8_t reg_gen; - /** ST(0) - ST(7) */ + /** DISFPREG_XXX */ uint8_t reg_fp; - /** MMX0 - MMX7 */ + /** DISMREG_XXX. */ uint8_t reg_mmx; - /** XMM0 - XMM7 */ + /** DISXREG_XXX. */ uint8_t reg_xmm; - /** {ES, CS, SS, DS, FS, GS} (DISSELREG). */ + /** DISSELREG_XXX. */ uint8_t reg_seg; - /** TR0-TR7 (?) */ + /** TR0-TR7 (no defines for these). */ uint8_t reg_test; - /** CR0-CR4 */ + /** DISCREG_XXX */ uint8_t reg_ctrl; - /** DR0-DR7 */ + /** DISDREG_XXX */ uint8_t reg_dbg; } base; Index: /trunk/src/VBox/Disassembler/DisasmCore.cpp =================================================================== --- /trunk/src/VBox/Disassembler/DisasmCore.cpp (revision 41727) +++ /trunk/src/VBox/Disassembler/DisasmCore.cpp (revision 41728) @@ -743,5 +743,5 @@ { pCpu->prefix &= ~DISPREFIX_LOCK; - pParam->base.reg_ctrl = USE_REG_CR8; + pParam->base.reg_ctrl = DISCREG_CR8; } else Index: /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp (revision 41727) +++ /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp (revision 41728) @@ -5,5 +5,5 @@ /* - * Copyright (C) 2006-2007 Oracle Corporation + * Copyright (C) 2006-2012 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as @@ -1265,5 +1265,5 @@ { uint64_t u64; - int rc = CPUMGetGuestCRx(pVCpu, USE_REG_CR8, &u64); + int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64); if (RT_FAILURE(rc)) u64 = 0; @@ -1348,21 +1348,21 @@ switch (iReg) { - case USE_REG_CR0: + case DISCREG_CR0: *pValue = pVCpu->cpum.s.Guest.cr0; break; - case USE_REG_CR2: + case DISCREG_CR2: *pValue = pVCpu->cpum.s.Guest.cr2; break; - case USE_REG_CR3: + case DISCREG_CR3: *pValue = pVCpu->cpum.s.Guest.cr3; break; - case USE_REG_CR4: + case DISCREG_CR4: *pValue = pVCpu->cpum.s.Guest.cr4; break; - case USE_REG_CR8: + case DISCREG_CR8: { uint8_t u8Tpr; @@ -1423,5 +1423,5 @@ VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue) { - AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER); + AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER); /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */ if (iReg == 4 || iReg == 5) @@ -1970,5 +1970,5 @@ VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value) { - AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER); + AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER); /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */ if (iReg == 4 || iReg == 5) Index: /trunk/src/VBox/VMM/VMMAll/EMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/EMAll.cpp (revision 41727) +++ /trunk/src/VBox/VMM/VMMAll/EMAll.cpp (revision 41728) @@ -2209,5 +2209,5 @@ switch (DestRegCrx) { - case USE_REG_CR0: + case DISCREG_CR0: oldval = CPUMGetGuestCR0(pVCpu); #ifdef IN_RC @@ -2262,9 +2262,9 @@ return rc2 == VINF_SUCCESS ? rc : rc2; - case USE_REG_CR2: + case DISCREG_CR2: rc = CPUMSetGuestCR2(pVCpu, val); AssertRC(rc); return VINF_SUCCESS; - case USE_REG_CR3: + case DISCREG_CR3: /* Reloading the current CR3 means the guest just wants to flush the TLBs */ rc = CPUMSetGuestCR3(pVCpu, val); AssertRC(rc); @@ -2277,5 +2277,5 @@ return rc; - case USE_REG_CR4: + case DISCREG_CR4: oldval = CPUMGetGuestCR4(pVCpu); rc = CPUMSetGuestCR4(pVCpu, val); AssertRC(rc); @@ -2315,10 +2315,10 @@ return rc2 == VINF_SUCCESS ? rc : rc2; - case USE_REG_CR8: + case DISCREG_CR8: return PDMApicSetTPR(pVCpu, val << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */ default: AssertFailed(); - case USE_REG_CR1: /* illegal op */ + case DISCREG_CR1: /* illegal op */ break; } @@ -2377,5 +2377,5 @@ | (u16Data & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)); - return emUpdateCRx(pVM, pVCpu, pRegFrame, USE_REG_CR0, NewCr0); + return emUpdateCRx(pVM, pVCpu, pRegFrame, DISCREG_CR0, NewCr0); } Index: /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (revision 41727) +++ /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (revision 41728) @@ -4169,5 +4169,5 @@ Assert( !pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) - || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3); + || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != DISCREG_CR3); /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */ Index: /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp (revision 41727) +++ /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp (revision 41728) @@ -994,5 +994,5 @@ //read Assert(Cpu.param2.fUse & DISUSE_REG_CR); - Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4); + Assert(Cpu.param2.base.reg_ctrl <= DISCREG_CR4); STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]); } @@ -1001,5 +1001,5 @@ //write Assert(Cpu.param1.fUse & DISUSE_REG_CR); - Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4); + Assert(Cpu.param1.base.reg_ctrl <= DISCREG_CR4); STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]); } Index: /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp (revision 41727) +++ /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp (revision 41728) @@ -1151,5 +1151,5 @@ { int rc = VINF_SUCCESS; - int reg, mod, rm, dbgreg; + unsigned reg, mod, rm, dbgreg; uint32_t offset; @@ -1183,5 +1183,5 @@ pPB[1] = MAKE_MODRM(mod, reg, rm); - AssertReturn(dbgreg <= USE_REG_DR7, VERR_INVALID_PARAMETER); + AssertReturn(dbgreg <= DISDREG_DR7, VERR_INVALID_PARAMETER); offset = RT_OFFSETOF(CPUMCTX, dr[dbgreg]); @@ -1235,14 +1235,14 @@ switch (ctrlreg) { - case USE_REG_CR0: + case DISCREG_CR0: offset = RT_OFFSETOF(CPUMCTX, cr0); break; - case USE_REG_CR2: + case DISCREG_CR2: offset = RT_OFFSETOF(CPUMCTX, cr2); break; - case USE_REG_CR3: + case DISCREG_CR3: offset = RT_OFFSETOF(CPUMCTX, cr3); break; - case USE_REG_CR4: + case DISCREG_CR4: offset = RT_OFFSETOF(CPUMCTX, cr4); break; Index: /trunk/src/VBox/VMM/include/EMInternal.h =================================================================== --- /trunk/src/VBox/VMM/include/EMInternal.h (revision 41727) +++ /trunk/src/VBox/VMM/include/EMInternal.h (revision 41728) @@ -272,6 +272,6 @@ STAMCOUNTER StatInvlpg; STAMCOUNTER StatHlt; - STAMCOUNTER StatMovReadCR[USE_REG_CR4 + 1]; - STAMCOUNTER StatMovWriteCR[USE_REG_CR4 + 1]; + STAMCOUNTER StatMovReadCR[DISCREG_CR4 + 1]; + STAMCOUNTER StatMovWriteCR[DISCREG_CR4 + 1]; STAMCOUNTER StatMovDRx; STAMCOUNTER StatIret;