Index: /trunk/include/VBox/dis.h =================================================================== --- /trunk/include/VBox/dis.h (revision 41726) +++ /trunk/include/VBox/dis.h (revision 41727) @@ -192,107 +192,119 @@ /** @} */ -/** index in {"RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"} - * @{ - */ -#define USE_REG_RAX 0 -#define USE_REG_RCX 1 -#define USE_REG_RDX 2 -#define USE_REG_RBX 3 -#define USE_REG_RSP 4 -#define USE_REG_RBP 5 -#define USE_REG_RSI 6 -#define USE_REG_RDI 7 -#define USE_REG_R8 8 -#define USE_REG_R9 9 -#define USE_REG_R10 10 -#define USE_REG_R11 11 -#define USE_REG_R12 12 -#define USE_REG_R13 13 -#define USE_REG_R14 14 -#define USE_REG_R15 15 -/** @} */ - -/** index in {"EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI", "R8D", "R9D", "R10D", "R11D", "R12D", "R13D", "R14D", "R15D"} - * @{ - */ -#define USE_REG_EAX 0 -#define USE_REG_ECX 1 -#define USE_REG_EDX 2 -#define USE_REG_EBX 3 -#define USE_REG_ESP 4 -#define USE_REG_EBP 5 -#define USE_REG_ESI 6 -#define USE_REG_EDI 7 -#define USE_REG_R8D 8 -#define USE_REG_R9D 9 -#define USE_REG_R10D 10 -#define USE_REG_R11D 11 -#define USE_REG_R12D 12 -#define USE_REG_R13D 13 -#define USE_REG_R14D 14 -#define USE_REG_R15D 15 -/** @} */ - -/** index in {"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI", "R8W", "R9W", "R10W", "R11W", "R12W", "R13W", "R14W", "R15W"} - * @{ - */ -#define USE_REG_AX 0 -#define USE_REG_CX 1 -#define USE_REG_DX 2 -#define USE_REG_BX 3 -#define USE_REG_SP 4 -#define USE_REG_BP 5 -#define USE_REG_SI 6 -#define USE_REG_DI 7 -#define USE_REG_R8W 8 -#define USE_REG_R9W 9 -#define USE_REG_R10W 10 -#define USE_REG_R11W 11 -#define USE_REG_R12W 12 -#define USE_REG_R13W 13 -#define USE_REG_R14W 14 -#define USE_REG_R15W 15 -/** @} */ - -/** index in {"AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH", "R8B", "R9B", "R10B", "R11B", "R12B", "R13B", "R14B", "R15B", "SPL", "BPL", "SIL", "DIL"} - * @{ - */ -#define USE_REG_AL 0 -#define USE_REG_CL 1 -#define USE_REG_DL 2 -#define USE_REG_BL 3 -#define USE_REG_AH 4 -#define USE_REG_CH 5 -#define USE_REG_DH 6 -#define USE_REG_BH 7 -#define USE_REG_R8B 8 -#define USE_REG_R9B 9 -#define USE_REG_R10B 10 -#define USE_REG_R11B 11 -#define USE_REG_R12B 12 -#define USE_REG_R13B 13 -#define USE_REG_R14B 14 -#define USE_REG_R15B 15 -#define USE_REG_SPL 16 -#define USE_REG_BPL 17 -#define USE_REG_SIL 18 -#define USE_REG_DIL 19 - -/** @} */ - -/** index in {ES, CS, SS, DS, FS, GS} +/** @name 64-bit general register indexes. + * This matches the AMD64 register encoding. It is found used in + * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen. + * @note Safe to assume same values as the 16-bit and 32-bit general registers. + * @{ + */ +#define DISGREG_RAX UINT8_C(0) +#define DISGREG_RCX UINT8_C(1) +#define DISGREG_RDX UINT8_C(2) +#define DISGREG_RBX UINT8_C(3) +#define DISGREG_RSP UINT8_C(4) +#define DISGREG_RBP UINT8_C(5) +#define DISGREG_RSI UINT8_C(6) +#define DISGREG_RDI UINT8_C(7) +#define DISGREG_R8 UINT8_C(8) +#define DISGREG_R9 UINT8_C(9) +#define DISGREG_R10 UINT8_C(10) +#define DISGREG_R11 UINT8_C(11) +#define DISGREG_R12 UINT8_C(12) +#define DISGREG_R13 UINT8_C(13) +#define DISGREG_R14 UINT8_C(14) +#define DISGREG_R15 UINT8_C(15) +/** @} */ + +/** @name 32-bit general register indexes. + * This matches the AMD64 register encoding. It is found used in + * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen. + * @note Safe to assume same values as the 16-bit and 64-bit general registers. + * @{ + */ +#define DISGREG_EAX UINT8_C(0) +#define DISGREG_ECX UINT8_C(1) +#define DISGREG_EDX UINT8_C(2) +#define DISGREG_EBX UINT8_C(3) +#define DISGREG_ESP UINT8_C(4) +#define DISGREG_EBP UINT8_C(5) +#define DISGREG_ESI UINT8_C(6) +#define DISGREG_EDI UINT8_C(7) +#define DISGREG_R8D UINT8_C(8) +#define DISGREG_R9D UINT8_C(9) +#define DISGREG_R10D UINT8_C(10) +#define DISGREG_R11D UINT8_C(11) +#define DISGREG_R12D UINT8_C(12) +#define DISGREG_R13D UINT8_C(13) +#define DISGREG_R14D UINT8_C(14) +#define DISGREG_R15D UINT8_C(15) +/** @} */ + +/** @name 16-bit general register indexes. + * This matches the AMD64 register encoding. It is found used in + * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen. + * @note Safe to assume same values as the 32-bit and 64-bit general registers. + * @{ + */ +#define DISGREG_AX UINT8_C(0) +#define DISGREG_CX UINT8_C(1) +#define DISGREG_DX UINT8_C(2) +#define DISGREG_BX UINT8_C(3) +#define DISGREG_SP UINT8_C(4) +#define DISGREG_BP UINT8_C(5) +#define DISGREG_SI UINT8_C(6) +#define DISGREG_DI UINT8_C(7) +#define DISGREG_R8W UINT8_C(8) +#define DISGREG_R9W UINT8_C(9) +#define DISGREG_R10W UINT8_C(10) +#define DISGREG_R11W UINT8_C(11) +#define DISGREG_R12W UINT8_C(12) +#define DISGREG_R13W UINT8_C(13) +#define DISGREG_R14W UINT8_C(14) +#define DISGREG_R15W UINT8_C(15) +/** @} */ + +/** @name 8-bit general register indexes. + * This mostly (?) matches the AMD64 register encoding. It is found used in + * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen. + * @{ + */ +#define DISGREG_AL UINT8_C(0) +#define DISGREG_CL UINT8_C(1) +#define DISGREG_DL UINT8_C(2) +#define DISGREG_BL UINT8_C(3) +#define DISGREG_AH UINT8_C(4) +#define DISGREG_CH UINT8_C(5) +#define DISGREG_DH UINT8_C(6) +#define DISGREG_BH UINT8_C(7) +#define DISGREG_R8B UINT8_C(8) +#define DISGREG_R9B UINT8_C(9) +#define DISGREG_R10B UINT8_C(10) +#define DISGREG_R11B UINT8_C(11) +#define DISGREG_R12B UINT8_C(12) +#define DISGREG_R13B UINT8_C(13) +#define DISGREG_R14B UINT8_C(14) +#define DISGREG_R15B UINT8_C(15) +#define DISGREG_SPL UINT8_C(16) +#define DISGREG_BPL UINT8_C(17) +#define DISGREG_SIL UINT8_C(18) +#define DISGREG_DIL UINT8_C(19) +/** @} */ + +/** @name Segment registerindexes. + * This matches the AMD64 register encoding. It is found used in + * DISOPPARAM::base.reg_seg. * @{ */ typedef enum { - DIS_SELREG_ES = 0, - DIS_SELREG_CS = 1, - DIS_SELREG_SS = 2, - DIS_SELREG_DS = 3, - DIS_SELREG_FS = 4, - DIS_SELREG_GS = 5, + DISSELREG_ES = 0, + DISSELREG_CS = 1, + DISSELREG_SS = 2, + DISSELREG_DS = 3, + DISSELREG_FS = 4, + DISSELREG_GS = 5, /** The usual 32-bit paranoia. */ DIS_SEGREG_32BIT_HACK = 0x7fffffff -} DIS_SELREG; +} DISSELREG; /** @} */ @@ -410,4 +422,5 @@ union { + /** DISGREG_XXX. */ uint8_t reg_gen; /** ST(0) - ST(7) */ @@ -417,5 +430,5 @@ /** XMM0 - XMM7 */ uint8_t reg_xmm; - /** {ES, CS, SS, DS, FS, GS} (DIS_SELREG). */ + /** {ES, CS, SS, DS, FS, GS} (DISSELREG). */ uint8_t reg_seg; /** TR0-TR7 (?) */ @@ -428,4 +441,5 @@ union { + /** DISGREG_XXX. */ uint8_t reg_gen; } index; @@ -476,5 +490,5 @@ /* off: 0x060 (96) */ - /** ModRM fields. */ + /** ModRM fields. */ union { @@ -502,9 +516,9 @@ unsigned u; } SIB; - int32_t i32SibDisp; + int32_t i32SibDisp; /* off: 0x06c (108) */ /** The CPU mode (DISCPUMODE). */ - uint8_t mode; + uint8_t mode; /** The addressing mode (DISCPUMODE). */ uint8_t addrmode; @@ -512,9 +526,9 @@ uint8_t opmode; /** Per instruction prefix settings. */ - uint8_t prefix; + uint8_t prefix; /* off: 0x070 (112) */ /** REX prefix value (64 bits only). */ - uint8_t prefix_rex; - /** Segment prefix value (DIS_SELREG). */ + uint8_t prefix_rex; + /** Segment prefix value (DISSELREG). */ uint8_t idxSegPrefix; /** Last prefix byte (for SSE2 extension tables). */ @@ -524,5 +538,5 @@ /* off: 0x074 (116) */ /** The size of the prefix bytes. */ - uint8_t cbPrefix; + uint8_t cbPrefix; /** The instruction size. */ uint8_t opsize; @@ -567,7 +581,7 @@ -/** - * Opcode descriptor. - */ +/** + * Opcode descriptor. + */ typedef struct DISOPCODE { @@ -603,5 +617,5 @@ DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, PDISOPPARAM pParam); -DISDECL(DIS_SELREG) DISDetectSegReg(PDISCPUSTATE pCpu, PDISOPPARAM pParam); +DISDECL(DISSELREG) DISDetectSegReg(PDISCPUSTATE pCpu, PDISOPPARAM pParam); DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu); @@ -613,11 +627,11 @@ DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal); DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal); -DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal); -DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal, PCPUMSELREGHID *ppSelHidReg); +DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal); +DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal, PCPUMSELREGHID *ppSelHidReg); DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8); DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16); DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32); DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64); -DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL val); +DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DISSELREG sel, RTSEL val); DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg); DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg); Index: /trunk/include/VBox/vmm/selm.h =================================================================== --- /trunk/include/VBox/vmm/selm.h (revision 41726) +++ /trunk/include/VBox/vmm/selm.h (revision 41727) @@ -50,5 +50,5 @@ VMMDECL(RTRCPTR) SELMGetHyperGDT(PVM pVM); VMMDECL(int) SELMGetTSSInfo(PVM pVM, PVMCPU pVCpu, PRTGCUINTPTR pGCPtrTss, PRTGCUINTPTR pcbTss, bool *pfCanHaveIOBitmap); -VMMDECL(RTGCPTR) SELMToFlat(PVM pVM, DIS_SELREG SelReg, PCPUMCTXCORE pCtxCore, RTGCPTR Addr); +VMMDECL(RTGCPTR) SELMToFlat(PVM pVM, DISSELREG SelReg, PCPUMCTXCORE pCtxCore, RTGCPTR Addr); VMMDECL(RTGCPTR) SELMToFlatBySel(PVM pVM, RTSEL Sel, RTGCPTR Addr); VMMDECL(void) SELMShadowCR3Changed(PVM pVM, PVMCPU pVCpu); @@ -74,5 +74,5 @@ /** @} */ -VMMDECL(int) SELMToFlatEx(PVMCPU pVCpu, DIS_SELREG SelReg, PCCPUMCTXCORE pCtxCore, RTGCPTR Addr, unsigned fFlags, PRTGCPTR ppvGC); +VMMDECL(int) SELMToFlatEx(PVMCPU pVCpu, DISSELREG SelReg, PCCPUMCTXCORE pCtxCore, RTGCPTR Addr, unsigned fFlags, PRTGCPTR ppvGC); VMMDECL(int) SELMToFlatBySelEx(PVMCPU pVCpu, X86EFLAGS eflags, RTSEL Sel, RTGCPTR Addr, PCCPUMSELREGHID pHiddenSel, uint32_t fFlags, PRTGCPTR ppvGC, uint32_t *pcb); Index: /trunk/src/VBox/Disassembler/DisasmCore.cpp =================================================================== --- /trunk/src/VBox/Disassembler/DisasmCore.cpp (revision 41726) +++ /trunk/src/VBox/Disassembler/DisasmCore.cpp (revision 41727) @@ -306,5 +306,5 @@ } pCpu->prefix = DISPREFIX_NONE; - pCpu->idxSegPrefix = DIS_SELREG_DS; + pCpu->idxSegPrefix = DISSELREG_DS; pCpu->uInstrAddr = uInstrAddr; pCpu->pfnDisasmFnTable = g_apfnFullDisasm; @@ -359,8 +359,8 @@ // segment override prefix byte case OP_SEG: - pCpu->idxSegPrefix = (DIS_SELREG)(paOneByteMap[codebyte].param1 - OP_PARM_REG_SEG_START); + pCpu->idxSegPrefix = (DISSELREG)(paOneByteMap[codebyte].param1 - OP_PARM_REG_SEG_START); /* Segment prefixes for CS, DS, ES and SS are ignored in long mode. */ if ( pCpu->mode != DISCPUMODE_64BIT - || pCpu->idxSegPrefix >= DIS_SELREG_FS) + || pCpu->idxSegPrefix >= DISSELREG_FS) { pCpu->prefix |= DISPREFIX_SEG; @@ -1591,5 +1591,5 @@ { /* Segment ES..GS registers. */ - pParam->base.reg_seg = (DIS_SELREG)(pParam->param - OP_PARM_REG_SEG_START); + pParam->base.reg_seg = (DISSELREG)(pParam->param - OP_PARM_REG_SEG_START); pParam->fUse |= DISUSE_REG_SEG; pParam->cb = 2; @@ -1643,5 +1643,5 @@ if (pCpu->addrmode == DISCPUMODE_32BIT) { - pParam->base.reg_gen = USE_REG_ESI; + pParam->base.reg_gen = DISGREG_ESI; pParam->fUse |= DISUSE_REG_GEN32; } @@ -1649,10 +1649,10 @@ if (pCpu->addrmode == DISCPUMODE_64BIT) { - pParam->base.reg_gen = USE_REG_RSI; + pParam->base.reg_gen = DISGREG_RSI; pParam->fUse |= DISUSE_REG_GEN64; } else { - pParam->base.reg_gen = USE_REG_SI; + pParam->base.reg_gen = DISGREG_SI; pParam->fUse |= DISUSE_REG_GEN16; } @@ -1668,5 +1668,5 @@ if (pCpu->addrmode == DISCPUMODE_32BIT) { - pParam->base.reg_gen = USE_REG_ESI; + pParam->base.reg_gen = DISGREG_ESI; pParam->fUse |= DISUSE_REG_GEN32; } @@ -1674,10 +1674,10 @@ if (pCpu->addrmode == DISCPUMODE_64BIT) { - pParam->base.reg_gen = USE_REG_RSI; + pParam->base.reg_gen = DISGREG_RSI; pParam->fUse |= DISUSE_REG_GEN64; } else { - pParam->base.reg_gen = USE_REG_SI; + pParam->base.reg_gen = DISGREG_SI; pParam->fUse |= DISUSE_REG_GEN16; } @@ -1693,5 +1693,5 @@ if (pCpu->addrmode == DISCPUMODE_32BIT) { - pParam->base.reg_gen = USE_REG_EDI; + pParam->base.reg_gen = DISGREG_EDI; pParam->fUse |= DISUSE_REG_GEN32; } @@ -1699,10 +1699,10 @@ if (pCpu->addrmode == DISCPUMODE_64BIT) { - pParam->base.reg_gen = USE_REG_RDI; + pParam->base.reg_gen = DISGREG_RDI; pParam->fUse |= DISUSE_REG_GEN64; } else { - pParam->base.reg_gen = USE_REG_DI; + pParam->base.reg_gen = DISGREG_DI; pParam->fUse |= DISUSE_REG_GEN16; } @@ -1718,5 +1718,5 @@ if (pCpu->addrmode == DISCPUMODE_32BIT) { - pParam->base.reg_gen = USE_REG_EDI; + pParam->base.reg_gen = DISGREG_EDI; pParam->fUse |= DISUSE_REG_GEN32; } @@ -1724,10 +1724,10 @@ if (pCpu->addrmode == DISCPUMODE_64BIT) { - pParam->base.reg_gen = USE_REG_RDI; + pParam->base.reg_gen = DISGREG_RDI; pParam->fUse |= DISUSE_REG_GEN64; } else { - pParam->base.reg_gen = USE_REG_DI; + pParam->base.reg_gen = DISGREG_DI; pParam->fUse |= DISUSE_REG_GEN16; } @@ -2294,6 +2294,6 @@ #endif static const char *szModRMSegReg[6] = {"ES", "CS", "SS", "DS", "FS", "GS"}; -static const int BaseModRMReg16[8] = { USE_REG_BX, USE_REG_BX, USE_REG_BP, USE_REG_BP, USE_REG_SI, USE_REG_DI, USE_REG_BP, USE_REG_BX}; -static const int IndexModRMReg16[4] = { USE_REG_SI, USE_REG_DI, USE_REG_SI, USE_REG_DI}; +static const int BaseModRMReg16[8] = { DISGREG_BX, DISGREG_BX, DISGREG_BP, DISGREG_BP, DISGREG_SI, DISGREG_DI, DISGREG_BP, DISGREG_BX}; +static const int IndexModRMReg16[4] = { DISGREG_SI, DISGREG_DI, DISGREG_SI, DISGREG_DI}; //***************************************************************************** static void disasmModRMReg(PDISCPUSTATE pCpu, PCDISOPCODE pOp, unsigned idx, PDISOPPARAM pParam, int fRegAddr) @@ -2336,8 +2336,8 @@ /* Intel® 64 and IA-32 Architectures Software Developer’s Manual: 3.4.1.1 */ if ( (pCpu->prefix & DISPREFIX_REX) - && idx >= USE_REG_AH - && idx <= USE_REG_BH) + && idx >= DISGREG_AH + && idx <= DISGREG_BH) { - idx += (USE_REG_SPL - USE_REG_AH); + idx += (DISGREG_SPL - DISGREG_AH); } @@ -2397,5 +2397,5 @@ pParam->fUse |= DISUSE_REG_SEG; - pParam->base.reg_seg = (DIS_SELREG)idx; + pParam->base.reg_seg = (DISSELREG)idx; } Index: /trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp =================================================================== --- /trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp (revision 41726) +++ /trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp (revision 41727) @@ -917,5 +917,5 @@ if (pfnGetSymbol) { - int rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), uTrgAddr, szSymbol, sizeof(szSymbol), &off, pvUser); + int rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, szSymbol, sizeof(szSymbol), &off, pvUser); if (RT_SUCCESS(rc)) { @@ -968,15 +968,15 @@ PUT_NUM_16(pParam->parval); if (pfnGetSymbol) - rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser); + rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser); break; case DISUSE_DISPLACEMENT32: PUT_NUM_32(pParam->parval); if (pfnGetSymbol) - rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser); + rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser); break; case DISUSE_DISPLACEMENT64: PUT_NUM_64(pParam->parval); if (pfnGetSymbol) - rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), (uint64_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser); + rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint64_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser); break; default: @@ -1032,15 +1032,15 @@ PUT_NUM_16(pParam->uDisp.i16); if (pfnGetSymbol) - rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), pParam->uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser); + rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser); break; case DISUSE_DISPLACEMENT32: PUT_NUM_32(pParam->uDisp.i32); if (pfnGetSymbol) - rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), pParam->uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser); + rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser); break; case DISUSE_DISPLACEMENT64: PUT_NUM_64(pParam->uDisp.i64); if (pfnGetSymbol) - rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), pParam->uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser); + rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser); break; default: Index: /trunk/src/VBox/Disassembler/DisasmReg.cpp =================================================================== --- /trunk/src/VBox/Disassembler/DisasmReg.cpp (revision 41726) +++ /trunk/src/VBox/Disassembler/DisasmReg.cpp (revision 41727) @@ -42,20 +42,20 @@ static const unsigned g_aReg64Index[] = { - RT_OFFSETOF(CPUMCTXCORE, rax), /* USE_REG_RAX */ - RT_OFFSETOF(CPUMCTXCORE, rcx), /* USE_REG_RCX */ - RT_OFFSETOF(CPUMCTXCORE, rdx), /* USE_REG_RDX */ - RT_OFFSETOF(CPUMCTXCORE, rbx), /* USE_REG_RBX */ - RT_OFFSETOF(CPUMCTXCORE, rsp), /* USE_REG_RSP */ - RT_OFFSETOF(CPUMCTXCORE, rbp), /* USE_REG_RBP */ - RT_OFFSETOF(CPUMCTXCORE, rsi), /* USE_REG_RSI */ - RT_OFFSETOF(CPUMCTXCORE, rdi), /* USE_REG_RDI */ - RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8 */ - RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9 */ - RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10 */ - RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11 */ - RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12 */ - RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13 */ - RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14 */ - RT_OFFSETOF(CPUMCTXCORE, r15) /* USE_REG_R15 */ + RT_OFFSETOF(CPUMCTXCORE, rax), /* DISGREG_RAX */ + RT_OFFSETOF(CPUMCTXCORE, rcx), /* DISGREG_RCX */ + RT_OFFSETOF(CPUMCTXCORE, rdx), /* DISGREG_RDX */ + RT_OFFSETOF(CPUMCTXCORE, rbx), /* DISGREG_RBX */ + RT_OFFSETOF(CPUMCTXCORE, rsp), /* DISGREG_RSP */ + RT_OFFSETOF(CPUMCTXCORE, rbp), /* DISGREG_RBP */ + RT_OFFSETOF(CPUMCTXCORE, rsi), /* DISGREG_RSI */ + RT_OFFSETOF(CPUMCTXCORE, rdi), /* DISGREG_RDI */ + RT_OFFSETOF(CPUMCTXCORE, r8), /* DISGREG_R8 */ + RT_OFFSETOF(CPUMCTXCORE, r9), /* DISGREG_R9 */ + RT_OFFSETOF(CPUMCTXCORE, r10), /* DISGREG_R10 */ + RT_OFFSETOF(CPUMCTXCORE, r11), /* DISGREG_R11 */ + RT_OFFSETOF(CPUMCTXCORE, r12), /* DISGREG_R12 */ + RT_OFFSETOF(CPUMCTXCORE, r13), /* DISGREG_R13 */ + RT_OFFSETOF(CPUMCTXCORE, r14), /* DISGREG_R14 */ + RT_OFFSETOF(CPUMCTXCORE, r15) /* DISGREG_R15 */ }; @@ -73,20 +73,20 @@ static const unsigned g_aReg32Index[] = { - RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_EAX */ - RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_ECX */ - RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_EDX */ - RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_EBX */ - RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_ESP */ - RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_EBP */ - RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_ESI */ - RT_OFFSETOF(CPUMCTXCORE, edi), /* USE_REG_EDI */ - RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8D */ - RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9D */ - RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10D */ - RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11D */ - RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12D */ - RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13D */ - RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14D */ - RT_OFFSETOF(CPUMCTXCORE, r15) /* USE_REG_R15D */ + RT_OFFSETOF(CPUMCTXCORE, eax), /* DISGREG_EAX */ + RT_OFFSETOF(CPUMCTXCORE, ecx), /* DISGREG_ECX */ + RT_OFFSETOF(CPUMCTXCORE, edx), /* DISGREG_EDX */ + RT_OFFSETOF(CPUMCTXCORE, ebx), /* DISGREG_EBX */ + RT_OFFSETOF(CPUMCTXCORE, esp), /* DISGREG_ESP */ + RT_OFFSETOF(CPUMCTXCORE, ebp), /* DISGREG_EBP */ + RT_OFFSETOF(CPUMCTXCORE, esi), /* DISGREG_ESI */ + RT_OFFSETOF(CPUMCTXCORE, edi), /* DISGREG_EDI */ + RT_OFFSETOF(CPUMCTXCORE, r8), /* DISGREG_R8D */ + RT_OFFSETOF(CPUMCTXCORE, r9), /* DISGREG_R9D */ + RT_OFFSETOF(CPUMCTXCORE, r10), /* DISGREG_R1D */ + RT_OFFSETOF(CPUMCTXCORE, r11), /* DISGREG_R11D */ + RT_OFFSETOF(CPUMCTXCORE, r12), /* DISGREG_R12D */ + RT_OFFSETOF(CPUMCTXCORE, r13), /* DISGREG_R13D */ + RT_OFFSETOF(CPUMCTXCORE, r14), /* DISGREG_R14D */ + RT_OFFSETOF(CPUMCTXCORE, r15) /* DISGREG_R15D */ }; @@ -109,20 +109,20 @@ static const unsigned g_aReg16Index[] = { - RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_AX */ - RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_CX */ - RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_DX */ - RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_BX */ - RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_SP */ - RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_BP */ - RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_SI */ - RT_OFFSETOF(CPUMCTXCORE, edi), /* USE_REG_DI */ - RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8W */ - RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9W */ - RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10W */ - RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11W */ - RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12W */ - RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13W */ - RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14W */ - RT_OFFSETOF(CPUMCTXCORE, r15) /* USE_REG_R15W */ + RT_OFFSETOF(CPUMCTXCORE, eax), /* DISGREG_AX */ + RT_OFFSETOF(CPUMCTXCORE, ecx), /* DISGREG_CX */ + RT_OFFSETOF(CPUMCTXCORE, edx), /* DISGREG_DX */ + RT_OFFSETOF(CPUMCTXCORE, ebx), /* DISGREG_BX */ + RT_OFFSETOF(CPUMCTXCORE, esp), /* DISGREG_SP */ + RT_OFFSETOF(CPUMCTXCORE, ebp), /* DISGREG_BP */ + RT_OFFSETOF(CPUMCTXCORE, esi), /* DISGREG_SI */ + RT_OFFSETOF(CPUMCTXCORE, edi), /* DISGREG_DI */ + RT_OFFSETOF(CPUMCTXCORE, r8), /* DISGREG_R8W */ + RT_OFFSETOF(CPUMCTXCORE, r9), /* DISGREG_R9W */ + RT_OFFSETOF(CPUMCTXCORE, r10), /* DISGREG_R10W */ + RT_OFFSETOF(CPUMCTXCORE, r11), /* DISGREG_R11W */ + RT_OFFSETOF(CPUMCTXCORE, r12), /* DISGREG_R12W */ + RT_OFFSETOF(CPUMCTXCORE, r13), /* DISGREG_R13W */ + RT_OFFSETOF(CPUMCTXCORE, r14), /* DISGREG_R14W */ + RT_OFFSETOF(CPUMCTXCORE, r15) /* DISGREG_R15W */ }; @@ -140,24 +140,24 @@ static const unsigned g_aReg8Index[] = { - RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_AL */ - RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_CL */ - RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_DL */ - RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_BL */ - RT_OFFSETOF_ADD(CPUMCTXCORE, eax, 1), /* USE_REG_AH */ - RT_OFFSETOF_ADD(CPUMCTXCORE, ecx, 1), /* USE_REG_CH */ - RT_OFFSETOF_ADD(CPUMCTXCORE, edx, 1), /* USE_REG_DH */ - RT_OFFSETOF_ADD(CPUMCTXCORE, ebx, 1), /* USE_REG_BH */ - RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8B */ - RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9B */ - RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10B*/ - RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11B */ - RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12B */ - RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13B */ - RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14B */ - RT_OFFSETOF(CPUMCTXCORE, r15), /* USE_REG_R15B */ - RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_SPL; with REX prefix only */ - RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_BPL; with REX prefix only */ - RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_SIL; with REX prefix only */ - RT_OFFSETOF(CPUMCTXCORE, edi) /* USE_REG_DIL; with REX prefix only */ + RT_OFFSETOF(CPUMCTXCORE, eax), /* DISGREG_AL */ + RT_OFFSETOF(CPUMCTXCORE, ecx), /* DISGREG_CL */ + RT_OFFSETOF(CPUMCTXCORE, edx), /* DISGREG_DL */ + RT_OFFSETOF(CPUMCTXCORE, ebx), /* DISGREG_BL */ + RT_OFFSETOF_ADD(CPUMCTXCORE, eax, 1), /* DISGREG_AH */ + RT_OFFSETOF_ADD(CPUMCTXCORE, ecx, 1), /* DISGREG_CH */ + RT_OFFSETOF_ADD(CPUMCTXCORE, edx, 1), /* DISGREG_DH */ + RT_OFFSETOF_ADD(CPUMCTXCORE, ebx, 1), /* DISGREG_BH */ + RT_OFFSETOF(CPUMCTXCORE, r8), /* DISGREG_R8B */ + RT_OFFSETOF(CPUMCTXCORE, r9), /* DISGREG_R9B */ + RT_OFFSETOF(CPUMCTXCORE, r10), /* DISGREG_R10B*/ + RT_OFFSETOF(CPUMCTXCORE, r11), /* DISGREG_R11B */ + RT_OFFSETOF(CPUMCTXCORE, r12), /* DISGREG_R12B */ + RT_OFFSETOF(CPUMCTXCORE, r13), /* DISGREG_R13B */ + RT_OFFSETOF(CPUMCTXCORE, r14), /* DISGREG_R14B */ + RT_OFFSETOF(CPUMCTXCORE, r15), /* DISGREG_R15B */ + RT_OFFSETOF(CPUMCTXCORE, esp), /* DISGREG_SPL; with REX prefix only */ + RT_OFFSETOF(CPUMCTXCORE, ebp), /* DISGREG_BPL; with REX prefix only */ + RT_OFFSETOF(CPUMCTXCORE, esi), /* DISGREG_SIL; with REX prefix only */ + RT_OFFSETOF(CPUMCTXCORE, edi) /* DISGREG_DIL; with REX prefix only */ }; @@ -175,20 +175,20 @@ static const unsigned g_aRegSegIndex[] = { - RT_OFFSETOF(CPUMCTXCORE, es), /* DIS_SELREG_ES */ - RT_OFFSETOF(CPUMCTXCORE, cs), /* DIS_SELREG_CS */ - RT_OFFSETOF(CPUMCTXCORE, ss), /* DIS_SELREG_SS */ - RT_OFFSETOF(CPUMCTXCORE, ds), /* DIS_SELREG_DS */ - RT_OFFSETOF(CPUMCTXCORE, fs), /* DIS_SELREG_FS */ - RT_OFFSETOF(CPUMCTXCORE, gs) /* DIS_SELREG_GS */ + RT_OFFSETOF(CPUMCTXCORE, es), /* DISSELREG_ES */ + RT_OFFSETOF(CPUMCTXCORE, cs), /* DISSELREG_CS */ + RT_OFFSETOF(CPUMCTXCORE, ss), /* DISSELREG_SS */ + RT_OFFSETOF(CPUMCTXCORE, ds), /* DISSELREG_DS */ + RT_OFFSETOF(CPUMCTXCORE, fs), /* DISSELREG_FS */ + RT_OFFSETOF(CPUMCTXCORE, gs) /* DISSELREG_GS */ }; static const unsigned g_aRegHidSegIndex[] = { - RT_OFFSETOF(CPUMCTXCORE, esHid), /* DIS_SELREG_ES */ - RT_OFFSETOF(CPUMCTXCORE, csHid), /* DIS_SELREG_CS */ - RT_OFFSETOF(CPUMCTXCORE, ssHid), /* DIS_SELREG_SS */ - RT_OFFSETOF(CPUMCTXCORE, dsHid), /* DIS_SELREG_DS */ - RT_OFFSETOF(CPUMCTXCORE, fsHid), /* DIS_SELREG_FS */ - RT_OFFSETOF(CPUMCTXCORE, gsHid) /* DIS_SELREG_GS */ + RT_OFFSETOF(CPUMCTXCORE, esHid), /* DISSELREG_ES */ + RT_OFFSETOF(CPUMCTXCORE, csHid), /* DISSELREG_CS */ + RT_OFFSETOF(CPUMCTXCORE, ssHid), /* DISSELREG_SS */ + RT_OFFSETOF(CPUMCTXCORE, dsHid), /* DISSELREG_DS */ + RT_OFFSETOF(CPUMCTXCORE, fsHid), /* DISSELREG_FS */ + RT_OFFSETOF(CPUMCTXCORE, gsHid) /* DISSELREG_GS */ }; @@ -257,22 +257,22 @@ //***************************************************************************** //***************************************************************************** -DISDECL(DIS_SELREG) DISDetectSegReg(PDISCPUSTATE pCpu, PDISOPPARAM pParam) +DISDECL(DISSELREG) DISDetectSegReg(PDISCPUSTATE pCpu, PDISOPPARAM pParam) { if (pCpu->prefix & DISPREFIX_SEG) /* Use specified SEG: prefix. */ - return (DIS_SELREG)pCpu->idxSegPrefix; + return (DISSELREG)pCpu->idxSegPrefix; /* Guess segment register by parameter type. */ if (pParam->fUse & (DISUSE_REG_GEN32|DISUSE_REG_GEN64|DISUSE_REG_GEN16)) { - AssertCompile(USE_REG_ESP == USE_REG_RSP); - AssertCompile(USE_REG_EBP == USE_REG_RBP); - AssertCompile(USE_REG_ESP == USE_REG_SP); - AssertCompile(USE_REG_EBP == USE_REG_BP); - if (pParam->base.reg_gen == USE_REG_ESP || pParam->base.reg_gen == USE_REG_EBP) - return DIS_SELREG_SS; + AssertCompile(DISGREG_ESP == DISGREG_RSP); + AssertCompile(DISGREG_EBP == DISGREG_RBP); + AssertCompile(DISGREG_ESP == DISGREG_SP); + AssertCompile(DISGREG_EBP == DISGREG_BP); + if (pParam->base.reg_gen == DISGREG_ESP || pParam->base.reg_gen == DISGREG_EBP) + return DISSELREG_SS; } /* Default is use DS: for data access. */ - return DIS_SELREG_DS; + return DISSELREG_DS; } //***************************************************************************** @@ -283,15 +283,15 @@ switch (pCpu->idxSegPrefix) { - case DIS_SELREG_ES: + case DISSELREG_ES: return 0x26; - case DIS_SELREG_CS: + case DISSELREG_CS: return 0x2E; - case DIS_SELREG_SS: + case DISSELREG_SS: return 0x36; - case DIS_SELREG_DS: + case DISSELREG_DS: return 0x3E; - case DIS_SELREG_FS: + case DISSELREG_FS: return 0x64; - case DIS_SELREG_GS: + case DISSELREG_GS: return 0x65; default: @@ -402,5 +402,5 @@ * */ -DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal) +DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal) { AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER); @@ -415,5 +415,5 @@ * */ -DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal, CPUMSELREGHID **ppSelHidReg) +DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal, CPUMSELREGHID **ppSelHidReg) { AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER); @@ -477,5 +477,5 @@ * */ -DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL val) +DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DISSELREG sel, RTSEL val) { AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER); Index: /trunk/src/VBox/VMM/VMMAll/EMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/EMAll.cpp (revision 41726) +++ /trunk/src/VBox/VMM/VMMAll/EMAll.cpp (revision 41727) @@ -399,5 +399,5 @@ { RTGCPTR GCPtrInstr; - int rc = SELMToFlatEx(pVCpu, DIS_SELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr); + int rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr); if (RT_FAILURE(rc)) { @@ -498,5 +498,5 @@ #else RTGCPTR pbCode; - VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode); + VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode); if (RT_SUCCESS(rc)) { @@ -552,5 +552,5 @@ #else RTGCPTR pbCode; - VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode); + VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode); if (RT_SUCCESS(rc)) { @@ -735,5 +735,5 @@ DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, PDISOPPARAM pParam, RTGCPTR pvAddr) { - DIS_SELREG enmPrefixSeg = DISDetectSegReg(pDis, pParam); + DISSELREG enmPrefixSeg = DISDetectSegReg(pDis, pParam); return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr); } @@ -1032,5 +1032,5 @@ /* Convert address; don't bother checking limits etc, as we only read here */ - pStackVal = SELMToFlat(pVM, DIS_SELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp); + pStackVal = SELMToFlat(pVM, DISSELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp); if (pStackVal == 0) return VERR_EM_INTERPRETER; @@ -1048,8 +1048,8 @@ /* pop [esp+xx] uses esp after the actual pop! */ - AssertCompile(USE_REG_ESP == USE_REG_SP); + AssertCompile(DISGREG_ESP == DISGREG_SP); if ( (pDis->param1.fUse & DISUSE_BASE) && (pDis->param1.fUse & (DISUSE_REG_GEN16|DISUSE_REG_GEN32)) - && pDis->param1.base.reg_gen == USE_REG_ESP + && pDis->param1.base.reg_gen == DISGREG_ESP ) pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size); @@ -1674,5 +1674,5 @@ } - GCDest = SELMToFlat(pVM, DIS_SELREG_ES, pRegFrame, GCOffset); + GCDest = SELMToFlat(pVM, DISSELREG_ES, pRegFrame, GCOffset); switch (pDis->opmode) { @@ -2686,5 +2686,5 @@ Assert(pRegFrame->eflags.u32 & X86_EFL_IF); - Assert(pvFault == SELMToFlat(pVM, DIS_SELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip)); + Assert(pvFault == SELMToFlat(pVM, DISSELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip)); pVCpu->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pDis->opsize; Index: /trunk/src/VBox/VMM/VMMAll/IOMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/IOMAll.cpp (revision 41726) +++ /trunk/src/VBox/VMM/VMMAll/IOMAll.cpp (revision 41727) @@ -137,5 +137,5 @@ { *pcbSize = 2; - DISFetchRegSeg(pRegFrame, (DIS_SELREG)pParam->base.reg_seg, (RTSEL *)pu64Data); + DISFetchRegSeg(pRegFrame, (DISSELREG)pParam->base.reg_seg, (RTSEL *)pu64Data); return true; } /* Else - error. */ @@ -193,5 +193,5 @@ if (pParam->fUse & DISUSE_REG_SEG) { - DISWriteRegSeg(pRegFrame, (DIS_SELREG)pParam->base.reg_seg, (RTSEL)u64Data); + DISWriteRegSeg(pRegFrame, (DISSELREG)pParam->base.reg_seg, (RTSEL)u64Data); return true; } Index: /trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp (revision 41726) +++ /trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp (revision 41727) @@ -728,5 +728,5 @@ /* Convert source address ds:esi. */ RTGCUINTPTR pu8Virt; - rc = SELMToFlatEx(pVM, DIS_SELREG_DS, pRegFrame, (RTGCPTR)pRegFrame->rsi, + rc = SELMToFlatEx(pVM, DISSELREG_DS, pRegFrame, (RTGCPTR)pRegFrame->rsi, SELMTOFLAT_FLAGS_HYPER | SELMTOFLAT_FLAGS_NO_PL, (PRTGCPTR)&pu8Virt); @@ -787,5 +787,5 @@ /* Convert destination address. */ RTGCUINTPTR pu8Virt; - rc = SELMToFlatEx(pVM, DIS_SELREG_ES, pRegFrame, (RTGCPTR)pRegFrame->rdi, + rc = SELMToFlatEx(pVM, DISSELREG_ES, pRegFrame, (RTGCPTR)pRegFrame->rdi, SELMTOFLAT_FLAGS_HYPER | SELMTOFLAT_FLAGS_NO_PL, (RTGCPTR *)&pu8Virt); @@ -2055,5 +2055,5 @@ /* Convert destination address es:edi. */ RTGCPTR GCPtrDst; - int rc2 = SELMToFlatEx(pVCpu, DIS_SELREG_ES, pRegFrame, pRegFrame->rdi & fAddrMask, + int rc2 = SELMToFlatEx(pVCpu, DISSELREG_ES, pRegFrame, pRegFrame->rdi & fAddrMask, SELMTOFLAT_FLAGS_HYPER | SELMTOFLAT_FLAGS_NO_PL, &GCPtrDst); @@ -2217,5 +2217,5 @@ /* Convert source address ds:esi. */ RTGCPTR GCPtrSrc; - int rc2 = SELMToFlatEx(pVCpu, DIS_SELREG_DS, pRegFrame, pRegFrame->rsi & fAddrMask, + int rc2 = SELMToFlatEx(pVCpu, DISSELREG_DS, pRegFrame, pRegFrame->rsi & fAddrMask, SELMTOFLAT_FLAGS_HYPER | SELMTOFLAT_FLAGS_NO_PL, &GCPtrSrc); Index: /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp (revision 41726) +++ /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp (revision 41727) @@ -806,5 +806,5 @@ if ( ( (pDis->param1.fUse & DISUSE_REG_GEN32) || (pDis->param1.fUse & DISUSE_REG_GEN64)) - && (pDis->param1.base.reg_gen == USE_REG_ESP)) + && (pDis->param1.base.reg_gen == DISGREG_ESP)) { Log4(("pgmPoolMonitorIsReused: ESP\n")); Index: /trunk/src/VBox/VMM/VMMAll/SELMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/SELMAll.cpp (revision 41726) +++ /trunk/src/VBox/VMM/VMMAll/SELMAll.cpp (revision 41727) @@ -82,5 +82,5 @@ * @param Addr Address part. */ -VMMDECL(RTGCPTR) SELMToFlat(PVM pVM, DIS_SELREG SelReg, PCPUMCTXCORE pCtxCore, RTGCPTR Addr) +VMMDECL(RTGCPTR) SELMToFlat(PVM pVM, DISSELREG SelReg, PCPUMCTXCORE pCtxCore, RTGCPTR Addr) { PCPUMSELREGHID pHiddenSel; @@ -119,6 +119,6 @@ switch (SelReg) { - case DIS_SELREG_FS: - case DIS_SELREG_GS: + case DISSELREG_FS: + case DISSELREG_GS: return (RTGCPTR)(pHiddenSel->u64Base + Addr); @@ -148,5 +148,5 @@ * @param ppvGC Where to store the GC flat address. */ -VMMDECL(int) SELMToFlatEx(PVMCPU pVCpu, DIS_SELREG SelReg, PCCPUMCTXCORE pCtxCore, RTGCPTR Addr, unsigned fFlags, PRTGCPTR ppvGC) +VMMDECL(int) SELMToFlatEx(PVMCPU pVCpu, DISSELREG SelReg, PCCPUMCTXCORE pCtxCore, RTGCPTR Addr, unsigned fFlags, PRTGCPTR ppvGC) { /* @@ -202,6 +202,6 @@ switch (SelReg) { - case DIS_SELREG_FS: - case DIS_SELREG_GS: + case DISSELREG_FS: + case DISSELREG_GS: pvFlat = (pHiddenSel->u64Base + Addr); break; Index: /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (revision 41726) +++ /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (revision 41727) @@ -3596,5 +3596,5 @@ } - rc2 = SELMToFlatEx(pVCpu, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack); + rc2 = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack); if (RT_FAILURE(rc2)) { @@ -3638,5 +3638,5 @@ } - rc2 = SELMToFlatEx(pVCpu, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, + rc2 = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, &GCPtrStack); if (RT_FAILURE(rc2)) @@ -3675,5 +3675,5 @@ } - rc2 = SELMToFlatEx(pVCpu, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack); + rc2 = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack); if (RT_FAILURE(rc2)) { Index: /trunk/src/VBox/VMM/VMMR3/CSAM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/CSAM.cpp (revision 41726) +++ /trunk/src/VBox/VMM/VMMR3/CSAM.cpp (revision 41727) @@ -2263,5 +2263,5 @@ Assert(SELMGetCpuModeFromSelector(VMMGetCpu0(pVM), pCtxCore->eflags, pCtxCore->cs, &pCtxCore->csHid) == DISCPUMODE_32BIT); - pInstrGC = SELMToFlat(pVM, DIS_SELREG_CS, pCtxCore, pInstrGC); + pInstrGC = SELMToFlat(pVM, DISSELREG_CS, pCtxCore, pInstrGC); return CSAMR3CheckCode(pVM, pInstrGC); } Index: /trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp (revision 41726) +++ /trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp (revision 41727) @@ -283,5 +283,5 @@ if ( DIS_FMT_SEL_IS_REG(u32Sel) - ? DIS_FMT_SEL_GET_REG(u32Sel) == DIS_SELREG_CS + ? DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_CS : pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel)) { Index: /trunk/src/VBox/VMM/VMMR3/EMHwaccm.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/EMHwaccm.cpp (revision 41726) +++ /trunk/src/VBox/VMM/VMMR3/EMHwaccm.cpp (revision 41727) @@ -408,7 +408,7 @@ /* Prefetch pages for EIP and ESP. */ /** @todo This is rather expensive. Should investigate if it really helps at all. */ - rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip)); + rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip)); if (rc == VINF_SUCCESS) - rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp)); + rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp)); if (rc != VINF_SUCCESS) { Index: /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp (revision 41726) +++ /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp (revision 41727) @@ -683,5 +683,5 @@ if (pCtx->SysEnter.cs != 0) { - rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip), + rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip), (SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == DISCPUMODE_32BIT) ? PATMFL_CODE32 : 0); if (RT_SUCCESS(rc)) @@ -933,5 +933,5 @@ && !PATMIsPatchGCAddr(pVM, pCtx->eip)) { - int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip), + int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip), (SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == DISCPUMODE_32BIT) ? PATMFL_CODE32 : 0); if (RT_SUCCESS(rc)) @@ -1277,7 +1277,7 @@ /* Prefetch pages for EIP and ESP. */ /** @todo This is rather expensive. Should investigate if it really helps at all. */ - rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip)); + rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip)); if (rc == VINF_SUCCESS) - rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp)); + rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp)); if (rc != VINF_SUCCESS) { Index: /trunk/src/VBox/VMM/VMMR3/HWACCM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/HWACCM.cpp (revision 41726) +++ /trunk/src/VBox/VMM/VMMR3/HWACCM.cpp (revision 41727) @@ -2028,5 +2028,5 @@ * */ - bool fUsesEax = (pDis->param2.fUse == DISUSE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX); + bool fUsesEax = (pDis->param2.fUse == DISUSE_REG_GEN32 && pDis->param2.base.reg_gen == DISGREG_EAX); aPatch[off++] = 0x51; /* push ecx */ @@ -2041,5 +2041,5 @@ { aPatch[off++] = 0x89; /* mov eax, src_reg */ - aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX); + aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, DISGREG_EAX); } } @@ -2081,9 +2081,9 @@ Assert(pDis->param1.fUse == DISUSE_REG_GEN32); - if (pDis->param1.base.reg_gen != USE_REG_ECX) + if (pDis->param1.base.reg_gen != DISGREG_ECX) aPatch[off++] = 0x51; /* push ecx */ - if (pDis->param1.base.reg_gen != USE_REG_EDX) + if (pDis->param1.base.reg_gen != DISGREG_EDX ) aPatch[off++] = 0x52; /* push edx */ - if (pDis->param1.base.reg_gen != USE_REG_EAX) + if (pDis->param1.base.reg_gen != DISGREG_EAX) aPatch[off++] = 0x50; /* push eax */ @@ -2098,15 +2098,15 @@ aPatch[off++] = 0x32; - if (pDis->param1.base.reg_gen != USE_REG_EAX) + if (pDis->param1.base.reg_gen != DISGREG_EAX) { aPatch[off++] = 0x89; /* mov dst_reg, eax */ - aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen); + aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->param1.base.reg_gen); } - if (pDis->param1.base.reg_gen != USE_REG_EAX) + if (pDis->param1.base.reg_gen != DISGREG_EAX) aPatch[off++] = 0x58; /* pop eax */ - if (pDis->param1.base.reg_gen != USE_REG_EDX) + if (pDis->param1.base.reg_gen != DISGREG_EDX ) aPatch[off++] = 0x5A; /* pop edx */ - if (pDis->param1.base.reg_gen != USE_REG_ECX) + if (pDis->param1.base.reg_gen != DISGREG_ECX) aPatch[off++] = 0x59; /* pop ecx */ } Index: /trunk/src/VBox/VMM/VMMR3/PATM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/PATM.cpp (revision 41726) +++ /trunk/src/VBox/VMM/VMMR3/PATM.cpp (revision 41727) @@ -1749,5 +1749,5 @@ /* mov ss, src? */ if ( (pCpu->param1.fUse & DISUSE_REG_SEG) - && (pCpu->param1.base.reg_seg == DIS_SELREG_SS)) + && (pCpu->param1.base.reg_seg == DISSELREG_SS)) { Log(("Force recompilation of next instruction for OP_MOV at %RRv\n", pCurInstrGC)); @@ -3486,5 +3486,5 @@ pBranchTarget = pCtx->edx; - pBranchTarget = SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pBranchTarget); + pBranchTarget = SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pBranchTarget); /* First we check if the duplicate function target lies in some existing function patch already. Will save some space. */ @@ -4068,5 +4068,5 @@ if (CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0) { - RTRCPTR pInstrGCFlat = SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pInstrGC); + RTRCPTR pInstrGCFlat = SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pInstrGC); if (pInstrGCFlat != pInstrGC) { @@ -6308,5 +6308,5 @@ /* continue at the original instruction */ - *ppNewEip = pNewEip - SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), 0); + *ppNewEip = pNewEip - SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), 0); STAM_PROFILE_ADV_STOP(&pVM->patm.s.StatHandleTrap, a); return VINF_SUCCESS; @@ -6343,5 +6343,5 @@ /* continue at the original instruction */ - *ppNewEip = pNewEip - SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), 0); + *ppNewEip = pNewEip - SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), 0); STAM_PROFILE_ADV_STOP(&pVM->patm.s.StatHandleTrap, a); return VINF_SUCCESS; @@ -6392,5 +6392,5 @@ } - *ppNewEip = pNewEip - SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), 0); + *ppNewEip = pNewEip - SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), 0); STAM_PROFILE_ADV_STOP(&pVM->patm.s.StatHandleTrap, a); return rc; @@ -6429,5 +6429,5 @@ /* Return original address, correct by subtracting the CS base address. */ - *ppNewEip = pNewEip - SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), 0); + *ppNewEip = pNewEip - SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), 0); /* Reset the PATM stack. */ Index: /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp (revision 41726) +++ /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp (revision 41727) @@ -424,5 +424,5 @@ rc = patmPatchReadBytes(pVM, pPB, pCurInstrGC, cbInstrShutUpGcc); AssertRC(rc); - PATCHGEN_EPILOG(pPatch, cbInstrShutUpGcc); + PATCHGEN_EPILOG(pPatch, cbInstrShutUpGcc); return rc; } @@ -1367,5 +1367,5 @@ pPB[offset++] = 0x8D; // lea edx, dword ptr [dest] // duplicate and modify modrm byte and additional bytes if present (e.g. direct address) - pPB[offset++] = MAKE_MODRM(pCpu->ModRM.Bits.Mod, USE_REG_EDX, pCpu->ModRM.Bits.Rm); + pPB[offset++] = MAKE_MODRM(pCpu->ModRM.Bits.Mod, DISGREG_EDX , pCpu->ModRM.Bits.Rm); i = 3; /* standard offset of modrm bytes */ @@ -1462,5 +1462,5 @@ pPB[offset++] = 0x8D; // lea edx, dword ptr [dest] // duplicate and modify modrm byte and additional bytes if present (e.g. direct address) - pPB[offset++] = MAKE_MODRM(pCpu->ModRM.Bits.Mod, USE_REG_EDX, pCpu->ModRM.Bits.Rm); + pPB[offset++] = MAKE_MODRM(pCpu->ModRM.Bits.Mod, DISGREG_EDX , pCpu->ModRM.Bits.Rm); i = 3; /* standard offset of modrm bytes */ Index: /trunk/src/VBox/VMM/include/EMHandleRCTmpl.h =================================================================== --- /trunk/src/VBox/VMM/include/EMHandleRCTmpl.h (revision 41726) +++ /trunk/src/VBox/VMM/include/EMHandleRCTmpl.h (revision 41727) @@ -111,5 +111,5 @@ */ case VINF_PATM_HC_MMIO_PATCH_READ: - rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip), + rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip), PATMFL_MMIO_ACCESS | ((SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == DISCPUMODE_32BIT) ? PATMFL_CODE32 : 0)); if (RT_FAILURE(rc))