Index: /trunk/include/VBox/dis.h =================================================================== --- /trunk/include/VBox/dis.h (revision 41674) +++ /trunk/include/VBox/dis.h (revision 41675) @@ -24,6 +24,6 @@ */ -#ifndef ___VBox_disasm_h -#define ___VBox_disasm_h +#ifndef ___VBox_dis_h +#define ___VBox_dis_h #include @@ -40,10 +40,10 @@ typedef enum DISCPUMODE { - CPUMODE_INVALID = 0, - CPUMODE_16BIT, - CPUMODE_32BIT, - CPUMODE_64BIT, + DISCPUMODE_INVALID = 0, + DISCPUMODE_16BIT, + DISCPUMODE_32BIT, + DISCPUMODE_64BIT, /** hack forcing the size of the enum to 32-bits. */ - CPUMODE_MAKE_32BIT_HACK = 0x7fffffff + DISCPUMODE_MAKE_32BIT_HACK = 0x7fffffff } DISCPUMODE; @@ -51,19 +51,19 @@ * @{ */ -#define PREFIX_NONE 0 +#define DISPREFIX_NONE UINT8_C(0x00) /** non-default address size. */ -#define PREFIX_ADDRSIZE UINT8_C(0x00) +#define DISPREFIX_ADDRSIZE UINT8_C(0x01) /** non-default operand size. */ -#define PREFIX_OPSIZE UINT8_C(0x01) +#define DISPREFIX_OPSIZE UINT8_C(0x02) /** lock prefix. */ -#define PREFIX_LOCK UINT8_C(0x02) +#define DISPREFIX_LOCK UINT8_C(0x04) /** segment prefix. */ -#define PREFIX_SEG UINT8_C(0x04) +#define DISPREFIX_SEG UINT8_C(0x08) /** rep(e) prefix (not a prefix, but we'll treat is as one). */ -#define PREFIX_REP UINT8_C(0x08) +#define DISPREFIX_REP UINT8_C(0x10) /** rep(e) prefix (not a prefix, but we'll treat is as one). */ -#define PREFIX_REPNE UINT8_C(0x10) +#define DISPREFIX_REPNE UINT8_C(0x20) /** REX prefix (64 bits) */ -#define PREFIX_REX UINT8_C(0x20) +#define DISPREFIX_REX UINT8_C(0x40) /** @} */ Index: /trunk/src/VBox/Devices/PC/BIOS-new/MakeDebianBiosAssembly.cpp =================================================================== --- /trunk/src/VBox/Devices/PC/BIOS-new/MakeDebianBiosAssembly.cpp (revision 41674) +++ /trunk/src/VBox/Devices/PC/BIOS-new/MakeDebianBiosAssembly.cpp (revision 41675) @@ -968,5 +968,5 @@ unsigned cbInstr; DISCPUSTATE CpuState; - int rc = DISInstrWithReader(uFlatAddr, fIs16Bit ? CPUMODE_16BIT : CPUMODE_32BIT, + int rc = DISInstrWithReader(uFlatAddr, fIs16Bit ? DISCPUMODE_16BIT : DISCPUMODE_32BIT, disReadOpcodeBytes, NULL, &CpuState, &cbInstr); if ( RT_SUCCESS(rc) Index: /trunk/src/VBox/Disassembler/DisasmCore.cpp =================================================================== --- /trunk/src/VBox/Disassembler/DisasmCore.cpp (revision 41674) +++ /trunk/src/VBox/Disassembler/DisasmCore.cpp (revision 41675) @@ -216,5 +216,5 @@ * accessed without faulting. (Consider * DISInstrWithReader if this isn't the case.) - * @param enmCpuMode The CPU mode. CPUMODE_32BIT, CPUMODE_16BIT, or CPUMODE_64BIT. + * @param enmCpuMode The CPU mode. DISCPUMODE_32BIT, DISCPUMODE_16BIT, or DISCPUMODE_64BIT. * @param pfnReadBytes Callback for reading instruction bytes. * @param pvUser User argument for the instruction reader. (Ends up in apvUserData[0].) @@ -238,5 +238,5 @@ * @param uInstrAddr Address of the instruction to decode. What this means * is left to the pfnReadBytes function. - * @param enmCpuMode The CPU mode. CPUMODE_32BIT, CPUMODE_16BIT, or CPUMODE_64BIT. + * @param enmCpuMode The CPU mode. DISCPUMODE_32BIT, DISCPUMODE_16BIT, or DISCPUMODE_64BIT. * @param pfnReadBytes Callback for reading instruction bytes. * @param pvUser User argument for the instruction reader. (Ends up in apvUserData[0].) @@ -259,5 +259,5 @@ * @param uInstrAddr Address of the instruction to decode. What this means * is left to the pfnReadBytes function. - * @param enmCpuMode The CPU mode. CPUMODE_32BIT, CPUMODE_16BIT, or CPUMODE_64BIT. + * @param enmCpuMode The CPU mode. DISCPUMODE_32BIT, DISCPUMODE_16BIT, or DISCPUMODE_64BIT. * @param pfnReadBytes Callback for reading instruction bytes. * @param fFilter Instruction type filter. @@ -284,9 +284,9 @@ pCpu->mode = enmCpuMode; - if (enmCpuMode == CPUMODE_64BIT) + if (enmCpuMode == DISCPUMODE_64BIT) { paOneByteMap = g_aOneByteMapX64; - pCpu->addrmode = CPUMODE_64BIT; - pCpu->opmode = CPUMODE_32BIT; + pCpu->addrmode = DISCPUMODE_64BIT; + pCpu->opmode = DISCPUMODE_32BIT; } else @@ -296,5 +296,5 @@ pCpu->opmode = enmCpuMode; } - pCpu->prefix = PREFIX_NONE; + pCpu->prefix = DISPREFIX_NONE; pCpu->enmPrefixSeg = DIS_SELREG_DS; pCpu->uInstrAddr = uInstrAddr; @@ -338,5 +338,5 @@ /** Last prefix byte (for SSE2 extension tables); don't include the REX prefix */ pCpu->lastprefix = opcode; - pCpu->prefix &= ~PREFIX_REX; + pCpu->prefix &= ~DISPREFIX_REX; } @@ -352,8 +352,8 @@ pCpu->enmPrefixSeg = (DIS_SELREG)(paOneByteMap[codebyte].param1 - OP_PARM_REG_SEG_START); /* Segment prefixes for CS, DS, ES and SS are ignored in long mode. */ - if ( pCpu->mode != CPUMODE_64BIT + if ( pCpu->mode != DISCPUMODE_64BIT || pCpu->enmPrefixSeg >= DIS_SELREG_FS) { - pCpu->prefix |= PREFIX_SEG; + pCpu->prefix |= DISPREFIX_SEG; } iByte += sizeof(uint8_t); @@ -362,5 +362,5 @@ // lock prefix byte case OP_LOCK: - pCpu->prefix |= PREFIX_LOCK; + pCpu->prefix |= DISPREFIX_LOCK; iByte += sizeof(uint8_t); continue; //fetch the next byte @@ -368,12 +368,12 @@ // address size override prefix byte case OP_ADDRSIZE: - pCpu->prefix |= PREFIX_ADDRSIZE; - if (pCpu->mode == CPUMODE_16BIT) - pCpu->addrmode = CPUMODE_32BIT; + pCpu->prefix |= DISPREFIX_ADDRSIZE; + if (pCpu->mode == DISCPUMODE_16BIT) + pCpu->addrmode = DISCPUMODE_32BIT; else - if (pCpu->mode == CPUMODE_32BIT) - pCpu->addrmode = CPUMODE_16BIT; + if (pCpu->mode == DISCPUMODE_32BIT) + pCpu->addrmode = DISCPUMODE_16BIT; else - pCpu->addrmode = CPUMODE_32BIT; /* 64 bits */ + pCpu->addrmode = DISCPUMODE_32BIT; /* 64 bits */ iByte += sizeof(uint8_t); @@ -382,9 +382,9 @@ // operand size override prefix byte case OP_OPSIZE: - pCpu->prefix |= PREFIX_OPSIZE; - if (pCpu->mode == CPUMODE_16BIT) - pCpu->opmode = CPUMODE_32BIT; + pCpu->prefix |= DISPREFIX_OPSIZE; + if (pCpu->mode == DISCPUMODE_16BIT) + pCpu->opmode = DISCPUMODE_32BIT; else - pCpu->opmode = CPUMODE_16BIT; /* for 32 and 64 bits mode (there is no 32 bits operand size override prefix) */ + pCpu->opmode = DISCPUMODE_16BIT; /* for 32 and 64 bits mode (there is no 32 bits operand size override prefix) */ iByte += sizeof(uint8_t); @@ -393,22 +393,22 @@ // rep and repne are not really prefixes, but we'll treat them as such case OP_REPE: - pCpu->prefix |= PREFIX_REP; + pCpu->prefix |= DISPREFIX_REP; iByte += sizeof(uint8_t); continue; //fetch the next byte case OP_REPNE: - pCpu->prefix |= PREFIX_REPNE; + pCpu->prefix |= DISPREFIX_REPNE; iByte += sizeof(uint8_t); continue; //fetch the next byte case OP_REX: - Assert(pCpu->mode == CPUMODE_64BIT); + Assert(pCpu->mode == DISCPUMODE_64BIT); /* REX prefix byte */ - pCpu->prefix |= PREFIX_REX; + pCpu->prefix |= DISPREFIX_REX; pCpu->prefix_rex = PREFIX_REX_OP_2_FLAGS(paOneByteMap[codebyte].param1); iByte += sizeof(uint8_t); if (pCpu->prefix_rex & PREFIX_REX_FLAGS_W) - pCpu->opmode = CPUMODE_64BIT; /* overrides size prefix byte */ + pCpu->opmode = DISCPUMODE_64BIT; /* overrides size prefix byte */ continue; //fetch the next byte } @@ -430,5 +430,5 @@ *pcbInstr = iByte; - if (pCpu->prefix & PREFIX_LOCK) + if (pCpu->prefix & DISPREFIX_LOCK) disValidateLockSequence(pCpu); @@ -471,12 +471,12 @@ /* Correct the operand size if the instruction is marked as forced or default 64 bits */ - if (pCpu->mode == CPUMODE_64BIT) + if (pCpu->mode == DISCPUMODE_64BIT) { if (pOp->optype & OPTYPE_FORCED_64_OP_SIZE) - pCpu->opmode = CPUMODE_64BIT; + pCpu->opmode = DISCPUMODE_64BIT; else if ( (pOp->optype & OPTYPE_DEFAULT_64_OP_SIZE) - && !(pCpu->prefix & PREFIX_OPSIZE)) - pCpu->opmode = CPUMODE_64BIT; + && !(pCpu->prefix & DISPREFIX_OPSIZE)) + pCpu->opmode = DISCPUMODE_64BIT; } else @@ -484,6 +484,6 @@ { /* Forced 32 bits operand size for certain instructions (mov crx, mov drx). */ - Assert(pCpu->mode != CPUMODE_64BIT); - pCpu->opmode = CPUMODE_32BIT; + Assert(pCpu->mode != DISCPUMODE_64BIT); + pCpu->opmode = DISCPUMODE_32BIT; } @@ -549,13 +549,13 @@ /* Correct the operand size if the instruction is marked as forced or default 64 bits */ - if (pCpu->mode == CPUMODE_64BIT) + if (pCpu->mode == DISCPUMODE_64BIT) { /* Note: redundant, but just in case this ever changes */ if (fpop->optype & OPTYPE_FORCED_64_OP_SIZE) - pCpu->opmode = CPUMODE_64BIT; + pCpu->opmode = DISCPUMODE_64BIT; else if ( (fpop->optype & OPTYPE_DEFAULT_64_OP_SIZE) - && !(pCpu->prefix & PREFIX_OPSIZE)) - pCpu->opmode = CPUMODE_64BIT; + && !(pCpu->prefix & DISPREFIX_OPSIZE)) + pCpu->opmode = DISCPUMODE_64BIT; } @@ -601,5 +601,5 @@ index = pCpu->SIB.Bits.Index; - if (pCpu->addrmode == CPUMODE_32BIT) + if (pCpu->addrmode == DISCPUMODE_32BIT) { ppszSIBIndexReg = szSIBIndexReg; @@ -629,5 +629,5 @@ { // [scaled index] + disp32 - if (pCpu->addrmode == CPUMODE_32BIT) + if (pCpu->addrmode == DISCPUMODE_32BIT) { pParam->flags |= USE_DISPLACEMENT32; @@ -662,5 +662,5 @@ pCpu->SIB.Bits.Scale = SIB_SCALE(SIB); - if (pCpu->prefix & PREFIX_REX) + if (pCpu->prefix & DISPREFIX_REX) { /* REX.B extends the Base field if not scaled index + disp32 */ @@ -695,5 +695,5 @@ pCpu->SIB.Bits.Scale = SIB_SCALE(SIB); - if (pCpu->prefix & PREFIX_REX) + if (pCpu->prefix & DISPREFIX_REX) { /* REX.B extends the Base field. */ @@ -738,8 +738,8 @@ if ( pCpu->pCurInstr->opcode == OP_MOV_CR - && pCpu->opmode == CPUMODE_32BIT - && (pCpu->prefix & PREFIX_LOCK)) + && pCpu->opmode == DISCPUMODE_32BIT + && (pCpu->prefix & DISPREFIX_LOCK)) { - pCpu->prefix &= ~PREFIX_LOCK; + pCpu->prefix &= ~DISPREFIX_LOCK; pParam->base.reg_ctrl = USE_REG_CR8; } @@ -787,7 +787,7 @@ /* @todo bound */ - if (pCpu->addrmode != CPUMODE_16BIT) - { - Assert(pCpu->addrmode == CPUMODE_32BIT || pCpu->addrmode == CPUMODE_64BIT); + if (pCpu->addrmode != DISCPUMODE_16BIT) + { + Assert(pCpu->addrmode == DISCPUMODE_32BIT || pCpu->addrmode == DISCPUMODE_64BIT); /* @@ -805,5 +805,5 @@ { /* 32 bits displacement */ - if (pCpu->mode != CPUMODE_64BIT) + if (pCpu->mode != DISCPUMODE_64BIT) { pParam->flags |= USE_DISPLACEMENT32; @@ -906,7 +906,7 @@ *pSibInc = 0; - if (pCpu->addrmode != CPUMODE_16BIT) - { - Assert(pCpu->addrmode == CPUMODE_32BIT || pCpu->addrmode == CPUMODE_64BIT); + if (pCpu->addrmode != DISCPUMODE_16BIT) + { + Assert(pCpu->addrmode == DISCPUMODE_32BIT || pCpu->addrmode == DISCPUMODE_64BIT); /* @@ -989,7 +989,7 @@ *pSibInc = 0; - if (pCpu->addrmode != CPUMODE_16BIT) - { - Assert(pCpu->addrmode == CPUMODE_32BIT || pCpu->addrmode == CPUMODE_64BIT); + if (pCpu->addrmode != DISCPUMODE_16BIT) + { + Assert(pCpu->addrmode == DISCPUMODE_32BIT || pCpu->addrmode == DISCPUMODE_64BIT); /* * Note: displacements in long mode are 8 or 32 bits and sign-extended to 64 bits @@ -1080,7 +1080,7 @@ pCpu->ModRM.Bits.Mod = 3; - if (pCpu->prefix & PREFIX_REX) - { - Assert(pCpu->mode == CPUMODE_64BIT); + if (pCpu->prefix & DISPREFIX_REX) + { + Assert(pCpu->mode == DISCPUMODE_64BIT); /* REX.R extends the Reg field. */ @@ -1126,7 +1126,7 @@ pCpu->ModRM.Bits.Mod = 3; - if (pCpu->prefix & PREFIX_REX) - { - Assert(pCpu->mode == CPUMODE_64BIT); + if (pCpu->prefix & DISPREFIX_REX) + { + Assert(pCpu->mode == DISCPUMODE_64BIT); /* REX.R extends the Reg field. */ @@ -1181,5 +1181,5 @@ { NOREF(pOp); - if (pCpu->opmode == CPUMODE_32BIT) + if (pCpu->opmode == DISCPUMODE_32BIT) { pParam->parval = (uint32_t)(int8_t)DISReadByte(pCpu, uCodePtr); @@ -1188,5 +1188,5 @@ } else - if (pCpu->opmode == CPUMODE_64BIT) + if (pCpu->opmode == DISCPUMODE_64BIT) { pParam->parval = (uint64_t)(int8_t)DISReadByte(pCpu, uCodePtr); @@ -1265,5 +1265,5 @@ { NOREF(pOp); - if (pCpu->opmode == CPUMODE_32BIT) + if (pCpu->opmode == DISCPUMODE_32BIT) { pParam->parval = DISReadDWord(pCpu, uCodePtr); @@ -1273,5 +1273,5 @@ } - if (pCpu->opmode == CPUMODE_64BIT) + if (pCpu->opmode == DISCPUMODE_64BIT) { pParam->parval = DISReadQWord(pCpu, uCodePtr); @@ -1291,7 +1291,7 @@ { NOREF(uCodePtr); NOREF(pOp); NOREF(pParam); - if (pCpu->opmode == CPUMODE_32BIT) + if (pCpu->opmode == DISCPUMODE_32BIT) return sizeof(uint32_t); - if (pCpu->opmode == CPUMODE_64BIT) + if (pCpu->opmode == DISCPUMODE_64BIT) return sizeof(uint64_t); return sizeof(uint16_t); @@ -1303,5 +1303,5 @@ NOREF(pOp); /* Word for 16-bit operand-size or doubleword for 32 or 64-bit operand-size. */ - if (pCpu->opmode == CPUMODE_16BIT) + if (pCpu->opmode == DISCPUMODE_16BIT) { pParam->parval = DISReadWord(pCpu, uCodePtr); @@ -1312,5 +1312,5 @@ /* 64 bits op mode means *sign* extend to 64 bits. */ - if (pCpu->opmode == CPUMODE_64BIT) + if (pCpu->opmode == DISCPUMODE_64BIT) { pParam->parval = (uint64_t)(int32_t)DISReadDWord(pCpu, uCodePtr); @@ -1332,5 +1332,5 @@ NOREF(uCodePtr); NOREF(pOp); NOREF(pParam); /* Word for 16-bit operand-size or doubleword for 32 or 64-bit operand-size. */ - if (pCpu->opmode == CPUMODE_16BIT) + if (pCpu->opmode == DISCPUMODE_16BIT) return sizeof(uint16_t); return sizeof(uint32_t); @@ -1362,5 +1362,5 @@ { NOREF(pOp); - if (pCpu->opmode == CPUMODE_32BIT) + if (pCpu->opmode == DISCPUMODE_32BIT) { pParam->parval = DISReadDWord(pCpu, uCodePtr); @@ -1370,5 +1370,5 @@ } - if (pCpu->opmode == CPUMODE_64BIT) + if (pCpu->opmode == DISCPUMODE_64BIT) { /* 32 bits relative immediate sign extended to 64 bits. */ @@ -1390,5 +1390,5 @@ { NOREF(uCodePtr); NOREF(pOp); NOREF(pParam); - if (pCpu->opmode == CPUMODE_16BIT) + if (pCpu->opmode == DISCPUMODE_16BIT) return sizeof(int16_t); /* Both 32 & 64 bits mode use 32 bits relative immediates. */ @@ -1399,5 +1399,5 @@ unsigned ParseImmAddr(RTUINTPTR uCodePtr, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu) { - if (pCpu->addrmode == CPUMODE_32BIT) + if (pCpu->addrmode == DISCPUMODE_32BIT) { if (OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_p) @@ -1423,5 +1423,5 @@ } - if (pCpu->addrmode == CPUMODE_64BIT) + if (pCpu->addrmode == DISCPUMODE_64BIT) { Assert(OP_PARM_VSUBTYPE(pParam->param) != OP_PARM_p); @@ -1462,5 +1462,5 @@ { NOREF(uCodePtr); NOREF(pOp); - if (pCpu->addrmode == CPUMODE_32BIT) + if (pCpu->addrmode == DISCPUMODE_32BIT) { if (OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_p) @@ -1473,5 +1473,5 @@ } } - if (pCpu->addrmode == CPUMODE_64BIT) + if (pCpu->addrmode == DISCPUMODE_64BIT) { Assert(OP_PARM_VSUBTYPE(pParam->param) != OP_PARM_p); @@ -1495,7 +1495,7 @@ { // immediate far pointers - only 16:16 or 16:32; determined by operand, *not* address size! - Assert(pCpu->opmode == CPUMODE_16BIT || pCpu->opmode == CPUMODE_32BIT); + Assert(pCpu->opmode == DISCPUMODE_16BIT || pCpu->opmode == DISCPUMODE_32BIT); Assert(OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_p); - if (pCpu->opmode == CPUMODE_32BIT) + if (pCpu->opmode == DISCPUMODE_32BIT) { // far 16:32 pointer @@ -1519,7 +1519,7 @@ NOREF(uCodePtr); NOREF(pOp); // immediate far pointers - only 16:16 or 16:32 - Assert(pCpu->opmode == CPUMODE_16BIT || pCpu->opmode == CPUMODE_32BIT); + Assert(pCpu->opmode == DISCPUMODE_16BIT || pCpu->opmode == DISCPUMODE_32BIT); Assert(OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_p); - if (pCpu->opmode == CPUMODE_32BIT) + if (pCpu->opmode == DISCPUMODE_32BIT) { // far 16:32 pointer @@ -1556,5 +1556,5 @@ { /* 32-bit EAX..EDI registers. */ - if (pCpu->opmode == CPUMODE_32BIT) + if (pCpu->opmode == DISCPUMODE_32BIT) { /* Use 32-bit registers. */ @@ -1564,5 +1564,5 @@ } else - if (pCpu->opmode == CPUMODE_64BIT) + if (pCpu->opmode == DISCPUMODE_64BIT) { /* Use 64-bit registers. */ @@ -1570,5 +1570,5 @@ if ( (pOp->optype & OPTYPE_REXB_EXTENDS_OPREG) && pParam == &pCpu->param1 /* ugly assumption that it only applies to the first parameter */ - && (pCpu->prefix & PREFIX_REX) + && (pCpu->prefix & DISPREFIX_REX) && (pCpu->prefix_rex & PREFIX_REX_FLAGS)) pParam->base.reg_gen += 8; @@ -1610,9 +1610,9 @@ pParam->cb = 1; - if (pCpu->opmode == CPUMODE_64BIT) + if (pCpu->opmode == DISCPUMODE_64BIT) { if ( (pOp->optype & OPTYPE_REXB_EXTENDS_OPREG) && pParam == &pCpu->param1 /* ugly assumption that it only applies to the first parameter */ - && (pCpu->prefix & PREFIX_REX) + && (pCpu->prefix & DISPREFIX_REX) && (pCpu->prefix_rex & PREFIX_REX_FLAGS)) pParam->base.reg_gen += 8; /* least significant byte of R8-R15 */ @@ -1640,5 +1640,5 @@ pParam->flags |= USE_POINTER_DS_BASED; - if (pCpu->addrmode == CPUMODE_32BIT) + if (pCpu->addrmode == DISCPUMODE_32BIT) { pParam->base.reg_gen = USE_REG_ESI; @@ -1646,5 +1646,5 @@ } else - if (pCpu->addrmode == CPUMODE_64BIT) + if (pCpu->addrmode == DISCPUMODE_64BIT) { pParam->base.reg_gen = USE_REG_RSI; @@ -1665,5 +1665,5 @@ pParam->flags |= USE_POINTER_DS_BASED; - if (pCpu->addrmode == CPUMODE_32BIT) + if (pCpu->addrmode == DISCPUMODE_32BIT) { pParam->base.reg_gen = USE_REG_ESI; @@ -1671,5 +1671,5 @@ } else - if (pCpu->addrmode == CPUMODE_64BIT) + if (pCpu->addrmode == DISCPUMODE_64BIT) { pParam->base.reg_gen = USE_REG_RSI; @@ -1690,5 +1690,5 @@ pParam->flags |= USE_POINTER_ES_BASED; - if (pCpu->addrmode == CPUMODE_32BIT) + if (pCpu->addrmode == DISCPUMODE_32BIT) { pParam->base.reg_gen = USE_REG_EDI; @@ -1696,5 +1696,5 @@ } else - if (pCpu->addrmode == CPUMODE_64BIT) + if (pCpu->addrmode == DISCPUMODE_64BIT) { pParam->base.reg_gen = USE_REG_RDI; @@ -1715,5 +1715,5 @@ pParam->flags |= USE_POINTER_ES_BASED; - if (pCpu->addrmode == CPUMODE_32BIT) + if (pCpu->addrmode == DISCPUMODE_32BIT) { pParam->base.reg_gen = USE_REG_EDI; @@ -1721,5 +1721,5 @@ } else - if (pCpu->addrmode == CPUMODE_64BIT) + if (pCpu->addrmode == DISCPUMODE_64BIT) { pParam->base.reg_gen = USE_REG_RDI; @@ -1760,5 +1760,5 @@ /* Cancel prefix changes. */ - pCpu->prefix &= ~PREFIX_OPSIZE; + pCpu->prefix &= ~DISPREFIX_OPSIZE; pCpu->opmode = pCpu->mode; } @@ -1772,5 +1772,5 @@ /* Cancel prefix changes. */ - pCpu->prefix &= ~PREFIX_REPNE; + pCpu->prefix &= ~DISPREFIX_REPNE; } break; @@ -1783,5 +1783,5 @@ /* Cancel prefix changes. */ - pCpu->prefix &= ~PREFIX_REP; + pCpu->prefix &= ~DISPREFIX_REP; } break; @@ -1827,5 +1827,5 @@ /* Cancel prefix changes. */ - pCpu->prefix &= ~PREFIX_OPSIZE; + pCpu->prefix &= ~DISPREFIX_OPSIZE; pCpu->opmode = pCpu->mode; } @@ -1844,5 +1844,5 @@ /* Cancel prefix changes. */ - pCpu->prefix &= ~PREFIX_REPNE; + pCpu->prefix &= ~DISPREFIX_REPNE; } } @@ -1878,5 +1878,5 @@ /* Cancel prefix changes. */ - pCpu->prefix &= ~PREFIX_OPSIZE; + pCpu->prefix &= ~DISPREFIX_OPSIZE; pCpu->opmode = pCpu->mode; } @@ -1895,8 +1895,8 @@ NOREF(pParam); - if (pCpu->prefix & PREFIX_REP) + if (pCpu->prefix & DISPREFIX_REP) { pOp = &g_aMapX86_NopPause[1]; /* PAUSE */ - pCpu->prefix &= ~PREFIX_REP; + pCpu->prefix &= ~DISPREFIX_REP; } else @@ -2185,5 +2185,5 @@ reg = MODRM_REG(modrm); - if (pCpu->prefix & PREFIX_OPSIZE) + if (pCpu->prefix & DISPREFIX_OPSIZE) reg += 8; //2nd table @@ -2206,5 +2206,5 @@ modrm = DISReadByte(pCpu, uCodePtr); reg = MODRM_REG(modrm); - if (pCpu->prefix & PREFIX_OPSIZE) + if (pCpu->prefix & DISPREFIX_OPSIZE) reg += 8; //2nd table @@ -2228,5 +2228,5 @@ modrm = DISReadByte(pCpu, uCodePtr); reg = MODRM_REG(modrm); - if (pCpu->prefix & PREFIX_OPSIZE) + if (pCpu->prefix & DISPREFIX_OPSIZE) reg += 8; //2nd table @@ -2306,5 +2306,5 @@ subtype = OP_PARM_VSUBTYPE(pParam->param); if (fRegAddr) - subtype = (pCpu->addrmode == CPUMODE_64BIT) ? OP_PARM_q : OP_PARM_d; + subtype = (pCpu->addrmode == DISCPUMODE_64BIT) ? OP_PARM_q : OP_PARM_d; else if (subtype == OP_PARM_v || subtype == OP_PARM_NONE) @@ -2312,11 +2312,11 @@ switch(pCpu->opmode) { - case CPUMODE_32BIT: + case DISCPUMODE_32BIT: subtype = OP_PARM_d; break; - case CPUMODE_64BIT: + case DISCPUMODE_64BIT: subtype = OP_PARM_q; break; - case CPUMODE_16BIT: + case DISCPUMODE_16BIT: subtype = OP_PARM_w; break; @@ -2330,9 +2330,9 @@ { case OP_PARM_b: - Assert(idx < (pCpu->prefix & PREFIX_REX) ? 16 : 8); + Assert(idx < (pCpu->prefix & DISPREFIX_REX) ? 16 : 8); /* AH, BH, CH & DH map to DIL, SIL, EBL & SPL when a rex prefix is present. */ /* Intel® 64 and IA-32 Architectures Software Developer’s Manual: 3.4.1.1 */ - if ( (pCpu->prefix & PREFIX_REX) + if ( (pCpu->prefix & DISPREFIX_REX) && idx >= USE_REG_AH && idx <= USE_REG_BH) @@ -2346,5 +2346,5 @@ case OP_PARM_w: - Assert(idx < (pCpu->prefix & PREFIX_REX) ? 16 : 8); + Assert(idx < (pCpu->prefix & DISPREFIX_REX) ? 16 : 8); pParam->flags |= USE_REG_GEN16; @@ -2353,5 +2353,5 @@ case OP_PARM_d: - Assert(idx < (pCpu->prefix & PREFIX_REX) ? 16 : 8); + Assert(idx < (pCpu->prefix & DISPREFIX_REX) ? 16 : 8); pParam->flags |= USE_REG_GEN32; @@ -2618,5 +2618,5 @@ void disValidateLockSequence(PDISCPUSTATE pCpu) { - Assert(pCpu->prefix & PREFIX_LOCK); + Assert(pCpu->prefix & DISPREFIX_LOCK); /* Index: /trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp =================================================================== --- /trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp (revision 41674) +++ /trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp (revision 41675) @@ -206,5 +206,5 @@ switch (pCpu->addrmode) { - case CPUMODE_16BIT: + case DISCPUMODE_16BIT: { Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen16)); @@ -214,5 +214,5 @@ } - case CPUMODE_32BIT: + case DISCPUMODE_32BIT: { Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen32)); @@ -222,5 +222,5 @@ } - case CPUMODE_64BIT: + case DISCPUMODE_64BIT: { Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen64)); @@ -392,5 +392,5 @@ if ( pOp->opcode == OP_INVALID || ( pOp->opcode == OP_ILLUD2 - && (pCpu->prefix & PREFIX_LOCK))) + && (pCpu->prefix & DISPREFIX_LOCK))) { @@ -401,9 +401,9 @@ * Prefixes */ - if (pCpu->prefix & PREFIX_LOCK) + if (pCpu->prefix & DISPREFIX_LOCK) PUT_SZ("lock "); - if(pCpu->prefix & PREFIX_REP) + if(pCpu->prefix & DISPREFIX_REP) PUT_SZ("rep "); - else if(pCpu->prefix & PREFIX_REPNE) + else if(pCpu->prefix & DISPREFIX_REPNE) PUT_SZ("repne "); @@ -417,17 +417,17 @@ { case OP_JECXZ: - pszFmt = pCpu->opmode == CPUMODE_16BIT ? "jcxz %Jb" : pCpu->opmode == CPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb"; + pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "jcxz %Jb" : pCpu->opmode == DISCPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb"; break; case OP_PUSHF: - pszFmt = pCpu->opmode == CPUMODE_16BIT ? "pushfw" : pCpu->opmode == CPUMODE_32BIT ? "pushfd" : "pushfq"; + pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "pushfw" : pCpu->opmode == DISCPUMODE_32BIT ? "pushfd" : "pushfq"; break; case OP_POPF: - pszFmt = pCpu->opmode == CPUMODE_16BIT ? "popfw" : pCpu->opmode == CPUMODE_32BIT ? "popfd" : "popfq"; + pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "popfw" : pCpu->opmode == DISCPUMODE_32BIT ? "popfd" : "popfq"; break; case OP_PUSHA: - pszFmt = pCpu->opmode == CPUMODE_16BIT ? "pushaw" : "pushad"; + pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "pushaw" : "pushad"; break; case OP_POPA: - pszFmt = pCpu->opmode == CPUMODE_16BIT ? "popaw" : "popad"; + pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "popaw" : "popad"; break; case OP_INSB: @@ -435,5 +435,5 @@ break; case OP_INSWD: - pszFmt = pCpu->opmode == CPUMODE_16BIT ? "insw" : pCpu->opmode == CPUMODE_32BIT ? "insd" : "insq"; + pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "insw" : pCpu->opmode == DISCPUMODE_32BIT ? "insd" : "insq"; break; case OP_OUTSB: @@ -441,5 +441,5 @@ break; case OP_OUTSWD: - pszFmt = pCpu->opmode == CPUMODE_16BIT ? "outsw" : pCpu->opmode == CPUMODE_32BIT ? "outsd" : "outsq"; + pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "outsw" : pCpu->opmode == DISCPUMODE_32BIT ? "outsd" : "outsq"; break; case OP_MOVSB: @@ -447,5 +447,5 @@ break; case OP_MOVSWD: - pszFmt = pCpu->opmode == CPUMODE_16BIT ? "movsw" : pCpu->opmode == CPUMODE_32BIT ? "movsd" : "movsq"; + pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "movsw" : pCpu->opmode == DISCPUMODE_32BIT ? "movsd" : "movsq"; break; case OP_CMPSB: @@ -453,5 +453,5 @@ break; case OP_CMPWD: - pszFmt = pCpu->opmode == CPUMODE_16BIT ? "cmpsw" : pCpu->opmode == CPUMODE_32BIT ? "cmpsd" : "cmpsq"; + pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "cmpsw" : pCpu->opmode == DISCPUMODE_32BIT ? "cmpsd" : "cmpsq"; break; case OP_SCASB: @@ -459,5 +459,5 @@ break; case OP_SCASWD: - pszFmt = pCpu->opmode == CPUMODE_16BIT ? "scasw" : pCpu->opmode == CPUMODE_32BIT ? "scasd" : "scasq"; + pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "scasw" : pCpu->opmode == DISCPUMODE_32BIT ? "scasd" : "scasq"; break; case OP_LODSB: @@ -465,5 +465,5 @@ break; case OP_LODSWD: - pszFmt = pCpu->opmode == CPUMODE_16BIT ? "lodsw" : pCpu->opmode == CPUMODE_32BIT ? "lodsd" : "lodsq"; + pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "lodsw" : pCpu->opmode == DISCPUMODE_32BIT ? "lodsd" : "lodsq"; break; case OP_STOSB: @@ -471,11 +471,11 @@ break; case OP_STOSWD: - pszFmt = pCpu->opmode == CPUMODE_16BIT ? "stosw" : pCpu->opmode == CPUMODE_32BIT ? "stosd" : "stosq"; + pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "stosw" : pCpu->opmode == DISCPUMODE_32BIT ? "stosd" : "stosq"; break; case OP_CBW: - pszFmt = pCpu->opmode == CPUMODE_16BIT ? "cbw" : pCpu->opmode == CPUMODE_32BIT ? "cwde" : "cdqe"; + pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "cbw" : pCpu->opmode == DISCPUMODE_32BIT ? "cwde" : "cdqe"; break; case OP_CWD: - pszFmt = pCpu->opmode == CPUMODE_16BIT ? "cwd" : pCpu->opmode == CPUMODE_32BIT ? "cdq" : "cqo"; + pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "cwd" : pCpu->opmode == DISCPUMODE_32BIT ? "cdq" : "cqo"; break; case OP_SHL: @@ -576,7 +576,7 @@ switch (pCpu->opmode) \ { \ - case CPUMODE_16BIT: PUT_SZ("word "); break; \ - case CPUMODE_32BIT: PUT_SZ("dword "); break; \ - case CPUMODE_64BIT: PUT_SZ("qword "); break; \ + case DISCPUMODE_16BIT: PUT_SZ("word "); break; \ + case DISCPUMODE_32BIT: PUT_SZ("dword "); break; \ + case DISCPUMODE_64BIT: PUT_SZ("qword "); break; \ default: break; \ } \ @@ -604,5 +604,5 @@ #define PUT_SEGMENT_OVERRIDE() \ do { \ - if (pCpu->prefix & PREFIX_SEG) \ + if (pCpu->prefix & DISPREFIX_SEG) \ PUT_STR(s_szSegPrefix[pCpu->enmPrefixSeg], 3); \ } while (0) @@ -612,5 +612,5 @@ * Segment prefixing for instructions that doesn't do memory access. */ - if ( (pCpu->prefix & PREFIX_SEG) + if ( (pCpu->prefix & DISPREFIX_SEG) && !DIS_IS_EFFECTIVE_ADDR(pCpu->param1.flags) && !DIS_IS_EFFECTIVE_ADDR(pCpu->param2.flags) @@ -812,5 +812,5 @@ case USE_IMMEDIATE32: - if ( pCpu->opmode != (pCpu->mode == CPUMODE_16BIT ? CPUMODE_16BIT : CPUMODE_32BIT) /* not perfect */ + if ( pCpu->opmode != (pCpu->mode == DISCPUMODE_16BIT ? DISCPUMODE_16BIT : DISCPUMODE_32BIT) /* not perfect */ || ( (fFlags & DIS_FMT_FLAGS_STRICT) && ( (int8_t)pParam->parval == (int32_t)pParam->parval @@ -897,7 +897,7 @@ RTUINTPTR uTrgAddr = pCpu->uInstrAddr + pCpu->opsize + offDisplacement; - if (pCpu->mode == CPUMODE_16BIT) + if (pCpu->mode == DISCPUMODE_16BIT) PUT_NUM_16(uTrgAddr); - else if (pCpu->mode == CPUMODE_32BIT) + else if (pCpu->mode == DISCPUMODE_32BIT) PUT_NUM_32(uTrgAddr); else @@ -1202,5 +1202,5 @@ * Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons. */ - if ( pCpu->addrmode != CPUMODE_16BIT ///@todo correct? + if ( pCpu->addrmode != DISCPUMODE_16BIT ///@todo correct? && pCpu->ModRM.Bits.Rm == 4 && pCpu->ModRM.Bits.Mod != 3) @@ -1235,10 +1235,10 @@ { case 0xf0: - f = PREFIX_LOCK; + f = DISPREFIX_LOCK; break; case 0xf2: case 0xf3: - f = PREFIX_REP; /* yes, both */ + f = DISPREFIX_REP; /* yes, both */ break; @@ -1249,18 +1249,18 @@ case 0x64: case 0x65: - f = PREFIX_SEG; + f = DISPREFIX_SEG; break; case 0x66: - f = PREFIX_OPSIZE; + f = DISPREFIX_OPSIZE; break; case 0x67: - f = PREFIX_ADDRSIZE; + f = DISPREFIX_ADDRSIZE; break; case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47: case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f: - f = pCpu->mode == CPUMODE_64BIT ? PREFIX_REX : 0; + f = pCpu->mode == DISCPUMODE_64BIT ? DISPREFIX_REX : 0; break; @@ -1277,8 +1277,8 @@ /* segment overrides are fun */ - if (fPrefixes & PREFIX_SEG) + if (fPrefixes & DISPREFIX_SEG) { /* no effective address which it may apply to. */ - Assert((pCpu->prefix & PREFIX_SEG) || pCpu->mode == CPUMODE_64BIT); + Assert((pCpu->prefix & DISPREFIX_SEG) || pCpu->mode == DISCPUMODE_64BIT); if ( !DIS_IS_EFFECTIVE_ADDR(pCpu->param1.flags) && !DIS_IS_EFFECTIVE_ADDR(pCpu->param2.flags) @@ -1288,7 +1288,7 @@ /* fixed register + addr override doesn't go down all that well. */ - if (fPrefixes & PREFIX_ADDRSIZE) - { - Assert(pCpu->prefix & PREFIX_ADDRSIZE); + if (fPrefixes & DISPREFIX_ADDRSIZE) + { + Assert(pCpu->prefix & DISPREFIX_ADDRSIZE); if ( pCpu->pCurInstr->param3 == OP_PARM_NONE && pCpu->pCurInstr->param2 == OP_PARM_NONE @@ -1335,5 +1335,5 @@ /* All but the segment prefix is bad news. */ - if (fPrefixes & ~PREFIX_SEG) + if (fPrefixes & ~DISPREFIX_SEG) { switch (pCpu->pCurInstr->opcode) @@ -1344,5 +1344,5 @@ && pCpu->pCurInstr->param1 <= OP_PARM_REG_SEG_END) return true; - if ( (fPrefixes & ~PREFIX_OPSIZE) + if ( (fPrefixes & ~DISPREFIX_OPSIZE) && pCpu->pCurInstr->param1 >= OP_PARM_REG_GEN32_START && pCpu->pCurInstr->param1 <= OP_PARM_REG_GEN32_END) @@ -1354,5 +1354,5 @@ case OP_PUSHA: case OP_PUSHF: - if (fPrefixes & ~PREFIX_OPSIZE) + if (fPrefixes & ~DISPREFIX_OPSIZE) return true; break; @@ -1361,5 +1361,5 @@ /* Implicit 8-bit register instructions doesn't mix with operand size. */ - if ( (fPrefixes & PREFIX_OPSIZE) + if ( (fPrefixes & DISPREFIX_OPSIZE) && ( ( pCpu->pCurInstr->param1 == OP_PARM_Gb /* r8 */ && pCpu->pCurInstr->param2 == OP_PARM_Eb /* r8/mem8 */) @@ -1506,5 +1506,5 @@ if ( pCpu->pCurInstr->opcode == OP_MOVZX && pCpu->opcode == 0xB7 - && (pCpu->mode == CPUMODE_16BIT) != !!(fPrefixes & PREFIX_OPSIZE)) + && (pCpu->mode == DISCPUMODE_16BIT) != !!(fPrefixes & DISPREFIX_OPSIZE)) return true; Index: /trunk/src/VBox/Disassembler/DisasmReg.cpp =================================================================== --- /trunk/src/VBox/Disassembler/DisasmReg.cpp (revision 41674) +++ /trunk/src/VBox/Disassembler/DisasmReg.cpp (revision 41675) @@ -210,11 +210,11 @@ switch(pCpu->opmode) { - case CPUMODE_32BIT: + case DISCPUMODE_32BIT: subtype = OP_PARM_d; break; - case CPUMODE_64BIT: + case DISCPUMODE_64BIT: subtype = OP_PARM_q; break; - case CPUMODE_16BIT: + case DISCPUMODE_16BIT: subtype = OP_PARM_w; break; @@ -241,8 +241,8 @@ case OP_PARM_p: /* far pointer */ - if (pCpu->addrmode == CPUMODE_32BIT) + if (pCpu->addrmode == DISCPUMODE_32BIT) return 6; /* 16:32 */ else - if (pCpu->addrmode == CPUMODE_64BIT) + if (pCpu->addrmode == DISCPUMODE_64BIT) return 12; /* 16:64 */ else @@ -260,5 +260,5 @@ DISDECL(DIS_SELREG) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam) { - if (pCpu->prefix & PREFIX_SEG) + if (pCpu->prefix & DISPREFIX_SEG) { /* Use specified SEG: prefix. */ @@ -285,5 +285,5 @@ DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu) { - Assert(pCpu->prefix & PREFIX_SEG); + Assert(pCpu->prefix & DISPREFIX_SEG); switch(pCpu->enmPrefixSeg) { @@ -592,8 +592,8 @@ if (pParam->flags & USE_DISPLACEMENT8) { - if (pCpu->mode == CPUMODE_32BIT) + if (pCpu->mode == DISCPUMODE_32BIT) pParamVal->val.val32 += (int32_t)pParam->uDisp.i8; else - if (pCpu->mode == CPUMODE_64BIT) + if (pCpu->mode == DISCPUMODE_64BIT) pParamVal->val.val64 += (int64_t)pParam->uDisp.i8; else @@ -603,8 +603,8 @@ if (pParam->flags & USE_DISPLACEMENT16) { - if (pCpu->mode == CPUMODE_32BIT) + if (pCpu->mode == DISCPUMODE_32BIT) pParamVal->val.val32 += (int32_t)pParam->uDisp.i16; else - if (pCpu->mode == CPUMODE_64BIT) + if (pCpu->mode == DISCPUMODE_64BIT) pParamVal->val.val64 += (int64_t)pParam->uDisp.i16; else @@ -614,5 +614,5 @@ if (pParam->flags & USE_DISPLACEMENT32) { - if (pCpu->mode == CPUMODE_32BIT) + if (pCpu->mode == DISCPUMODE_32BIT) pParamVal->val.val32 += pParam->uDisp.i32; else @@ -622,5 +622,5 @@ if (pParam->flags & USE_DISPLACEMENT64) { - Assert(pCpu->mode == CPUMODE_64BIT); + Assert(pCpu->mode == DISCPUMODE_64BIT); pParamVal->val.val64 += pParam->uDisp.i64; } @@ -628,5 +628,5 @@ if (pParam->flags & USE_RIPDISPLACEMENT32) { - Assert(pCpu->mode == CPUMODE_64BIT); + Assert(pCpu->mode == DISCPUMODE_64BIT); /* Relative to the RIP of the next instruction. */ pParamVal->val.val64 += pParam->uDisp.i32 + pCtx->rip + pCpu->opsize; Index: /trunk/src/VBox/Disassembler/DisasmTest.cpp =================================================================== --- /trunk/src/VBox/Disassembler/DisasmTest.cpp (revision 41674) +++ /trunk/src/VBox/Disassembler/DisasmTest.cpp (revision 41675) @@ -50,5 +50,5 @@ char szOutput[256]; - if (RT_SUCCESS(DISInstrToStr(pbInstr, CPUMODE_32BIT, &cpu, &cb, szOutput, sizeof(szOutput)))) + if (RT_SUCCESS(DISInstrToStr(pbInstr, DISCPUMODE_32BIT, &cpu, &cb, szOutput, sizeof(szOutput)))) { printf("%s", szOutput); @@ -73,5 +73,5 @@ char szOutput[256]; - if (RT_SUCCESS(DISInstrToStr(pbInstr, CPUMODE_64BIT, &cpu, &cb, szOutput, sizeof(szOutput)))) + if (RT_SUCCESS(DISInstrToStr(pbInstr, DISCPUMODE_64BIT, &cpu, &cb, szOutput, sizeof(szOutput)))) printf("%s", szOutput); else Index: /trunk/src/VBox/Disassembler/DisasmTestCore.cpp =================================================================== --- /trunk/src/VBox/Disassembler/DisasmTestCore.cpp (revision 41674) +++ /trunk/src/VBox/Disassembler/DisasmTestCore.cpp (revision 41675) @@ -39,5 +39,5 @@ unsigned cb; DISCPUSTATE cpu; - if (DISInstr((void *)(uintptr_t)&DISInstr, CPUMODE_32BIT, &cpu, &cb)) + if (DISInstr((void *)(uintptr_t)&DISInstr, DISCPUMODE_32BIT, &cpu, &cb)) printf("ok %d\n", cpu.addrmode); else Index: /trunk/src/VBox/Disassembler/testcase/tstDisasm-2.cpp =================================================================== --- /trunk/src/VBox/Disassembler/testcase/tstDisasm-2.cpp (revision 41674) +++ /trunk/src/VBox/Disassembler/testcase/tstDisasm-2.cpp (revision 41675) @@ -303,5 +303,5 @@ case kAsmStyle_yasm: - RTPrintf(" BITS %d\n", enmCpuMode == CPUMODE_16BIT ? 16 : enmCpuMode == CPUMODE_32BIT ? 32 : 64); + RTPrintf(" BITS %d\n", enmCpuMode == DISCPUMODE_16BIT ? 16 : enmCpuMode == DISCPUMODE_32BIT ? 32 : 64); pfnFormatter = MyDisasYasmFormatter; break; @@ -492,5 +492,5 @@ UNDEFOPHANDLING enmUndefOp = kUndefOp_Fail; bool fListing = true; - DISCPUMODE enmCpuMode = CPUMODE_32BIT; + DISCPUMODE enmCpuMode = DISCPUMODE_32BIT; RTFOFF off = 0; RTFOFF cbMax = _1G; @@ -532,9 +532,9 @@ case 'c': if (ValueUnion.u32 == 16) - enmCpuMode = CPUMODE_16BIT; + enmCpuMode = DISCPUMODE_16BIT; else if (ValueUnion.u32 == 32) - enmCpuMode = CPUMODE_32BIT; + enmCpuMode = DISCPUMODE_32BIT; else if (ValueUnion.u32 == 64) - enmCpuMode = CPUMODE_64BIT; + enmCpuMode = DISCPUMODE_64BIT; else { Index: /trunk/src/VBox/Runtime/testcase/tstLdr-2.cpp =================================================================== --- /trunk/src/VBox/Runtime/testcase/tstLdr-2.cpp (revision 41674) +++ /trunk/src/VBox/Runtime/testcase/tstLdr-2.cpp (revision 41675) @@ -47,5 +47,5 @@ char szOutput[256]; uint32_t cbInstr; - if (RT_FAILURE(DISInstrToStr(pbCodeBlock + i, CPUMODE_32BIT, &Cpu, &cbInstr, szOutput, sizeof(szOutput)))) + if (RT_FAILURE(DISInstrToStr(pbCodeBlock + i, DISCPUMODE_32BIT, &Cpu, &cbInstr, szOutput, sizeof(szOutput)))) return false; Index: /trunk/src/VBox/Runtime/testcase/tstLdr-3.cpp =================================================================== --- /trunk/src/VBox/Runtime/testcase/tstLdr-3.cpp (revision 41674) +++ /trunk/src/VBox/Runtime/testcase/tstLdr-3.cpp (revision 41675) @@ -247,7 +247,7 @@ memset(&Cpu, 0, sizeof(Cpu)); #ifdef RT_ARCH_X86 /** @todo select according to the module type. */ - Cpu.mode = CPUMODE_32BIT; + Cpu.mode = DISCPUMODE_32BIT; #else - Cpu.mode = CPUMODE_64BIT; + Cpu.mode = DISCPUMODE_64BIT; #endif uint8_t *pbCode = (uint8_t *)g_pvBits + (NearSym.aSyms[0].Value - g_uLoadAddr); Index: /trunk/src/VBox/Runtime/testcase/tstLdrDisasmTest.cpp =================================================================== --- /trunk/src/VBox/Runtime/testcase/tstLdrDisasmTest.cpp (revision 41674) +++ /trunk/src/VBox/Runtime/testcase/tstLdrDisasmTest.cpp (revision 41675) @@ -105,5 +105,5 @@ { uint32_t cb; - int rc = DISInstrWithReader(CodeIndex, CPUMODE_32BIT, DisasmTest1ReadCode, 0, pCpu, &cb); + int rc = DISInstrWithReader(CodeIndex, DISCPUMODE_32BIT, DisasmTest1ReadCode, 0, pCpu, &cb); *pcb = cb; MY_PRINTF(("DISCoreOneEx -> rc=%d cb=%d Cpu: opcode=%#x pCurInstr=%p (42=%d)\n", \ @@ -122,5 +122,5 @@ memset(&Cpu, 0, sizeof(Cpu)); - Cpu.mode = CPUMODE_32BIT; + Cpu.mode = DISCPUMODE_32BIT; #define DISAS_AND_CHECK(cbInstr, enmOp) \ Index: /trunk/src/VBox/Runtime/testcase/tstLdrObj.cpp =================================================================== --- /trunk/src/VBox/Runtime/testcase/tstLdrObj.cpp (revision 41674) +++ /trunk/src/VBox/Runtime/testcase/tstLdrObj.cpp (revision 41675) @@ -98,5 +98,5 @@ static unsigned cb; DISCPUSTATE Cpu; - DISInstr((void *)(uintptr_t)SomeExportFunction3, CPUMODE_32BIT, &Cpu, &cb); + DISInstr((void *)(uintptr_t)SomeExportFunction3, DISCPUMODE_32BIT, &Cpu, &cb); return (void *)(uintptr_t)&SomeExportFunction1; } Index: /trunk/src/VBox/Runtime/testcase/tstLdrObjR0.cpp =================================================================== --- /trunk/src/VBox/Runtime/testcase/tstLdrObjR0.cpp (revision 41674) +++ /trunk/src/VBox/Runtime/testcase/tstLdrObjR0.cpp (revision 41675) @@ -96,7 +96,7 @@ memset(&Cpu, 0, sizeof(Cpu)); - Cpu.mode = CPUMODE_32BIT; + Cpu.mode = DISCPUMODE_32BIT; - DISInstr((void *)(uintptr_t)SomeExportFunction3, CPUMODE_32BIT, &Cpu, &cb); + DISInstr((void *)(uintptr_t)SomeExportFunction3, DISCPUMODE_32BIT, &Cpu, &cb); return (void *)(uintptr_t)&SomeExportFunction1; } Index: /trunk/src/VBox/VMM/VMMAll/EMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/EMAll.cpp (revision 41674) +++ /trunk/src/VBox/VMM/VMMAll/EMAll.cpp (revision 41675) @@ -789,6 +789,6 @@ case OP_LMSW: return "Lmsw"; case OP_SMSW: return "Smsw"; - case OP_CMPXCHG: return pDis->prefix & PREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg"; - case OP_CMPXCHG8B: return pDis->prefix & PREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b"; + case OP_CMPXCHG: return pDis->prefix & DISPREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg"; + case OP_CMPXCHG8B: return pDis->prefix & DISPREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b"; default: @@ -1009,5 +1009,5 @@ static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) { - Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */ + Assert(pDis->mode != DISCPUMODE_64BIT); /** @todo check */ OP_PARAMVAL param1; NOREF(pvFault); @@ -1028,5 +1028,5 @@ /* Read stack value first */ - if (SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == CPUMODE_16BIT) + if (SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == DISCPUMODE_16BIT) return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */ @@ -1561,5 +1561,5 @@ } #ifdef LOG_ENABLED - if (pDis->mode == CPUMODE_64BIT) + if (pDis->mode == DISCPUMODE_64BIT) LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64)); else @@ -1624,5 +1624,5 @@ } #ifdef LOG_ENABLED - if (pDis->mode == CPUMODE_64BIT) + if (pDis->mode == DISCPUMODE_64BIT) LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size)); else @@ -1652,18 +1652,18 @@ /* Don't support any but these three prefix bytes. */ - if ((pDis->prefix & ~(PREFIX_ADDRSIZE|PREFIX_OPSIZE|PREFIX_REP|PREFIX_REX))) + if ((pDis->prefix & ~(DISPREFIX_ADDRSIZE|DISPREFIX_OPSIZE|DISPREFIX_REP|DISPREFIX_REX))) return VERR_EM_INTERPRETER; switch (pDis->addrmode) { - case CPUMODE_16BIT: + case DISCPUMODE_16BIT: GCOffset = pRegFrame->di; cTransfers = pRegFrame->cx; break; - case CPUMODE_32BIT: + case DISCPUMODE_32BIT: GCOffset = pRegFrame->edi; cTransfers = pRegFrame->ecx; break; - case CPUMODE_64BIT: + case DISCPUMODE_64BIT: GCOffset = pRegFrame->rdi; cTransfers = pRegFrame->rcx; @@ -1677,11 +1677,11 @@ switch (pDis->opmode) { - case CPUMODE_16BIT: + case DISCPUMODE_16BIT: cbSize = 2; break; - case CPUMODE_32BIT: + case DISCPUMODE_32BIT: cbSize = 4; break; - case CPUMODE_64BIT: + case DISCPUMODE_64BIT: cbSize = 8; break; @@ -1693,5 +1693,5 @@ offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize; - if (!(pDis->prefix & PREFIX_REP)) + if (!(pDis->prefix & DISPREFIX_REP)) { LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize)); @@ -1705,11 +1705,11 @@ switch (pDis->addrmode) { - case CPUMODE_16BIT: + case DISCPUMODE_16BIT: pRegFrame->di += offIncrement; break; - case CPUMODE_32BIT: + case DISCPUMODE_32BIT: pRegFrame->edi += offIncrement; break; - case CPUMODE_64BIT: + case DISCPUMODE_64BIT: pRegFrame->rdi += offIncrement; break; @@ -1770,13 +1770,13 @@ switch (pDis->addrmode) { - case CPUMODE_16BIT: + case DISCPUMODE_16BIT: pRegFrame->di = GCOffset; pRegFrame->cx = cTransfers; break; - case CPUMODE_32BIT: + case DISCPUMODE_32BIT: pRegFrame->edi = GCOffset; pRegFrame->ecx = cTransfers; break; - case CPUMODE_64BIT: + case DISCPUMODE_64BIT: pRegFrame->rdi = GCOffset; pRegFrame->rcx = cTransfers; @@ -1848,5 +1848,5 @@ LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar)); - if (pDis->prefix & PREFIX_LOCK) + if (pDis->prefix & DISPREFIX_LOCK) eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->param2.cb); else @@ -1870,5 +1870,5 @@ static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) { - Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */ + Assert(pDis->mode != DISCPUMODE_64BIT); /** @todo check */ OP_PARAMVAL param1; NOREF(pvFault); @@ -1901,5 +1901,5 @@ LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax)); - if (pDis->prefix & PREFIX_LOCK) + if (pDis->prefix & DISPREFIX_LOCK) eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx); else @@ -1924,5 +1924,5 @@ static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) { - Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */ + Assert(pDis->mode != DISCPUMODE_64BIT); /** @todo check */ OP_PARAMVAL param1; void *pvParamReg2; @@ -1970,5 +1970,5 @@ LogFlow(("XAdd %RGv=%p reg=%08llx\n", GCPtrPar1, pvParam1, *(uint64_t *)pvParamReg2)); - if (pDis->prefix & PREFIX_LOCK) + if (pDis->prefix & DISPREFIX_LOCK) eflags = EMEmulateLockXAdd(pvParam1, pvParamReg2, cbParamReg2); else @@ -2654,5 +2654,5 @@ AssertRCReturn(rc, VERR_EM_INTERPRETER); - if (!(pDis->prefix & PREFIX_OPSIZE)) + if (!(pDis->prefix & DISPREFIX_OPSIZE)) dtr32.uAddr &= 0xffffff; /* 16 bits operand size */ @@ -3030,5 +3030,5 @@ /* Note: The Intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */ - Assert(!(pDis->prefix & PREFIX_REX)); + Assert(!(pDis->prefix & DISPREFIX_REX)); NOREF(pDis); NOREF(pvFault); NOREF(pcbSize); return EMInterpretRdmsr(pVM, pVCpu, pRegFrame); @@ -3104,6 +3104,6 @@ #ifdef IN_RC - if ( (pDis->prefix & (PREFIX_REPNE | PREFIX_REP)) - || ( (pDis->prefix & PREFIX_LOCK) + if ( (pDis->prefix & (DISPREFIX_REPNE | DISPREFIX_REP)) + || ( (pDis->prefix & DISPREFIX_LOCK) && pDis->pCurInstr->opcode != OP_CMPXCHG && pDis->pCurInstr->opcode != OP_CMPXCHG8B @@ -3116,9 +3116,9 @@ ) #else - if ( (pDis->prefix & PREFIX_REPNE) - || ( (pDis->prefix & PREFIX_REP) + if ( (pDis->prefix & DISPREFIX_REPNE) + || ( (pDis->prefix & DISPREFIX_REP) && pDis->pCurInstr->opcode != OP_STOSWD ) - || ( (pDis->prefix & PREFIX_LOCK) + || ( (pDis->prefix & DISPREFIX_LOCK) && pDis->pCurInstr->opcode != OP_OR && pDis->pCurInstr->opcode != OP_AND @@ -3228,5 +3228,5 @@ # define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \ case opcode:\ - if (pDis->prefix & PREFIX_LOCK) \ + if (pDis->prefix & DISPREFIX_LOCK) \ rc = emInterpretLock##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \ else \ Index: /trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp (revision 41674) +++ /trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp (revision 41675) @@ -670,5 +670,5 @@ * We do not support segment prefixes or REPNE. */ - if (pCpu->prefix & (PREFIX_SEG | PREFIX_REPNE)) + if (pCpu->prefix & (DISPREFIX_SEG | DISPREFIX_REPNE)) return VINF_IOM_R3_MMIO_READ_WRITE; /** @todo -> interpret whatever. */ @@ -679,5 +679,5 @@ */ uint32_t cTransfers = 1; - if (pCpu->prefix & PREFIX_REP) + if (pCpu->prefix & DISPREFIX_REP) { #ifndef IN_RC @@ -688,5 +688,5 @@ cTransfers = pRegFrame->ecx; - if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid) == CPUMODE_16BIT) + if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid) == DISCPUMODE_16BIT) cTransfers &= 0xffff; @@ -767,5 +767,5 @@ #endif /* Update ecx. */ - if (pCpu->prefix & PREFIX_REP) + if (pCpu->prefix & DISPREFIX_REP) pRegFrame->ecx = cTransfers; } @@ -875,5 +875,5 @@ /* Update ecx on exit. */ - if (pCpu->prefix & PREFIX_REP) + if (pCpu->prefix & DISPREFIX_REP) pRegFrame->ecx = cTransfers; } @@ -898,7 +898,7 @@ switch (enmCpuMode) { - case CPUMODE_16BIT: return UINT16_MAX; - case CPUMODE_32BIT: return UINT32_MAX; - case CPUMODE_64BIT: return UINT64_MAX; + case DISCPUMODE_16BIT: return UINT16_MAX; + case DISCPUMODE_32BIT: return UINT32_MAX; + case DISCPUMODE_64BIT: return UINT64_MAX; default: AssertFailedReturn(UINT32_MAX); @@ -928,5 +928,5 @@ * We do not support segment prefixes or REPNE.. */ - if (pCpu->prefix & (PREFIX_SEG | PREFIX_REPNE)) + if (pCpu->prefix & (DISPREFIX_SEG | DISPREFIX_REPNE)) return VINF_IOM_R3_MMIO_READ_WRITE; /** @todo -> REM instead of HC */ @@ -936,5 +936,5 @@ uint64_t const fAddrMask = iomDisModeToMask(pCpu->addrmode); RTGCUINTREG cTransfers = 1; - if (pCpu->prefix & PREFIX_REP) + if (pCpu->prefix & DISPREFIX_REP) { #ifndef IN_RC @@ -983,5 +983,5 @@ pRegFrame->rdi = ((pRegFrame->rdi + (cTransfers << SIZE_2_SHIFT(cb))) & fAddrMask) | (pRegFrame->rdi & ~fAddrMask); - if (pCpu->prefix & PREFIX_REP) + if (pCpu->prefix & DISPREFIX_REP) pRegFrame->rcx &= ~fAddrMask; } @@ -998,5 +998,5 @@ pRegFrame->rdi = ((pRegFrame->rdi - (cTransfers << SIZE_2_SHIFT(cb))) & fAddrMask) | (pRegFrame->rdi & ~fAddrMask); - if (pCpu->prefix & PREFIX_REP) + if (pCpu->prefix & DISPREFIX_REP) pRegFrame->rcx &= ~fAddrMask; } @@ -1025,5 +1025,5 @@ /* Update rcx on exit. */ - if (pCpu->prefix & PREFIX_REP) + if (pCpu->prefix & DISPREFIX_REP) pRegFrame->rcx = (cTransfers & fAddrMask) | (pRegFrame->rcx & ~fAddrMask); @@ -1062,5 +1062,5 @@ * We do not support segment prefixes or REP*. */ - if (pCpu->prefix & (PREFIX_SEG | PREFIX_REP | PREFIX_REPNE)) + if (pCpu->prefix & (DISPREFIX_SEG | DISPREFIX_REP | DISPREFIX_REPNE)) return VINF_IOM_R3_MMIO_READ_WRITE; /** @todo -> REM instead of HC */ @@ -2030,5 +2030,5 @@ * pointer. Segment prefixes are deliberately ignored, as per the instruction specification. */ - if ( (uPrefix & PREFIX_REPNE) + if ( (uPrefix & DISPREFIX_REPNE) || pRegFrame->eflags.Bits.u1DF) return VINF_EM_RAW_EMULATE_INSTR; @@ -2041,5 +2041,5 @@ uint64_t const fAddrMask = iomDisModeToMask(enmAddrMode); RTGCUINTREG cTransfers = 1; - if (uPrefix & PREFIX_REP) + if (uPrefix & DISPREFIX_REP) { #ifndef IN_RC @@ -2108,5 +2108,5 @@ /* Update rcx on exit. */ - if (uPrefix & PREFIX_REP) + if (uPrefix & DISPREFIX_REP) pRegFrame->rcx = (cTransfers & fAddrMask) | (pRegFrame->rcx & ~fAddrMask); @@ -2147,5 +2147,5 @@ cb = 1; else - cb = (pCpu->opmode == CPUMODE_16BIT) ? 2 : 4; /* dword in both 32 & 64 bits mode */ + cb = (pCpu->opmode == DISCPUMODE_16BIT) ? 2 : 4; /* dword in both 32 & 64 bits mode */ VBOXSTRICTRC rcStrict = IOMInterpretCheckPortIOAccess(pVM, pRegFrame, Port, cb); @@ -2192,5 +2192,5 @@ * decrementing source pointer. */ - if ( (uPrefix & (PREFIX_SEG | PREFIX_REPNE)) + if ( (uPrefix & (DISPREFIX_SEG | DISPREFIX_REPNE)) || pRegFrame->eflags.Bits.u1DF) return VINF_EM_RAW_EMULATE_INSTR; @@ -2203,5 +2203,5 @@ uint64_t const fAddrMask = iomDisModeToMask(enmAddrMode); RTGCUINTREG cTransfers = 1; - if (uPrefix & PREFIX_REP) + if (uPrefix & DISPREFIX_REP) { #ifndef IN_RC @@ -2275,5 +2275,5 @@ /* Update rcx on exit. */ - if (uPrefix & PREFIX_REP) + if (uPrefix & DISPREFIX_REP) pRegFrame->rcx = (cTransfers & fAddrMask) | (pRegFrame->rcx & ~fAddrMask); @@ -2316,5 +2316,5 @@ cb = 1; else - cb = (pCpu->opmode == CPUMODE_16BIT) ? 2 : 4; /* dword in both 32 & 64 bits mode */ + cb = (pCpu->opmode == DISCPUMODE_16BIT) ? 2 : 4; /* dword in both 32 & 64 bits mode */ VBOXSTRICTRC rcStrict = IOMInterpretCheckPortIOAccess(pVM, pRegFrame, Port, cb); Index: /trunk/src/VBox/VMM/VMMAll/PGMAllBth.h =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PGMAllBth.h (revision 41674) +++ /trunk/src/VBox/VMM/VMMAll/PGMAllBth.h (revision 41675) @@ -918,5 +918,5 @@ if ( rc == VINF_SUCCESS && pDis->pCurInstr->opcode == OP_MOVSWD - && (pDis->prefix & PREFIX_REP)) + && (pDis->prefix & DISPREFIX_REP)) { CSAMMarkPossibleCodePage(pVM, pvFault); Index: /trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp (revision 41674) +++ /trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp (revision 41675) @@ -107,6 +107,6 @@ rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, pDis, &cbOp); if ( RT_SUCCESS(rc) - && pDis->mode == CPUMODE_32BIT /** @todo why does this matter? */ - && !(pDis->prefix & (PREFIX_REPNE | PREFIX_REP | PREFIX_SEG))) + && pDis->mode == DISCPUMODE_32BIT /** @todo why does this matter? */ + && !(pDis->prefix & (DISPREFIX_REPNE | DISPREFIX_REP | DISPREFIX_SEG))) { switch (pDis->opcode) Index: /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp (revision 41674) +++ /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp (revision 41675) @@ -793,9 +793,9 @@ case OP_MOVSWD: case OP_STOSWD: - if ( pDis->prefix == (PREFIX_REP|PREFIX_REX) + if ( pDis->prefix == (DISPREFIX_REP|DISPREFIX_REX) && pRegFrame->rcx >= 0x40 ) { - Assert(pDis->mode == CPUMODE_64BIT); + Assert(pDis->mode == DISCPUMODE_64BIT); Log(("pgmPoolMonitorIsReused: OP_STOSQ\n")); @@ -890,9 +890,9 @@ NOREF(pVM); - Assert(pDis->mode == CPUMODE_32BIT || pDis->mode == CPUMODE_64BIT); + Assert(pDis->mode == DISCPUMODE_32BIT || pDis->mode == DISCPUMODE_64BIT); Assert(pRegFrame->rcx <= 0x20); #ifdef VBOX_STRICT - if (pDis->opmode == CPUMODE_32BIT) + if (pDis->opmode == DISCPUMODE_32BIT) Assert(uIncrement == 4); else @@ -1155,5 +1155,5 @@ * Simple instructions, no REP prefix. */ - if (!(pDis->prefix & (PREFIX_REP | PREFIX_REPNE))) + if (!(pDis->prefix & (DISPREFIX_REP | DISPREFIX_REPNE))) { rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault, &fReused); @@ -1203,6 +1203,6 @@ bool fValidStosd = false; - if ( pDis->mode == CPUMODE_32BIT - && pDis->prefix == PREFIX_REP + if ( pDis->mode == DISCPUMODE_32BIT + && pDis->prefix == DISPREFIX_REP && pRegFrame->ecx <= 0x20 && pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK) @@ -1215,6 +1215,6 @@ } else - if ( pDis->mode == CPUMODE_64BIT - && pDis->prefix == (PREFIX_REP | PREFIX_REX) + if ( pDis->mode == DISCPUMODE_64BIT + && pDis->prefix == (DISPREFIX_REP | DISPREFIX_REX) && pRegFrame->rcx <= 0x20 && pRegFrame->rcx * 8 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK) Index: /trunk/src/VBox/VMM/VMMAll/SELMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/SELMAll.cpp (revision 41674) +++ /trunk/src/VBox/VMM/VMMAll/SELMAll.cpp (revision 41675) @@ -911,5 +911,5 @@ Desc = paLDT[Sel >> X86_SEL_SHIFT]; } - return (Desc.Gen.u1DefBig) ? CPUMODE_32BIT : CPUMODE_16BIT; + return (Desc.Gen.u1DefBig) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT; } #endif /* !IN_RING0 */ @@ -938,5 +938,5 @@ if ( eflags.Bits.u1VM || CPUMIsGuestInRealMode(pVCpu)) - return CPUMODE_16BIT; + return DISCPUMODE_16BIT; return selmGetCpuModeFromSelector(pVCpu->CTX_SUFF(pVM), pVCpu, Sel); @@ -945,8 +945,8 @@ if ( pHiddenSel->Attr.n.u1Long && CPUMIsGuestInLongMode(pVCpu)) - return CPUMODE_64BIT; + return DISCPUMODE_64BIT; /* Else compatibility or 32 bits mode. */ - return pHiddenSel->Attr.n.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT; + return pHiddenSel->Attr.n.u1DefBig ? DISCPUMODE_32BIT : DISCPUMODE_16BIT; } Index: /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp (revision 41674) +++ /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp (revision 41675) @@ -2972,5 +2972,5 @@ */ DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVCpu, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid); - if (enmMode != CPUMODE_16BIT) + if (enmMode != DISCPUMODE_16BIT) { RTGCPTR pbCode; Index: /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (revision 41674) +++ /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (revision 41675) @@ -3585,5 +3585,5 @@ X86EFLAGS eflags; - if (pDis->prefix & PREFIX_OPSIZE) + if (pDis->prefix & DISPREFIX_OPSIZE) { cbParm = 4; @@ -3627,5 +3627,5 @@ X86EFLAGS eflags; - if (pDis->prefix & PREFIX_OPSIZE) + if (pDis->prefix & DISPREFIX_OPSIZE) { cbParm = 4; @@ -3669,5 +3669,5 @@ uint16_t aIretFrame[3]; - if (pDis->prefix & (PREFIX_OPSIZE | PREFIX_ADDRSIZE)) + if (pDis->prefix & (DISPREFIX_OPSIZE | DISPREFIX_ADDRSIZE)) { rc = VERR_EM_INTERPRETER; Index: /trunk/src/VBox/VMM/VMMR3/CPUM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/CPUM.cpp (revision 41674) +++ /trunk/src/VBox/VMM/VMMR3/CPUM.cpp (revision 41675) @@ -3631,8 +3631,8 @@ State.cbSegLimit = pCtx->csHid.u32Limit; enmDisCpuMode = (State.f64Bits) - ? CPUMODE_64BIT + ? DISCPUMODE_64BIT : pCtx->csHid.Attr.n.u1DefBig - ? CPUMODE_32BIT - : CPUMODE_16BIT; + ? DISCPUMODE_32BIT + : DISCPUMODE_16BIT; } else @@ -3659,5 +3659,5 @@ State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase; State.cbSegLimit = SelInfo.cbLimit; - enmDisCpuMode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT; + enmDisCpuMode = SelInfo.u.Raw.Gen.u1DefBig ? DISCPUMODE_32BIT : DISCPUMODE_16BIT; } } @@ -3665,5 +3665,5 @@ { /* real or V86 mode */ - enmDisCpuMode = CPUMODE_16BIT; + enmDisCpuMode = DISCPUMODE_16BIT; State.GCPtrSegBase = pCtx->cs * 16; State.GCPtrSegEnd = 0xFFFFFFFF; Index: /trunk/src/VBox/VMM/VMMR3/CSAM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/CSAM.cpp (revision 41674) +++ /trunk/src/VBox/VMM/VMMR3/CSAM.cpp (revision 41675) @@ -870,5 +870,5 @@ Assert(VALID_PTR(pCurInstrHC)); - rc = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, (fCode32) ? CPUMODE_32BIT : CPUMODE_16BIT, + rc = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, (fCode32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, &cpu, &opsize, NULL, 0); } @@ -1053,9 +1053,9 @@ STAM_PROFILE_START(&pVM->csam.s.StatTimeDisasm, a); #ifdef DEBUG - rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, (fCode32) ? CPUMODE_32BIT : CPUMODE_16BIT, + rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, (fCode32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, &cpu, &opsize, szOutput, sizeof(szOutput)); if (RT_SUCCESS(rc2)) Log(("CSAM Call Analysis: %s", szOutput)); #else - rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, (fCode32) ? CPUMODE_32BIT : CPUMODE_16BIT, + rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, (fCode32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, &cpu, &opsize, NULL, 0); #endif @@ -1266,9 +1266,9 @@ STAM_PROFILE_START(&pVM->csam.s.StatTimeDisasm, a); #ifdef DEBUG - rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, fCode32 ? CPUMODE_32BIT : CPUMODE_16BIT, + rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, fCode32 ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, &cpu, &opsize, szOutput, sizeof(szOutput)); if (RT_SUCCESS(rc2)) Log(("CSAM Analysis: %s", szOutput)); #else - rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, fCode32 ? CPUMODE_32BIT : CPUMODE_16BIT, + rc2 = CSAMR3DISInstr(pVM, pCurInstrGC, pCurInstrHC, fCode32 ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, &cpu, &opsize, NULL, 0); #endif @@ -2261,5 +2261,5 @@ { /* Assuming 32 bits code for now. */ - Assert(SELMGetCpuModeFromSelector(VMMGetCpu0(pVM), pCtxCore->eflags, pCtxCore->cs, &pCtxCore->csHid) == CPUMODE_32BIT); + Assert(SELMGetCpuModeFromSelector(VMMGetCpu0(pVM), pCtxCore->eflags, pCtxCore->cs, &pCtxCore->csHid) == DISCPUMODE_32BIT); pInstrGC = SELMToFlat(pVM, DIS_SELREG_CS, pCtxCore, pInstrGC); Index: /trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp (revision 41674) +++ /trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp (revision 41675) @@ -122,18 +122,18 @@ case DBGF_DISAS_FLAGS_DEFAULT_MODE: enmCpuMode = pState->f64Bits - ? CPUMODE_64BIT + ? DISCPUMODE_64BIT : pSelInfo->u.Raw.Gen.u1DefBig - ? CPUMODE_32BIT - : CPUMODE_16BIT; + ? DISCPUMODE_32BIT + : DISCPUMODE_16BIT; break; case DBGF_DISAS_FLAGS_16BIT_MODE: case DBGF_DISAS_FLAGS_16BIT_REAL_MODE: - enmCpuMode = CPUMODE_16BIT; + enmCpuMode = DISCPUMODE_16BIT; break; case DBGF_DISAS_FLAGS_32BIT_MODE: - enmCpuMode = CPUMODE_32BIT; + enmCpuMode = DISCPUMODE_32BIT; break; case DBGF_DISAS_FLAGS_64BIT_MODE: - enmCpuMode = CPUMODE_64BIT; + enmCpuMode = DISCPUMODE_64BIT; break; } Index: /trunk/src/VBox/VMM/VMMR3/EMHwaccm.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/EMHwaccm.cpp (revision 41674) +++ /trunk/src/VBox/VMM/VMMR3/EMHwaccm.cpp (revision 41675) @@ -307,5 +307,5 @@ rcStrict = VINF_EM_RAW_EMULATE_INSTR; - if (!(Cpu.prefix & (PREFIX_REP | PREFIX_REPNE))) + if (!(Cpu.prefix & (DISPREFIX_REP | DISPREFIX_REPNE))) { switch (Cpu.pCurInstr->opcode) @@ -326,5 +326,5 @@ } } - else if (Cpu.prefix & PREFIX_REP) + else if (Cpu.prefix & DISPREFIX_REP) { switch (Cpu.pCurInstr->opcode) Index: /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp (revision 41674) +++ /trunk/src/VBox/VMM/VMMR3/EMRaw.cpp (revision 41675) @@ -428,5 +428,5 @@ VBOXSTRICTRC rcStrict = VINF_EM_RAW_EMULATE_INSTR; - if (!(Cpu.prefix & (PREFIX_REP | PREFIX_REPNE))) + if (!(Cpu.prefix & (DISPREFIX_REP | DISPREFIX_REPNE))) { switch (Cpu.pCurInstr->opcode) @@ -447,5 +447,5 @@ } } - else if (Cpu.prefix & PREFIX_REP) + else if (Cpu.prefix & DISPREFIX_REP) { switch (Cpu.pCurInstr->opcode) @@ -684,5 +684,5 @@ { rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip), - (SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0); + (SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == DISCPUMODE_32BIT) ? PATMFL_CODE32 : 0); if (RT_SUCCESS(rc)) { @@ -934,5 +934,5 @@ { int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip), - (SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0); + (SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == DISCPUMODE_32BIT) ? PATMFL_CODE32 : 0); if (RT_SUCCESS(rc)) { @@ -1041,5 +1041,5 @@ if ( (pCtx->ss & X86_SEL_RPL) == 0 && !pCtx->eflags.Bits.u1VM - && SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) + && SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == DISCPUMODE_32BIT) { STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a); Index: /trunk/src/VBox/VMM/VMMR3/PATM.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/PATM.cpp (revision 41674) +++ /trunk/src/VBox/VMM/VMMR3/PATM.cpp (revision 41675) @@ -604,5 +604,5 @@ disinfo.fReadFlags = fReadFlags; return RT_SUCCESS(DISInstrToStrWithReader(InstrGCPtr32, - (pPatch->flags & PATMFL_CODE32) ? CPUMODE_32BIT : CPUMODE_16BIT, + (pPatch->flags & PATMFL_CODE32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, patmReadBytes, &disinfo, pCpu, pcbInstr, pszOutput, cbOutput)); @@ -620,5 +620,5 @@ disinfo.fReadFlags = fReadFlags; return RT_SUCCESS(DISInstrWithReader(InstrGCPtr32, - (pPatch->flags & PATMFL_CODE32) ? CPUMODE_32BIT : CPUMODE_16BIT, + (pPatch->flags & PATMFL_CODE32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT, patmReadBytes, &disinfo, pCpu, pcbInstr)); @@ -1654,5 +1654,5 @@ */ Log(("patmRecompileCallback: jump to code we've recompiled before %RRv!\n", pCurInstrGC)); - return patmPatchGenRelJump(pVM, pPatch, pCurInstrGC, OP_JMP, !!(pCpu->prefix & PREFIX_OPSIZE)); + return patmPatchGenRelJump(pVM, pPatch, pCurInstrGC, OP_JMP, !!(pCpu->prefix & DISPREFIX_OPSIZE)); } @@ -1713,5 +1713,5 @@ } else - rc = patmPatchGenRelJump(pVM, pPatch, pTargetGC, pCpu->pCurInstr->opcode, !!(pCpu->prefix & PREFIX_OPSIZE)); + rc = patmPatchGenRelJump(pVM, pPatch, pTargetGC, pCpu->pCurInstr->opcode, !!(pCpu->prefix & DISPREFIX_OPSIZE)); if (RT_SUCCESS(rc)) @@ -1855,5 +1855,5 @@ fGenerateJmpBack = false; - rc = patmPatchGenPopf(pVM, pPatch, pCurInstrGC + pCpu->opsize, !!(pCpu->prefix & PREFIX_OPSIZE), fGenerateJmpBack); + rc = patmPatchGenPopf(pVM, pPatch, pCurInstrGC + pCpu->opsize, !!(pCpu->prefix & DISPREFIX_OPSIZE), fGenerateJmpBack); if (RT_SUCCESS(rc)) { @@ -1873,5 +1873,5 @@ case OP_PUSHF: - rc = patmPatchGenPushf(pVM, pPatch, !!(pCpu->prefix & PREFIX_OPSIZE)); + rc = patmPatchGenPushf(pVM, pPatch, !!(pCpu->prefix & DISPREFIX_OPSIZE)); if (RT_SUCCESS(rc)) rc = VWRN_CONTINUE_RECOMPILE; @@ -1890,5 +1890,5 @@ case OP_IRET: Log(("IRET at %RRv\n", pCurInstrGC)); - rc = patmPatchGenIret(pVM, pPatch, pCurInstrGC, !!(pCpu->prefix & PREFIX_OPSIZE)); + rc = patmPatchGenIret(pVM, pPatch, pCurInstrGC, !!(pCpu->prefix & DISPREFIX_OPSIZE)); if (RT_SUCCESS(rc)) { @@ -3217,5 +3217,5 @@ pPatch->uCurPatchOffset = 0; - cpu.mode = (pPatch->flags & PATMFL_CODE32) ? CPUMODE_32BIT : CPUMODE_16BIT; + cpu.mode = (pPatch->flags & PATMFL_CODE32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT; /* Note: Set the PATM interrupt flag here; it was cleared before the patched call. (!!!) */ @@ -4212,5 +4212,5 @@ pPatchRec->patch.pPrivInstrGC = pInstrGC; pPatchRec->patch.flags = flags; - pPatchRec->patch.uOpMode = (flags & PATMFL_CODE32) ? CPUMODE_32BIT : CPUMODE_16BIT; + pPatchRec->patch.uOpMode = (flags & PATMFL_CODE32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT; pPatchRec->patch.pTrampolinePatchesHead = NULL; @@ -6457,5 +6457,5 @@ if (disret && (cpu.pCurInstr->opcode == OP_SYSEXIT || cpu.pCurInstr->opcode == OP_HLT || cpu.pCurInstr->opcode == OP_INT3)) { - cpu.mode = (pPatch->patch.flags & PATMFL_CODE32) ? CPUMODE_32BIT : CPUMODE_16BIT; + cpu.mode = (pPatch->patch.flags & PATMFL_CODE32) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT; disret = patmR3DisInstr(pVM, &pPatch->patch, pNewEip, PATMGCVirtToHCVirt(pVM, &cacheRec, pNewEip), PATMREAD_RAWCODE, &cpu, &opsize); Index: /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp (revision 41674) +++ /trunk/src/VBox/VMM/VMMR3/PATMPatch.cpp (revision 41675) @@ -701,12 +701,12 @@ offset = 0; /* include prefix byte to make sure we don't use the incorrect selector register. */ - if (pCpu->prefix & PREFIX_SEG) + if (pCpu->prefix & DISPREFIX_SEG) pPB[offset++] = DISQuerySegPrefixByte(pCpu); pPB[offset++] = 0xFF; // push r/m32 pPB[offset++] = MAKE_MODRM(pCpu->ModRM.Bits.Mod, 6 /* group 5 */, pCpu->ModRM.Bits.Rm); i = 2; /* standard offset of modrm bytes */ - if (pCpu->prefix & PREFIX_OPSIZE) + if (pCpu->prefix & DISPREFIX_OPSIZE) i++; //skip operand prefix - if (pCpu->prefix & PREFIX_SEG) + if (pCpu->prefix & DISPREFIX_SEG) i++; //skip segment prefix @@ -797,5 +797,5 @@ offset = 0; /* include prefix byte to make sure we don't use the incorrect selector register. */ - if (pCpu->prefix & PREFIX_SEG) + if (pCpu->prefix & DISPREFIX_SEG) pPB[offset++] = DISQuerySegPrefixByte(pCpu); @@ -803,7 +803,7 @@ pPB[offset++] = MAKE_MODRM(pCpu->ModRM.Bits.Mod, 6 /* group 5 */, pCpu->ModRM.Bits.Rm); i = 2; /* standard offset of modrm bytes */ - if (pCpu->prefix & PREFIX_OPSIZE) + if (pCpu->prefix & DISPREFIX_OPSIZE) i++; //skip operand prefix - if (pCpu->prefix & PREFIX_SEG) + if (pCpu->prefix & DISPREFIX_SEG) i++; //skip segment prefix @@ -1276,5 +1276,5 @@ PATCHGEN_PROLOG_NODEF(pVM, pPatch); offset = 0; - if (pCpu->prefix & PREFIX_OPSIZE) + if (pCpu->prefix & DISPREFIX_OPSIZE) pPB[offset++] = 0x66; /* size override -> 16 bits push */ pPB[offset++] = 0x16; @@ -1289,5 +1289,5 @@ PATCHGEN_PROLOG_NODEF(pVM, pPatch); offset = 0; - if (pCpu->prefix & PREFIX_OPSIZE) + if (pCpu->prefix & DISPREFIX_OPSIZE) pPB[offset++] = 0x66; /* size override -> 16 bits pop */ pPB[offset++] = 0x58 + pCpu->param1.base.reg_gen; @@ -1320,5 +1320,5 @@ /** @todo segment prefix (untested) */ - Assert(pCpu->prefix == PREFIX_NONE || pCpu->prefix == PREFIX_OPSIZE); + Assert(pCpu->prefix == DISPREFIX_NONE || pCpu->prefix == DISPREFIX_OPSIZE); PATCHGEN_PROLOG(pVM, pPatch); @@ -1329,5 +1329,5 @@ // 8B 15 [32 bits addr] mov edx, CPUMCTX.tr/ldtr - if (pCpu->prefix == PREFIX_OPSIZE) + if (pCpu->prefix == DISPREFIX_OPSIZE) pPB[offset++] = 0x66; @@ -1360,5 +1360,5 @@ pPB[offset++] = 0x52; // push edx - if (pCpu->prefix == PREFIX_SEG) + if (pCpu->prefix == DISPREFIX_SEG) { pPB[offset++] = DISQuerySegPrefixByte(pCpu); @@ -1369,7 +1369,7 @@ i = 3; /* standard offset of modrm bytes */ - if (pCpu->prefix == PREFIX_OPSIZE) + if (pCpu->prefix == DISPREFIX_OPSIZE) i++; //skip operand prefix - if (pCpu->prefix == PREFIX_SEG) + if (pCpu->prefix == DISPREFIX_SEG) i++; //skip segment prefix @@ -1420,5 +1420,5 @@ /* @todo segment prefix (untested) */ - Assert(pCpu->prefix == PREFIX_NONE); + Assert(pCpu->prefix == DISPREFIX_NONE); // sgdt %Ms @@ -1455,5 +1455,5 @@ pPB[offset++] = 0x52; // push edx - if (pCpu->prefix == PREFIX_SEG) + if (pCpu->prefix == DISPREFIX_SEG) { pPB[offset++] = DISQuerySegPrefixByte(pCpu); @@ -1464,7 +1464,7 @@ i = 3; /* standard offset of modrm bytes */ - if (pCpu->prefix == PREFIX_OPSIZE) + if (pCpu->prefix == DISPREFIX_OPSIZE) i++; //skip operand prefix - if (pCpu->prefix == PREFIX_SEG) + if (pCpu->prefix == DISPREFIX_SEG) i++; //skip segment prefix rc = patmPatchReadBytes(pVM, &pPB[offset], (RTRCPTR)((RTGCUINTPTR32)pCurInstrGC + i), pCpu->opsize - i); Index: /trunk/src/VBox/VMM/VMMR3/VMMSwitcher.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/VMMSwitcher.cpp (revision 41674) +++ /trunk/src/VBox/VMM/VMMR3/VMMSwitcher.cpp (revision 41675) @@ -835,5 +835,5 @@ DISCPUSTATE Cpu; char szDisas[256]; - int rc = DISInstr(pu8CodeR3 + offCode, CPUMODE_32BIT, &Cpu, &cbInstr); + int rc = DISInstr(pu8CodeR3 + offCode, DISCPUMODE_32BIT, &Cpu, &cbInstr); if (RT_SUCCESS(rc)) { Index: /trunk/src/VBox/VMM/VMMRC/PATMRC.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMRC/PATMRC.cpp (revision 41674) +++ /trunk/src/VBox/VMM/VMMRC/PATMRC.cpp (revision 41675) @@ -511,5 +511,5 @@ cpu.mode = SELMGetCpuModeFromSelector(VMMGetCpu0(pVM), pRegFrame->eflags, pRegFrame->cs, 0); - if (cpu.mode != CPUMODE_32BIT) + if (cpu.mode != DISCPUMODE_32BIT) { AssertFailed(); Index: /trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp (revision 41674) +++ /trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp (revision 41675) @@ -542,5 +542,5 @@ * Speed up dtrace and don't entrust invalid lock sequences to the recompiler. */ - else if (Cpu.prefix & PREFIX_LOCK) + else if (Cpu.prefix & DISPREFIX_LOCK) { Log(("TRPMGCTrap06Handler: pc=%08x op=%d\n", pRegFrame->eip, Cpu.pCurInstr->opcode)); Index: /trunk/src/VBox/VMM/include/EMHandleRCTmpl.h =================================================================== --- /trunk/src/VBox/VMM/include/EMHandleRCTmpl.h (revision 41674) +++ /trunk/src/VBox/VMM/include/EMHandleRCTmpl.h (revision 41675) @@ -112,5 +112,5 @@ case VINF_PATM_HC_MMIO_PATCH_READ: rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip), - PATMFL_MMIO_ACCESS | ((SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0)); + PATMFL_MMIO_ACCESS | ((SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == DISCPUMODE_32BIT) ? PATMFL_CODE32 : 0)); if (RT_FAILURE(rc)) rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO"); Index: /trunk/src/VBox/VMM/testcase/tstCompiler.cpp =================================================================== --- /trunk/src/VBox/VMM/testcase/tstCompiler.cpp (revision 41674) +++ /trunk/src/VBox/VMM/testcase/tstCompiler.cpp (revision 41675) @@ -207,5 +207,5 @@ char sz[256]; uint32_t cbInstr = 0; - if (RT_SUCCESS(DISInstrToStr(pbCur, CPUMODE_32BIT, &Cpu, &cbInstr, sz, sizeof(sz)))) + if (RT_SUCCESS(DISInstrToStr(pbCur, DISCPUMODE_32BIT, &Cpu, &cbInstr, sz, sizeof(sz)))) { RTPrintf("tstBitFields: %s", sz); Index: /trunk/src/recompiler/VBoxRecompiler.c =================================================================== --- /trunk/src/recompiler/VBoxRecompiler.c (revision 41674) +++ /trunk/src/recompiler/VBoxRecompiler.c (revision 41675) @@ -4072,7 +4072,7 @@ DISCPUSTATE Cpu; #ifdef RT_ARCH_X86 - DISCPUMODE enmCpuMode = CPUMODE_32BIT; + DISCPUMODE enmCpuMode = DISCPUMODE_32BIT; #else - DISCPUMODE enmCpuMode = CPUMODE_64BIT; + DISCPUMODE enmCpuMode = DISCPUMODE_64BIT; #endif