Index: /trunk/src/VBox/VMM/VMMAll/PGMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PGMAll.cpp (revision 41390) +++ /trunk/src/VBox/VMM/VMMAll/PGMAll.cpp (revision 41391) @@ -1847,4 +1847,5 @@ break; } + PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3); if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3) @@ -1949,4 +1950,6 @@ break; } + PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3); + if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3) { @@ -2034,4 +2037,5 @@ break; } + PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3); if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3) Index: /trunk/src/VBox/VMM/VMMAll/PGMAllBth.h =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PGMAllBth.h (revision 41390) +++ /trunk/src/VBox/VMM/VMMAll/PGMAllBth.h (revision 41391) @@ -173,5 +173,5 @@ const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys; # else - const RTGCPHYS GCPhysFault = (RTGCPHYS)pvFault; + const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault); # endif PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault); @@ -561,5 +561,5 @@ rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr); # else - rc = pgmPhysGetPageEx(pVM, (RTGCPHYS)pvFault, &pPage); + rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage); if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, @@ -753,5 +753,5 @@ RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK; # else - RTGCPHYS GCPhys = (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK; + RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK); # endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */ PPGMPAGE pPage; @@ -1283,5 +1283,5 @@ # if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */ - GCPhys |= (iPDDst & 1) * (PAGE_SIZE/2); + GCPhys = PGM_A20_APPLY(pVCpu, GCPhys | ((iPDDst & 1) * (PAGE_SIZE / 2))); # endif if (pShwPage->GCPhys == GCPhys) @@ -1332,5 +1332,5 @@ # if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/ - GCPhys |= GCPtrPage & (1 << X86_PD_PAE_SHIFT); + GCPhys = PGM_A20_APPLY(pVCpu, GCPhys | (GCPtrPage & (1 << X86_PD_PAE_SHIFT))); # endif if ( pShwPage->GCPhys == GCPhys @@ -1909,5 +1909,5 @@ # if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */ - GCPhys |= (iPDDst & 1) * (PAGE_SIZE / 2); + GCPhys = PGM_A20_APPLY(pVCpu, GCPhys | ((iPDDst & 1) * (PAGE_SIZE / 2))); # endif } @@ -1917,5 +1917,5 @@ # if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/ - GCPhys |= GCPtrPage & (1 << X86_PD_PAE_SHIFT); + GCPhys = PGM_A20_APPLY(pVCpu, GCPhys | (GCPtrPage & (1 << X86_PD_PAE_SHIFT))); # endif } @@ -2037,5 +2037,5 @@ */ /* Calculate the GC physical address of this 4KB shadow page. */ - GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) | (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK); + GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) | (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK)); /* Find ram range. */ PPGMPAGE pPage; @@ -2673,5 +2673,5 @@ # if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */ - GCPhys |= (iPDDst & 1) * (PAGE_SIZE / 2); + GCPhys = PGM_A20_APPLY(pVCpu, GCPhys | ((iPDDst & 1) * (PAGE_SIZE / 2))); # endif rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage); @@ -2689,5 +2689,5 @@ # if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/ - GCPhys |= GCPtrPage & (1 << X86_PD_PAE_SHIFT); + GCPhys = PGM_A20_APPLY(pVCpu, GCPhys | (GCPtrPage & (1 << X86_PD_PAE_SHIFT))); # endif /* Determine the right kind of large page to avoid incorrect cached entry reuse. */ @@ -2909,9 +2909,15 @@ if (pRam && GCPhys >= pRam->GCPhys) { +# ifndef PGM_WITH_A20 unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT; +# endif do { /* Make shadow PTE. */ +# ifdef PGM_WITH_A20 + PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]; +# else PPGMPAGE pPage = &pRam->aPages[iHCPage]; +# endif SHWPTE PteDst; @@ -2977,5 +2983,8 @@ /* advance */ GCPhys += PAGE_SIZE; + PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys); +# ifndef PGM_WITH_A20 iHCPage++; +# endif iPTDst++; } while ( iPTDst < RT_ELEMENTS(pPTDst->a) @@ -2996,4 +3005,5 @@ } while ( iPTDst < RT_ELEMENTS(pPTDst->a) && GCPhys < pRam->GCPhys); + PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys); } else @@ -3092,5 +3102,5 @@ /* Check if we allocated a big page before for this 2 MB range. */ PPGMPAGE pPage; - rc = pgmPhysGetPageEx(pVM, GCPtrPage & X86_PDE2M_PAE_PG_MASK, &pPage); + rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage); if (RT_SUCCESS(rc)) { @@ -3098,9 +3108,18 @@ if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE) { - STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused); - AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED); - HCPhys = PGM_PAGE_GET_HCPHYS(pPage); + if (PGM_A20_IS_ENABLED(pVCpu)) + { + STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused); + AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED); + HCPhys = PGM_PAGE_GET_HCPHYS(pPage); + } + else + { + PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED); + pVM->pgm.s.cLargePagesDisabled++; + } } - else if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED) + else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED + && PGM_A20_IS_ENABLED(pVCpu)) { /* Recheck the entire 2 MB range to see if we can use it again as a large page. */ @@ -3113,5 +3132,6 @@ } } - else if (PGMIsUsingLargePages(pVM)) + else if ( PGMIsUsingLargePages(pVM) + && PGM_A20_IS_ENABLED(pVCpu)) { rc = pgmPhysAllocLargePage(pVM, GCPtrPage); @@ -3161,5 +3181,5 @@ /* Virtual address = physical address */ - GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK; + GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK); rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage); @@ -3183,5 +3203,6 @@ for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++) { - RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) | (iPTDst << PAGE_SHIFT); + RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) + | (iPTDst << PAGE_SHIFT)); PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst); @@ -3563,7 +3584,8 @@ * @returns VBox status code, no specials. * @param pVCpu The VMCPU handle. - * @param cr0 Guest context CR0 register - * @param cr3 Guest context CR3 register - * @param cr4 Guest context CR4 register + * @param cr0 Guest context CR0 register. + * @param cr3 Guest context CR3 register. Not subjected to the A20 + * mask. + * @param cr4 Guest context CR4 register. * @param fGlobal Including global page directories or not */ @@ -3690,5 +3712,5 @@ * Check that the Guest CR3 and all its mappings are correct. */ - AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK), + AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), ("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3), false); @@ -3701,5 +3723,5 @@ AssertRCReturn(rc, 1); HCPhys = NIL_RTHCPHYS; - rc = pgmRamGCPhys2HCPhys(pVM, cr3 & GST_CR3_PAGE_MASK, &HCPhys); + rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys); AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false); # if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3) @@ -3708,5 +3730,5 @@ rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys); AssertRCReturn(rc, 1); - AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false); + AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false); # endif # endif /* !IN_RING0 */ @@ -3755,5 +3777,5 @@ pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK); - GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK; + GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK); if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present) @@ -3829,5 +3851,5 @@ pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK); - GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK; + GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK); if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present) @@ -3940,5 +3962,5 @@ GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc); # if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT - GCPhysGst |= (iPDDst & 1) * (PAGE_SIZE / 2); + GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst | ((iPDDst & 1) * (PAGE_SIZE / 2))); # endif } @@ -3956,5 +3978,5 @@ GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc); # if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT - GCPhysGst |= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT); + GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst | (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT))); # endif } @@ -3992,5 +4014,6 @@ */ const GSTPT *pPTSrc; - rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc); + rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1)), + &pPTSrc); if (RT_FAILURE(rc)) { @@ -4047,5 +4070,5 @@ AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n", GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0], - (uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc)*sizeof(PteSrc))); + (uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc))); cErrors++; continue; @@ -4275,5 +4298,5 @@ for (unsigned iPT = 0, off = 0; iPT < RT_ELEMENTS(pPTDst->a); - iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE) + iPT++, off += PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + PAGE_SIZE)) { const SHWPTE PteDst = pPTDst->a[iPT]; @@ -4414,6 +4437,7 @@ * @retval VINF_SUCCESS. * - * @param pVCpu The VMCPU handle. - * @param GCPhysCR3 The physical address in the CR3 register. + * @param pVCpu The VMCPU handle. + * @param GCPhysCR3 The physical address in the CR3 register. (A20 + * mask already applied.) */ PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3) @@ -4481,5 +4505,5 @@ RTHCPTR HCPtr; RTHCPHYS HCPhys; - RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK; + RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, pGuestPDPT->a[i].u & X86_PDPE_PG_MASK); pgmLock(pVM); PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys); Index: /trunk/src/VBox/VMM/VMMAll/PGMAllGst.h =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PGMAllGst.h (revision 41390) +++ /trunk/src/VBox/VMM/VMMAll/PGMAllGst.h (revision 41391) @@ -167,4 +167,5 @@ pWalk->Core.GCPhys = GST_GET_BIG_PDE_GCPHYS(pVCpu->CTX_SUFF(pVM), Pde) | (GCPtr & GST_BIG_PAGE_OFFSET_MASK); + PGM_A20_APPLY_TO_VAR(pVCpu, pWalk->Core.GCPhys); uint8_t fEffectiveXX = (uint8_t)pWalk->Pde.u # if PGM_GST_TYPE == PGM_TYPE_AMD64 @@ -515,5 +516,5 @@ RTGCPHYS GCPhysNew; if (Pte.n.u1Present) - GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage; + GCPhysNew = PGM_A20_APPLY(pVCpu, (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage); else GCPhysNew = NIL_RTGCPHYS; @@ -567,5 +568,5 @@ i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0) { - RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage; + RTGCPHYS GCPhysNew = PGM_A20_APPLY(pVCpu, GCPhys + (i4KB << PAGE_SHIFT) + offPage); if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew) { Index: /trunk/src/VBox/VMM/include/PGMGstDefs.h =================================================================== --- /trunk/src/VBox/VMM/include/PGMGstDefs.h (revision 41390) +++ /trunk/src/VBox/VMM/include/PGMGstDefs.h (revision 41391) @@ -107,5 +107,5 @@ # endif # endif -# define GST_GET_PTE_GCPHYS(Pte) ((Pte).u & GST_PTE_PG_MASK) +# define GST_GET_PTE_GCPHYS(Pte) PGM_A20_APPLY(pVCpu, ((Pte).u & GST_PTE_PG_MASK)) # define GST_GET_PDE_GCPHYS(Pde) (true && This_should_perhaps_not_be_used_in_this_context) //?? # define GST_GET_BIG_PDE_GCPHYS(Pde) (true && This_should_perhaps_not_be_used_in_this_context) //?? @@ -138,7 +138,7 @@ # define GST_PDE_PG_MASK X86_PDE_PG_MASK # define GST_PDE_BIG_PG_MASK X86_PDE4M_PG_MASK -# define GST_GET_PTE_GCPHYS(Pte) ((Pte).u & GST_PDE_PG_MASK) -# define GST_GET_PDE_GCPHYS(Pde) ((Pde).u & GST_PDE_PG_MASK) -# define GST_GET_BIG_PDE_GCPHYS(pVM, Pde) pgmGstGet4MBPhysPage((pVM), Pde) +# define GST_GET_PTE_GCPHYS(Pte) PGM_A20_APPLY(pVCpu, ((Pte).u & GST_PDE_PG_MASK)) +# define GST_GET_PDE_GCPHYS(Pde) PGM_A20_APPLY(pVCpu, ((Pde).u & GST_PDE_PG_MASK)) +# define GST_GET_BIG_PDE_GCPHYS(pVM, Pde) PGM_A20_APPLY(pVCpu, pgmGstGet4MBPhysPage((pVM), Pde)) # define GST_GET_PDE_SHW_FLAGS(pVCpu, Pde) ((Pde).u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_A)) # define GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, Pde) \ @@ -178,7 +178,7 @@ # define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK # define GST_PDE_BIG_PG_MASK X86_PDE2M_PAE_PG_MASK -# define GST_GET_PTE_GCPHYS(Pte) ((Pte).u & GST_PTE_PG_MASK) -# define GST_GET_PDE_GCPHYS(Pde) ((Pde).u & GST_PDE_PG_MASK) -# define GST_GET_BIG_PDE_GCPHYS(pVM, Pde) ((Pde).u & GST_PDE_BIG_PG_MASK) +# define GST_GET_PTE_GCPHYS(Pte) PGM_A20_APPLY(pVCpu, ((Pte).u & GST_PTE_PG_MASK)) +# define GST_GET_PDE_GCPHYS(Pde) PGM_A20_APPLY(pVCpu, ((Pde).u & GST_PDE_PG_MASK)) +# define GST_GET_BIG_PDE_GCPHYS(pVM, Pde) PGM_A20_APPLY(pVCpu, ((Pde).u & GST_PDE_BIG_PG_MASK)) # define GST_GET_PTE_SHW_FLAGS(pVCpu, Pte) ((Pte).u & (pVCpu)->pgm.s.fGst64ShadowedPteMask ) # define GST_GET_PDE_SHW_FLAGS(pVCpu, Pde) ((Pde).u & (pVCpu)->pgm.s.fGst64ShadowedPdeMask ) Index: /trunk/src/VBox/VMM/include/PGMInternal.h =================================================================== --- /trunk/src/VBox/VMM/include/PGMInternal.h (revision 41390) +++ /trunk/src/VBox/VMM/include/PGMInternal.h (revision 41391) @@ -2520,4 +2520,21 @@ + +/** @name A20 gate macros + * @{ */ +/*#define PGM_WITH_A20*/ +#ifdef PGM_WITH_A20 +# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled) +# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_pVCpu)->pgm.s.GCPhysA20Mask & (a_GCPhys)) +# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \ + do { a_GCPhysVar = (a_pVCpu)->pgm.s.GCPhysA20Mask & a_GCPhysVar; } while (0) +#else +# define PGM_A20_IS_ENABLED(a_pVCpu) (true) +# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys) +# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0) +#endif +/** @} */ + + /** * Trees are using self relative offsets as pointers.