Index: /trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp	(revision 41311)
+++ /trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp	(revision 41312)
@@ -865,8 +865,4 @@
 
     pCpu->idCpu         = idCpu;
-
-    /* Make sure we start with a clean TLB. */
-    pCpu->fFlushTLB     = true;
-
     pCpu->uCurrentASID  = 0;    /* we'll aways increment this the first time (host uses ASID 0) */
     pCpu->cTLBFlushes   = 0;
Index: /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp	(revision 41311)
+++ /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp	(revision 41312)
@@ -1014,5 +1014,4 @@
 
     pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
-    pCpu->fFlushTLB = false;
     pVMCB->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
 
@@ -1102,4 +1101,9 @@
     if (pVMCB->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
         STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
+    else if (   pVMCB->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
+             || pVMCB->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
+    {
+        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
+    }
     else
         STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
@@ -1332,6 +1336,6 @@
             LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
     }
-    if (pCpu->fFlushTLB)
-        LogFlow(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
+    else if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH))
+        LogFlow(("Manual TLB flush\n"));
 #endif
 
Index: /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp	(revision 41311)
+++ /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp	(revision 41312)
@@ -233,5 +233,5 @@
 #endif
 
-    /* Allocate VMCBs for all guest CPUs. */
+    /* Allocate VMCSs for all guest CPUs. */
     for (VMCPUID i = 0; i < pVM->cCpus; i++)
     {
@@ -2205,12 +2205,4 @@
 
     pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
-    pCpu->fFlushTLB           = false;
-
-#ifdef VBOX_WITH_STATISTICS
-    if (pVCpu->hwaccm.s.fForceTLBFlush)
-        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
-    else
-        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
-#endif
 
     if (pVCpu->hwaccm.s.fForceTLBFlush)
@@ -2228,5 +2220,10 @@
             pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
             if (pCpu->fFlushASIDBeforeUse)
+            {
                 hmR0VmxFlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushVPID, 0 /* GCPtr */);
+#ifdef VBOX_WITH_STATISTICS
+                STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
+#endif
+            }
         }
         else
@@ -2236,4 +2233,12 @@
             else
                 hmR0VmxFlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushEPT);
+
+#ifdef VBOX_WITH_STATISTICS
+            /*
+             * This is not terribly accurate (i.e. we don't have a StatFlushEPT counter so we currently count these
+             * as ASID flushes too, better than including them under StatFlushTLBWorldSwitch.
+             */
+            STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
+#endif
         }
 
@@ -2264,9 +2269,14 @@
                 hmR0VmxFlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushEPT);
         }
+        else
+        {
+#ifdef VBOX_WITH_STATISTICS
+            STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
+#endif
+        }
     }
     pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
     VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
 
-    Assert(pCpu->fFlushTLB == false);
     AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes,
               ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
@@ -2307,8 +2317,4 @@
         pVCpu->hwaccm.s.fForceTLBFlush = true;
     }
-    /* Disabled because this has triggered every time I have suspended my
-     * laptop with a VM running for the past three months or more.  */
-    // else
-    //     Assert(!pCpu->fFlushTLB);
 
     /* Check for tlb shootdown flushes. */
@@ -2317,10 +2323,7 @@
 
     pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
-    pCpu->fFlushTLB           = false;
 
     if (pVCpu->hwaccm.s.fForceTLBFlush)
-    {
         hmR0VmxFlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushEPT);
-    }
     else
     {
@@ -2374,6 +2377,4 @@
         pVCpu->hwaccm.s.fForceTLBFlush = true;
     }
-    else
-        Assert(!pCpu->fFlushTLB);
 
     pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
@@ -2387,8 +2388,6 @@
     {
         ++pCpu->uCurrentASID;
-        if (    pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
-            ||  pCpu->fFlushTLB)
-        {
-            pCpu->fFlushTLB                  = false;
+        if (pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID)
+        {
             pCpu->uCurrentASID               = 1;       /* start at 1; host uses 0 */
             pCpu->cTLBFlushes++;
@@ -2406,5 +2405,4 @@
     else
     {
-        Assert(!pCpu->fFlushTLB);
         Assert(pVCpu->hwaccm.s.uCurrentASID && pCpu->uCurrentASID);
 
@@ -2757,7 +2755,5 @@
                 LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
         }
-        if (pCpu->fFlushTLB)
-            LogFlow(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
-        else if (pVCpu->hwaccm.s.fForceTLBFlush)
+        else if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH))
             LogFlow(("Manual TLB flush\n"));
     }
Index: /trunk/src/VBox/VMM/include/HWACCMInternal.h
===================================================================
--- /trunk/src/VBox/VMM/include/HWACCMInternal.h	(revision 41311)
+++ /trunk/src/VBox/VMM/include/HWACCMInternal.h	(revision 41312)
@@ -168,7 +168,4 @@
     /** Whether to flush each new ASID/VPID before use. */
     bool                fFlushASIDBeforeUse;
-
-    /** Set the first time a cpu is used to make sure we start with a clean TLB. */
-    bool                fFlushTLB;
 
     /** Configured for VT-x or AMD-V. */