Index: /trunk/src/VBox/Devices/PC/DevAPIC.cpp
===================================================================
--- /trunk/src/VBox/Devices/PC/DevAPIC.cpp	(revision 37573)
+++ /trunk/src/VBox/Devices/PC/DevAPIC.cpp	(revision 37574)
@@ -564,5 +564,5 @@
  * @param   fMsr                Set if called via MSR, clear if MMIO.
  */
-static int acpiWriteRegister(APICDeviceInfo *pDev, APICState *pApic, uint32_t iReg, uint64_t u64Value,
+static int apicWriteRegister(APICDeviceInfo *pDev, APICState *pApic, uint32_t iReg, uint64_t u64Value,
                              int rcBusy, bool fMsr)
 {
@@ -589,5 +589,5 @@
 
         case 0x09: case 0x0a:
-            Log(("acpiWriteRegister: write to read-only register %d ignored\n", iReg));
+            Log(("apicWriteRegister: write to read-only register %d ignored\n", iReg));
             break;
 
@@ -621,5 +621,5 @@
         case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
         case 0x28:
-            Log(("acpiWriteRegister: write to read-only register %d ignored\n", iReg));
+            Log(("apicWriteRegister: write to read-only register %d ignored\n", iReg));
             break;
 
@@ -664,5 +664,5 @@
 
         case 0x39:
-            Log(("acpiWriteRegister: write to read-only register %d ignored\n", iReg));
+            Log(("apicWriteRegister: write to read-only register %d ignored\n", iReg));
             break;
 
@@ -713,5 +713,5 @@
     APICState      *pApic = getLapicById(pDev, idCpu);
     uint32_t        iReg = (u32Reg - MSR_IA32_APIC_START) & 0xff;
-    return acpiWriteRegister(pDev, pApic, iReg, u64Value, VINF_SUCCESS /*rcBusy*/, true /*fMsr*/);
+    return apicWriteRegister(pDev, pApic, iReg, u64Value, VINF_SUCCESS /*rcBusy*/, true /*fMsr*/);
 }
 
@@ -1728,5 +1728,5 @@
         case 4:
             /* It does its own locking. */
-            return acpiWriteRegister(pDev, s, (GCPhysAddr >> 4) & 0xff, *(uint32_t const *)pv,
+            return apicWriteRegister(pDev, s, (GCPhysAddr >> 4) & 0xff, *(uint32_t const *)pv,
                                      VINF_IOM_HC_MMIO_WRITE, false /*fMsr*/);