Index: /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp (revision 37089) +++ /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp (revision 37090) @@ -605,4 +605,5 @@ static VBOXSTRICTRC iemMemStackPushBeginSpecial(PIEMCPU pIemCpu, size_t cbMem, void **ppvMem, uint64_t *puNewRsp); static VBOXSTRICTRC iemMemMarkSelDescAccessed(PIEMCPU pIemCpu, uint16_t uSel); +static uint16_t iemSRegFetchU16(PIEMCPU pIemCpu, uint8_t iSegReg); #ifdef IEM_VERIFICATION_MODE @@ -1353,10 +1354,4 @@ /** Generated by the breakpoint instruction. */ #define IEM_XCPT_FLAGS_BP_INSTR RT_BIT_32(5) -/** Mask out the nesting level. */ -#define IEM_XCPT_FLAGS_NESTING_MASK UINT32_C(0xff000000) -/** Shift count for the nesting level. */ -#define IEM_XCPT_FLAGS_NESTING_SHIFT 24 -/** Mask out the nesting level after shifting. */ -#define IEM_XCPT_FLAGS_NESTING_SMASK UINT32_C(0x000000ff) /** @} */ @@ -1810,5 +1805,5 @@ } - /* ... register commiting continues. */ + /* ... register committing continues. */ pCtx->cs = (NewCS & ~X86_SEL_RPL) | uNewCpl; pCtx->csHid.u32Limit = cbLimitCS; @@ -1818,4 +1813,7 @@ pCtx->rip = uNewEip; pCtx->rflags.u &= ~fEflToClear; + + if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT) + iemRaiseXcptAdjustState(pCtx, u8Vector); return fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT ? VINF_IEM_RAISED_XCPT : VINF_SUCCESS; @@ -1891,5 +1889,5 @@ * @param uCr2 The CR2 value if IEM_XCPT_FLAGS_CR2 is set. */ -static VBOXSTRICTRC +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseXcptOrInt(PIEMCPU pIemCpu, uint8_t cbInstr, @@ -1904,5 +1902,6 @@ * Do recursion accounting. */ - uint8_t const uPrevXcpt = pIemCpu->uCurXcpt; + uint8_t const uPrevXcpt = pIemCpu->uCurXcpt; + uint32_t const fPrevXcpt = pIemCpu->fCurXcpt; if (pIemCpu->cXcptRecursions == 0) Log(("iemRaiseXcptOrInt: %#x at %04x:%RGv cbInstr=%#x fFlags=%#x uErr=%#x uCr2=%llx\n", @@ -1910,12 +1909,63 @@ else { - Log(("iemRaiseXcptOrInt: %#x at %04x:%RGv cbInstr=%#x fFlags=%#x uErr=%#x uCr2=%llx; prev=%#x depth=%d\n", - u8Vector, pCtx->cs, pCtx->rip, cbInstr, fFlags, uErr, uCr2, pIemCpu->uCurXcpt, pIemCpu->cXcptRecursions + 1)); + Log(("iemRaiseXcptOrInt: %#x at %04x:%RGv cbInstr=%#x fFlags=%#x uErr=%#x uCr2=%llx; prev=%#x depth=%d flags=%#x\n", + u8Vector, pCtx->cs, pCtx->rip, cbInstr, fFlags, uErr, uCr2, pIemCpu->uCurXcpt, pIemCpu->cXcptRecursions + 1, fPrevXcpt)); /** @todo double and tripple faults. */ AssertReturn(pIemCpu->cXcptRecursions < 3, VERR_NOT_IMPLEMENTED); + + /** @todo set X86_TRAP_ERR_EXTERNAL when appropriate. + if (fPrevXcpt & IEM_XCPT_FLAGS_T_EXT_INT) + { + .... + } */ } pIemCpu->cXcptRecursions++; pIemCpu->uCurXcpt = u8Vector; + pIemCpu->fCurXcpt = fFlags; + + /* + * Extensive logging. + */ +#ifdef LOG_ENABLED + if (LogIs3Enabled()) + { + PVM pVM = IEMCPU_TO_VM(pIemCpu); + PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu); + char szRegs[4096]; + DBGFR3RegPrintf(pVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs), + "rax=%016VR{rax} rbx=%016VR{rbx} rcx=%016VR{rcx} rdx=%016VR{rdx}\n" + "rsi=%016VR{rsi} rdi=%016VR{rdi} r8 =%016VR{r8} r9 =%016VR{r9}\n" + "r10=%016VR{r10} r11=%016VR{r11} r12=%016VR{r12} r13=%016VR{r13}\n" + "r14=%016VR{r14} r15=%016VR{r15} %VRF{rflags}\n" + "rip=%016VR{rip} rsp=%016VR{rsp} rbp=%016VR{rbp}\n" + "cs={%04VR{cs} base=%016VR{cs_base} limit=%08VR{cs_lim} flags=%04VR{cs_attr}} cr0=%016VR{cr0}\n" + "ds={%04VR{ds} base=%016VR{ds_base} limit=%08VR{ds_lim} flags=%04VR{ds_attr}} cr2=%016VR{cr2}\n" + "es={%04VR{es} base=%016VR{es_base} limit=%08VR{es_lim} flags=%04VR{es_attr}} cr3=%016VR{cr3}\n" + "fs={%04VR{fs} base=%016VR{fs_base} limit=%08VR{fs_lim} flags=%04VR{fs_attr}} cr4=%016VR{cr4}\n" + "gs={%04VR{gs} base=%016VR{gs_base} limit=%08VR{gs_lim} flags=%04VR{gs_attr}} cr8=%016VR{cr8}\n" + "ss={%04VR{ss} base=%016VR{ss_base} limit=%08VR{ss_lim} flags=%04VR{ss_attr}}\n" + "dr0=%016VR{dr0} dr1=%016VR{dr1} dr2=%016VR{dr2} dr3=%016VR{dr3}\n" + "dr6=%016VR{dr6} dr7=%016VR{dr7}\n" + "gdtr=%016VR{gdtr_base}:%04VR{gdtr_lim} idtr=%016VR{idtr_base}:%04VR{idtr_lim} rflags=%08VR{rflags}\n" + "ldtr={%04VR{ldtr} base=%016VR{ldtr_base} limit=%08VR{ldtr_lim} flags=%08VR{ldtr_attr}}\n" + "tr ={%04VR{tr} base=%016VR{tr_base} limit=%08VR{tr_lim} flags=%08VR{tr_attr}}\n" + " sysenter={cs=%04VR{sysenter_cs} eip=%08VR{sysenter_eip} esp=%08VR{sysenter_esp}}\n" + " efer=%016VR{efer}\n" + " pat=%016VR{pat}\n" + " sf_mask=%016VR{sf_mask}\n" + "krnl_gs_base=%016VR{krnl_gs_base}\n" + " lstar=%016VR{lstar}\n" + " star=%016VR{star} cstar=%016VR{cstar}\n" + "fcw=%04VR{fcw} fsw=%04VR{fsw} ftw=%04VR{ftw} mxcsr=%04VR{mxcsr} mxcsr_mask=%04VR{mxcsr_mask}\n" + ); + + char szInstr[256]; + DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, 0, 0, + DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE, + szInstr, sizeof(szInstr), NULL); + Log3(("%s%s\n", szRegs, szInstr)); + } +#endif /* LOG_ENABLED */ /* @@ -1937,4 +1987,5 @@ pIemCpu->cXcptRecursions--; pIemCpu->uCurXcpt = uPrevXcpt; + pIemCpu->fCurXcpt = fPrevXcpt; Log(("iemRaiseXcptOrInt: returns %Rrc (vec=%#x); cs:rip=%04x:%RGv ss:rsp=%04x:%RGv\n", VBOXSTRICTRC_VAL(rcStrict), u8Vector, pCtx->cs, pCtx->rip, pCtx->ss, pCtx->esp)); @@ -1944,144 +1995,166 @@ /** \#DE - 00. */ -static VBOXSTRICTRC iemRaiseDivideError(PIEMCPU pIemCpu) -{ - AssertFailed(/** @todo implement this */); - return VERR_NOT_IMPLEMENTED; +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseDivideError(PIEMCPU pIemCpu) +{ + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_DE, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0); } /** \#DB - 01. */ -static VBOXSTRICTRC iemRaiseDebugException(PIEMCPU pIemCpu) -{ - AssertFailed(/** @todo implement this */); - return VERR_NOT_IMPLEMENTED; +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseDebugException(PIEMCPU pIemCpu) +{ + /** @todo set/clear RF. */ + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_DB, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0); } /** \#UD - 06. */ -static VBOXSTRICTRC iemRaiseUndefinedOpcode(PIEMCPU pIemCpu) -{ - AssertFailed(/** @todo implement X86_XCPT_UD */); - return VERR_NOT_IMPLEMENTED; +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseUndefinedOpcode(PIEMCPU pIemCpu) +{ + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_UD, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0); } /** \#NM - 07. */ -static VBOXSTRICTRC iemRaiseDeviceNotAvailable(PIEMCPU pIemCpu) -{ - AssertFailed(/** @todo implement this */); - return VERR_NOT_IMPLEMENTED; +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseDeviceNotAvailable(PIEMCPU pIemCpu) +{ + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_NM, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0); } /** \#TS(err) - 0a. */ -static VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PIEMCPU pIemCpu, uint16_t uErr) -{ - AssertFailed(/** @todo implement this */); - return VERR_NOT_IMPLEMENTED; +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseTaskSwitchFaultWithErr(PIEMCPU pIemCpu, uint16_t uErr) +{ + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_TS, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, uErr, 0); } /** \#TS(tr) - 0a. */ -static VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PIEMCPU pIemCpu) -{ - return iemRaiseTaskSwitchFaultWithErr(pIemCpu, pIemCpu->CTX_SUFF(pCtx)->tr); +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseTaskSwitchFaultCurrentTSS(PIEMCPU pIemCpu) +{ + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_TS, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, + pIemCpu->CTX_SUFF(pCtx)->tr, 0); } /** \#NP(err) - 0b. */ -static VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PIEMCPU pIemCpu, uint16_t uErr) -{ - AssertFailed(/** @todo implement this */); - return VERR_NOT_IMPLEMENTED; +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseSelectorNotPresentWithErr(PIEMCPU pIemCpu, uint16_t uErr) +{ + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_NP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, uErr, 0); } /** \#NP(seg) - 0b. */ -static VBOXSTRICTRC iemRaiseSelectorNotPresentBySegReg(PIEMCPU pIemCpu, uint32_t iSegReg) -{ - AssertFailed(/** @todo implement this */); - return VERR_NOT_IMPLEMENTED; +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseSelectorNotPresentBySegReg(PIEMCPU pIemCpu, uint32_t iSegReg) +{ + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_NP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, + iemSRegFetchU16(pIemCpu, iSegReg) & ~X86_SEL_RPL, 0); } /** \#NP(sel) - 0b. */ -static VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PIEMCPU pIemCpu, uint16_t uSel) -{ - AssertFailed(/** @todo implement this */); - return VERR_NOT_IMPLEMENTED; +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseSelectorNotPresentBySelector(PIEMCPU pIemCpu, uint16_t uSel) +{ + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_NP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, + uSel & ~X86_SEL_RPL, 0); } /** \#GP(n) - 0d. */ -static VBOXSTRICTRC iemRaiseGeneralProtectionFault(PIEMCPU pIemCpu, uint16_t uErr) -{ - AssertFailed(/** @todo implement this */); - return VERR_NOT_IMPLEMENTED; +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseGeneralProtectionFault(PIEMCPU pIemCpu, uint16_t uErr) +{ + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, uErr, 0); } /** \#GP(0) - 0d. */ -static VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PIEMCPU pIemCpu) -{ - return iemRaiseGeneralProtectionFault(pIemCpu, 0); +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseGeneralProtectionFault0(PIEMCPU pIemCpu) +{ + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, 0, 0); } /** \#GP(sel) - 0d. */ -static VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PIEMCPU pIemCpu, RTSEL Sel) -{ - return iemRaiseGeneralProtectionFault(pIemCpu, Sel & (X86_SEL_MASK | X86_SEL_LDT)); +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseGeneralProtectionFaultBySelector(PIEMCPU pIemCpu, RTSEL Sel) +{ + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, + Sel & ~X86_SEL_RPL, 0); } /** \#GP(0) - 0d. */ -static VBOXSTRICTRC iemRaiseNotCanonical(PIEMCPU pIemCpu) -{ - AssertFailed(/** @todo implement this */); - return VERR_NOT_IMPLEMENTED; +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseNotCanonical(PIEMCPU pIemCpu) +{ + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, 0, 0); } /** \#GP(sel) - 0d. */ -static VBOXSTRICTRC iemRaiseSelectorBounds(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess) -{ - AssertFailed(/** @todo implement this */); - return VERR_NOT_IMPLEMENTED; +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseSelectorBounds(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess) +{ + NOREF(iSegReg); NOREF(fAccess); + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, 0, 0); } /** \#GP(sel) - 0d. */ -static VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PIEMCPU pIemCpu, RTSEL Sel) -{ - AssertFailed(/** @todo implement this */); - return VERR_NOT_IMPLEMENTED; +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseSelectorBoundsBySelector(PIEMCPU pIemCpu, RTSEL Sel) +{ + NOREF(Sel); + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, 0, 0); } /** \#GP(sel) - 0d. */ -static VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess) -{ - AssertFailed(/** @todo implement this */); - return VERR_NOT_IMPLEMENTED; +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseSelectorInvalidAccess(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess) +{ + NOREF(iSegReg); NOREF(fAccess); + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, 0, 0); } /** \#PF(n) - 0e. */ -static VBOXSTRICTRC iemRaisePageFault(PIEMCPU pIemCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) -{ - /** @todo implement this */ - AssertMsgFailed(("GCPtrWhere=%RGp fAccess=%#x rc=%Rrc\n", GCPtrWhere, fAccess, rc)); - return VERR_NOT_IMPLEMENTED; +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaisePageFault(PIEMCPU pIemCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) +{ + uint16_t uErr; + switch (rc) + { + case VERR_PAGE_NOT_PRESENT: + case VERR_PAGE_TABLE_NOT_PRESENT: + case VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT: + case VERR_PAGE_MAP_LEVEL4_NOT_PRESENT: + uErr = 0; + break; + + default: + AssertMsgFailed(("%Rrc\n", rc)); + case VERR_ACCESS_DENIED: + uErr = X86_TRAP_PF_P; + break; + + /** @todo reserved */ + } + + if (pIemCpu->uCpl == 3) + uErr |= X86_TRAP_PF_US; + + if ( (fAccess & IEM_ACCESS_WHAT_MASK) == IEM_ACCESS_WHAT_CODE + && ( (pIemCpu->CTX_SUFF(pCtx)->cr4 & X86_CR4_PAE) + && (pIemCpu->CTX_SUFF(pCtx)->msrEFER & MSR_K6_EFER_NXE) ) ) + uErr |= X86_TRAP_PF_ID; + + if (fAccess & IEM_ACCESS_TYPE_WRITE) + uErr |= X86_TRAP_PF_RW; + + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_PF, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR | IEM_XCPT_FLAGS_CR2, + uErr, GCPtrWhere); } /** \#MF(n) - 10. */ -static VBOXSTRICTRC iemRaiseMathFault(PIEMCPU pIemCpu) -{ - AssertFailed(/** @todo implement this */); - return VERR_NOT_IMPLEMENTED; -} - +DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseMathFault(PIEMCPU pIemCpu) +{ + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_MF, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0); +} @@ -2097,6 +2170,5 @@ IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix) { - AssertFailed(); - return VERR_NOT_IMPLEMENTED; + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_UD, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0); } @@ -2113,6 +2185,5 @@ IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode) { - AssertFailed(); - return VERR_NOT_IMPLEMENTED; + return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_UD, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0); } @@ -5297,9 +5368,23 @@ PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu); PCPUMCTX pOrgCtx = pIemCpu->CTX_SUFF(pCtx); - pIemCpu->fNoRem = !LogIsEnabled(); /* logging triggers the no-rem/rem verification stuff */ - + + /* + * Enable verification and/or logging. + */ + pIemCpu->fNoRem = !LogIs6Enabled(); /* logging triggers the no-rem/rem verification stuff */ + if ( pIemCpu->fNoRem +#if 0 /* auto enable on first paged protected mode interrupt */ + && pOrgCtx->eflags.Bits.u1IF + && (pOrgCtx->cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG) + && TRPMHasTrap(pVCpu) + && EMGetInhibitInterruptsPC(pVCpu) != pOrgCtx->rip) +#endif #if 0 - // Auto enable; DSL. - if ( pIemCpu->fNoRem + && pOrgCtx->cs == 0x10 + && ( pOrgCtx->rip == 0x90119e3e + || pOrgCtx->rip == 0x901d9810 + ) +#endif +#if 0 /* Auto enable; DSL. */ && pOrgCtx->cs == 0x10 && ( pOrgCtx->rip == 0x00100fc7 @@ -5307,21 +5392,14 @@ || pOrgCtx->rip == 0x00100ffe ) +#endif +#if 0 + && 0 +#endif ) { + RTLogGroupSettings(NULL, "iem.eo.l6.l2"); RTLogFlags(NULL, "enabled"); pIemCpu->fNoRem = false; } -#endif -#if 0 /* auto enable on first paged protected mode interrupt */ - if ( pIemCpu->fNoRem - && pOrgCtx->eflags.Bits.u1IF - && (pOrgCtx->cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG) - && TRPMHasTrap(pVCpu) - && EMGetInhibitInterruptsPC(pVCpu) != pOrgCtx->rip) - { - RTLogFlags(NULL, "enabled"); - pIemCpu->fNoRem = false; - } -#endif /* @@ -6014,4 +6092,5 @@ pIemCpu->CTX_SUFF(pCtx) = pOrgCtx; +#if 0 /* * HACK ALERT! You don't normally want to verify a whole boot sequence. @@ -6019,4 +6098,5 @@ if (pIemCpu->cInstructions == 1) RTLogFlags(NULL, "disabled"); +#endif } Index: /trunk/src/VBox/VMM/include/IEMInternal.h =================================================================== --- /trunk/src/VBox/VMM/include/IEMInternal.h (revision 37089) +++ /trunk/src/VBox/VMM/include/IEMInternal.h (revision 37090) @@ -147,10 +147,14 @@ bool fByPassHandlers; /** Explicit alignment padding. */ - bool afAlignment0[4]; - + bool afAlignment0[2]; + + /** The flags of the current exception / interrupt. */ + uint32_t fCurXcpt; + /** The current exception / interrupt. */ + uint8_t uCurXcpt; /** Exception / interrupt recursion depth. */ int8_t cXcptRecursions; - /** The current exception / interrupt . */ - uint8_t uCurXcpt; + /** Explicit alignment padding. */ + bool afAlignment1[1]; /** The CPL. */ uint8_t uCpl; @@ -175,5 +179,5 @@ * and RDTSCP are timing sensitive. */ bool fIgnoreRaxRdx; - bool afAlignment1[2]; + bool afAlignment2[2]; /** Mask of undefined eflags. * The verifier will any difference in these flags. */