Index: /trunk/include/VBox/vmm/dbgf.h =================================================================== --- /trunk/include/VBox/vmm/dbgf.h (revision 35600) +++ /trunk/include/VBox/vmm/dbgf.h (revision 35601) @@ -1424,5 +1424,5 @@ VMMR3DECL(const char *) DBGFR3RegCpuName(PVM pVM, DBGFREG enmReg, DBGFREGVALTYPE enmType); -VMMR3_INT_DECL(int) DBGFR3RegRegisterCpu(PVM pVM, PVMCPU pVCpu, PCDBGFREGDESC paRegisters); +VMMR3_INT_DECL(int) DBGFR3RegRegisterCpu(PVM pVM, PVMCPU pVCpu, PCDBGFREGDESC paRegisters, bool fGuestRegs); VMMR3DECL(int) DBGFR3RegRegisterDevice(PVM pVM, PCDBGFREGDESC paRegisters, PPDMDEVINS pDevIns, const char *pszPrefix, uint32_t iInstance); Index: /trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp (revision 35600) +++ /trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp (revision 35601) @@ -39,5 +39,5 @@ { PVMCPU pVCpu = (PVMCPU)pvUser; - void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest + pDesc->offRegister; + void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister; VMCPU_ASSERT_EMT(pVCpu); @@ -62,5 +62,5 @@ { PVMCPU pVCpu = (PVMCPU)pvUser; - void *pv = (uint8_t *)&pVCpu->cpum.s.Guest + pDesc->offRegister; + void *pv = (uint8_t *)&pVCpu->cpum + pDesc->offRegister; VMCPU_ASSERT_EMT(pVCpu); @@ -115,8 +115,155 @@ * @interface_method_impl{DBGFREGDESC, pfnGet} */ -static DECLCALLBACK(int) cpumR3RegGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) +static DECLCALLBACK(int) cpumR3RegGet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) +{ + PVMCPU pVCpu = (PVMCPU)pvUser; + VBOXGDTR const *pGdtr = (VBOXGDTR const *)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister); + + VMCPU_ASSERT_EMT(pVCpu); + Assert(pDesc->enmType == DBGFREGVALTYPE_DTR); + + pValue->dtr.u32Limit = pGdtr->cbGdt; + pValue->dtr.u64Base = pGdtr->pGdt; + return VINF_SUCCESS; +} + + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegSet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) +{ + return VERR_NOT_IMPLEMENTED; +} + + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegGet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) +{ + PVMCPU pVCpu = (PVMCPU)pvUser; + VBOXIDTR const *pIdtr = (VBOXIDTR const *)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister); + + VMCPU_ASSERT_EMT(pVCpu); + Assert(pDesc->enmType == DBGFREGVALTYPE_DTR); + + pValue->dtr.u32Limit = pIdtr->cbIdt; + pValue->dtr.u64Base = pIdtr->pIdt; + return VINF_SUCCESS; +} + + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegSet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) +{ + return VERR_NOT_IMPLEMENTED; +} + + +/** + * Is the FPU state in FXSAVE format or not. + * + * @returns true if it is, false if it's in FNSAVE. + * @param pVCpu The virtual CPU handle. + */ +DECLINLINE(bool) cpumR3RegIsFxSaveFormat(PVMCPU pVCpu) +{ +#ifdef RT_ARCH_AMD64 + return true; +#else + return pVCpu->pVMR3->cpum.s.CPUFeatures.edx.u1FXSR; +#endif +} + + +/** + * Determins the tag register value for a CPU register when the FPU state + * format is FXSAVE. + * + * @returns The tag register value. + * @param pVCpu The virtual CPU handle. + * @param iReg The register number (0..7). + */ +DECLINLINE(uint16_t) cpumR3RegCalcFpuTagFromFxSave(PCX86FXSTATE pFpu, unsigned iReg) +{ + /* + * See table 11-1 in the AMD docs. + */ + if (!(pFpu->FTW & RT_BIT_32(iReg))) + return 3; /* b11 - empty */ + + uint16_t const uExp = pFpu->aRegs[iReg].au16[4]; + if (uExp == 0) + { + if (pFpu->aRegs[iReg].au64[0] == 0) /* J & M == 0 */ + return 1; /* b01 - zero */ + return 2; /* b10 - special */ + } + + if (uExp == UINT16_C(0xffff)) + return 2; /* b10 - special */ + + if (!(pFpu->aRegs[iReg].au64[0] >> 63)) /* J == 0 */ + return 2; /* b10 - special */ + + return 0; /* b00 - valid (normal) */ +} + + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegGet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) +{ + PVMCPU pVCpu = (PVMCPU)pvUser; + PCX86FXSTATE pFpu = (PCX86FXSTATE)((uint8_t const *)&pVCpu->cpum + pDesc->offRegister); + + VMCPU_ASSERT_EMT(pVCpu); + Assert(pDesc->enmType == DBGFREGVALTYPE_U16); + + if (cpumR3RegIsFxSaveFormat(pVCpu)) + pValue->u16 = cpumR3RegCalcFpuTagFromFxSave(pFpu, 0) + | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 1) << 2) + | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 2) << 4) + | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 3) << 6) + | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 4) << 8) + | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 5) << 10) + | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 6) << 12) + | (cpumR3RegCalcFpuTagFromFxSave(pFpu, 7) << 14); + else + { + PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)pFpu; + pValue->u16 = pOldFpu->FTW; + } + return VINF_SUCCESS; +} + + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegSet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) +{ + return VERR_DBGF_READ_ONLY_REGISTER; +} + + + +/* + * + * Guest register access functions. + * + */ + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegGstGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) { PVMCPU pVCpu = (PVMCPU)pvUser; - void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest + pDesc->offRegister; + void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister; VMCPU_ASSERT_EMT(pVCpu); @@ -139,9 +286,9 @@ * @interface_method_impl{DBGFREGDESC, pfnGet} */ -static DECLCALLBACK(int) cpumR3RegSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) +static DECLCALLBACK(int) cpumR3RegGstSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) { int rc; PVMCPU pVCpu = (PVMCPU)pvUser; - void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest + pDesc->offRegister; + void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister; VMCPU_ASSERT_EMT(pVCpu); @@ -197,8 +344,8 @@ * @interface_method_impl{DBGFREGDESC, pfnGet} */ -static DECLCALLBACK(int) cpumR3RegGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) +static DECLCALLBACK(int) cpumR3RegGstGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) { PVMCPU pVCpu = (PVMCPU)pvUser; - void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest + pDesc->offRegister; + void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister; VMCPU_ASSERT_EMT(pVCpu); @@ -221,9 +368,9 @@ * @interface_method_impl{DBGFREGDESC, pfnGet} */ -static DECLCALLBACK(int) cpumR3RegSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) +static DECLCALLBACK(int) cpumR3RegGstSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) { int rc; PVMCPU pVCpu = (PVMCPU)pvUser; - void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest + pDesc->offRegister; + void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister; VMCPU_ASSERT_EMT(pVCpu); @@ -269,8 +416,8 @@ * @interface_method_impl{DBGFREGDESC, pfnGet} */ -static DECLCALLBACK(int) cpumR3RegGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) +static DECLCALLBACK(int) cpumR3RegGstGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) { PVMCPU pVCpu = (PVMCPU)pvUser; - void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest + pDesc->offRegister; + void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister; VMCPU_ASSERT_EMT(pVCpu); @@ -296,9 +443,9 @@ * @interface_method_impl{DBGFREGDESC, pfnGet} */ -static DECLCALLBACK(int) cpumR3RegSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) +static DECLCALLBACK(int) cpumR3RegGstSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) { int rc; PVMCPU pVCpu = (PVMCPU)pvUser; - void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest + pDesc->offRegister; + void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister; VMCPU_ASSERT_EMT(pVCpu); @@ -349,145 +496,5 @@ * @interface_method_impl{DBGFREGDESC, pfnGet} */ -static DECLCALLBACK(int) cpumR3RegGet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) -{ - PVMCPU pVCpu = (PVMCPU)pvUser; - void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest + pDesc->offRegister; - - VMCPU_ASSERT_EMT(pVCpu); - Assert(pDesc->enmType == DBGFREGVALTYPE_DTR); - - pValue->dtr.u32Limit = pVCpu->cpum.s.Guest.gdtr.cbGdt; - pValue->dtr.u64Base = pVCpu->cpum.s.Guest.gdtr.pGdt; - return VINF_SUCCESS; -} - - -/** - * @interface_method_impl{DBGFREGDESC, pfnGet} - */ -static DECLCALLBACK(int) cpumR3RegSet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) -{ - return VERR_NOT_IMPLEMENTED; -} - - -/** - * @interface_method_impl{DBGFREGDESC, pfnGet} - */ -static DECLCALLBACK(int) cpumR3RegGet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) -{ - PVMCPU pVCpu = (PVMCPU)pvUser; - void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest + pDesc->offRegister; - - VMCPU_ASSERT_EMT(pVCpu); - Assert(pDesc->enmType == DBGFREGVALTYPE_DTR); - - pValue->dtr.u32Limit = pVCpu->cpum.s.Guest.idtr.cbIdt; - pValue->dtr.u64Base = pVCpu->cpum.s.Guest.idtr.pIdt; - return VINF_SUCCESS; -} - - -/** - * @interface_method_impl{DBGFREGDESC, pfnGet} - */ -static DECLCALLBACK(int) cpumR3RegSet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) -{ - return VERR_NOT_IMPLEMENTED; -} - - -/** - * Is the FPU state in FXSAVE format or not. - * - * @returns true if it is, false if it's in FNSAVE. - * @param pVCpu The virtual CPU handle. - */ -DECLINLINE(bool) cpumR3RegIsFxSaveFormat(PVMCPU pVCpu) -{ -#ifdef RT_ARCH_AMD64 - return true; -#else - return pVCpu->pVMR3->cpum.s.CPUFeatures.edx.u1FXSR; -#endif -} - - -/** - * Determins the tag register value for a CPU register when the FPU state - * format is FXSAVE. - * - * @returns The tag register value. - * @param pVCpu The virtual CPU handle. - * @param iReg The register number (0..7). - */ -DECLINLINE(uint16_t) cpumR3RegCalcFpuTagFromFxSave(PVMCPU pVCpu, unsigned iReg) -{ - /* - * See table 11-1 in the AMD docs. - */ - if (!(pVCpu->cpum.s.Guest.fpu.FTW & RT_BIT_32(iReg))) - return 3; /* b11 - empty */ - - uint16_t const uExp = pVCpu->cpum.s.Guest.fpu.aRegs[iReg].au16[4]; - if (uExp == 0) - { - if (pVCpu->cpum.s.Guest.fpu.aRegs[iReg].au64[0] == 0) /* J & M == 0 */ - return 1; /* b01 - zero */ - return 2; /* b10 - special */ - } - - if (uExp == UINT16_C(0xffff)) - return 2; /* b10 - special */ - - if (!(pVCpu->cpum.s.Guest.fpu.aRegs[iReg].au64[0] >> 63)) /* J == 0 */ - return 2; /* b10 - special */ - - return 0; /* b00 - valid (normal) */ -} - - -/** - * @interface_method_impl{DBGFREGDESC, pfnGet} - */ -static DECLCALLBACK(int) cpumR3RegGet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) -{ - PVMCPU pVCpu = (PVMCPU)pvUser; - void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest + pDesc->offRegister; - - VMCPU_ASSERT_EMT(pVCpu); - Assert(pDesc->enmType == DBGFREGVALTYPE_U16); - - if (cpumR3RegIsFxSaveFormat(pVCpu)) - pValue->u16 = cpumR3RegCalcFpuTagFromFxSave(pVCpu, 0) - | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 1) << 2) - | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 2) << 4) - | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 3) << 6) - | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 4) << 8) - | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 5) << 10) - | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 6) << 12) - | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 7) << 14); - else - { - PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.fpu; - pValue->u16 = pOldFpu->FTW; - } - return VINF_SUCCESS; -} - - -/** - * @interface_method_impl{DBGFREGDESC, pfnGet} - */ -static DECLCALLBACK(int) cpumR3RegSet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) -{ - return VERR_DBGF_READ_ONLY_REGISTER; -} - - -/** - * @interface_method_impl{DBGFREGDESC, pfnGet} - */ -static DECLCALLBACK(int) cpumR3RegGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) +static DECLCALLBACK(int) cpumR3RegGstGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) { PVMCPU pVCpu = (PVMCPU)pvUser; @@ -518,11 +525,175 @@ } -/** - * @interface_method_impl{DBGFREGDESC, pfnGet} - */ -static DECLCALLBACK(int) cpumR3RegSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegGstSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) { return VERR_NOT_IMPLEMENTED; } + + + +/* + * + * Hypervisor register access functions. + * + */ + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegHyperGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) +{ + PVMCPU pVCpu = (PVMCPU)pvUser; + VMCPU_ASSERT_EMT(pVCpu); + + uint64_t u64Value; + switch (pDesc->offRegister) + { + case 0: u64Value = UINT64_MAX; break; + case 2: u64Value = UINT64_MAX; break; + case 3: u64Value = CPUMGetHyperCR3(pVCpu); break; + case 4: u64Value = UINT64_MAX; break; + case 8: u64Value = UINT64_MAX; break; + default: + AssertFailedReturn(VERR_INTERNAL_ERROR_3); + } + switch (pDesc->enmType) + { + case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break; + case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break; + default: + AssertFailedReturn(VERR_INTERNAL_ERROR_4); + } + return VINF_SUCCESS; +} + + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegHyperSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) +{ + /* Not settable, prevents killing your host. */ + return VERR_ACCESS_DENIED; +} + + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegHyperGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) +{ + PVMCPU pVCpu = (PVMCPU)pvUser; + void const *pv = (uint8_t const *)&pVCpu->cpum + pDesc->offRegister; + + VMCPU_ASSERT_EMT(pVCpu); + + uint64_t u64Value; + switch (pDesc->offRegister) + { + case 0: u64Value = CPUMGetHyperDR0(pVCpu); break; + case 1: u64Value = CPUMGetHyperDR1(pVCpu); break; + case 2: u64Value = CPUMGetHyperDR2(pVCpu); break; + case 3: u64Value = CPUMGetHyperDR3(pVCpu); break; + case 6: u64Value = CPUMGetHyperDR6(pVCpu); break; + case 7: u64Value = CPUMGetHyperDR7(pVCpu); break; + default: + AssertFailedReturn(VERR_INTERNAL_ERROR_3); + } + switch (pDesc->enmType) + { + case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break; + case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break; + default: + AssertFailedReturn(VERR_INTERNAL_ERROR_4); + } + return VINF_SUCCESS; +} + + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegHyperSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) +{ + /* Not settable, prevents killing your host. */ + return VERR_ACCESS_DENIED; +} + + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegHyperGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) +{ + /* Not availble at present, return all FFs to keep things quiet */ + uint64_t u64Value = UINT64_MAX; + switch (pDesc->enmType) + { + case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break; + case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break; + case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break; + default: + AssertFailedReturn(VERR_INTERNAL_ERROR_4); + } + return VINF_SUCCESS; +} + + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegHyperSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) +{ + /* Not settable, return failure. */ + NOREF(pvUser); NOREF(pDesc); NOREF(pValue); NOREF(pfMask); + return VERR_ACCESS_DENIED; +} + + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegHyperGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) +{ + PVMCPU pVCpu = (PVMCPU)pvUser; + + VMCPU_ASSERT_EMT(pVCpu); + Assert(pDesc->enmType == DBGFREGVALTYPE_R80); + + if (cpumR3RegIsFxSaveFormat(pVCpu)) + { + unsigned iReg = (pVCpu->cpum.s.Guest.fpu.FSW >> 11) & 7; + iReg += pDesc->offRegister; + iReg &= 7; + pValue->r80 = pVCpu->cpum.s.Guest.fpu.aRegs[iReg].r80; + } + else + { + PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.fpu; + + unsigned iReg = (pOldFpu->FSW >> 11) & 7; + iReg += pDesc->offRegister; + iReg &= 7; + + pValue->r80 = pOldFpu->regs[iReg].r80; + } + + return VINF_SUCCESS; +} + + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegHyperSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) +{ + /* There isn't a FPU context for the hypervisor yet, so no point in trying to set stuff. */ + return VERR_ACCESS_DENIED; +} + @@ -831,144 +1002,278 @@ - -/** - * The register descriptors. - */ -static DBGFREGDESC const g_aCpumRegDescs[] = -{ -#define CPUMREGDESC_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \ - { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, RT_OFFSETOF(CPUMCTX, a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields } -#define CPUMREGDESC_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \ - { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCTX, a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields } -#define CPUMREGDESC_EX_AS(a_szName, a_RegSuff, a_TypeSuff, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \ - { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields } - -#define CPUMREGDESC_REG(UName, LName) \ - CPUMREGDESC_RW_AS(#LName, UName, U64, LName, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_##LName, NULL) - CPUMREGDESC_REG(RAX, rax), - CPUMREGDESC_REG(RCX, rcx), - CPUMREGDESC_REG(RDX, rdx), - CPUMREGDESC_REG(RBX, rbx), - CPUMREGDESC_REG(RSP, rsp), - CPUMREGDESC_REG(RBP, rbp), - CPUMREGDESC_REG(RSI, rsi), - CPUMREGDESC_REG(RDI, rdi), - CPUMREGDESC_REG(R8, r8), - CPUMREGDESC_REG(R9, r9), - CPUMREGDESC_REG(R10, r10), - CPUMREGDESC_REG(R11, r11), - CPUMREGDESC_REG(R12, r12), - CPUMREGDESC_REG(R13, r13), - CPUMREGDESC_REG(R14, r14), - CPUMREGDESC_REG(R15, r15), -#define CPUMREGDESC_SEG(UName, LName) \ - CPUMREGDESC_RW_AS(#LName, UName, U16, LName, cpumR3RegGet_Generic, cpumR3RegSet_seg, NULL, NULL ), \ - CPUMREGDESC_RW_AS(#LName "_attr", UName##_ATTR, U32, LName##Hid.Attr.u, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_seg), \ - CPUMREGDESC_RW_AS(#LName "_base", UName##_BASE, U64, LName##Hid.u64Base, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), \ - CPUMREGDESC_RW_AS(#LName "_lim", UName##_LIMIT, U32, LName##Hid.u32Limit, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ) - CPUMREGDESC_SEG(CS, cs), - CPUMREGDESC_SEG(DS, ds), - CPUMREGDESC_SEG(ES, es), - CPUMREGDESC_SEG(FS, fs), - CPUMREGDESC_SEG(GS, gs), - CPUMREGDESC_SEG(SS, ss), - CPUMREGDESC_REG(RIP, rip), - CPUMREGDESC_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ), - CPUMREGDESC_RW_AS("fcw", FCW, U16, fpu.FCW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fcw ), - CPUMREGDESC_RW_AS("fsw", FSW, U16, fpu.FSW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fsw ), - CPUMREGDESC_RO_AS("ftw", FTW, U16, fpu.FTW, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ), - CPUMREGDESC_RW_AS("fop", FOP, U16, fpu.FOP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), - CPUMREGDESC_RW_AS("fpuip", FPUIP, U32, fpu.FPUIP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpuip, NULL ), - CPUMREGDESC_RW_AS("fpucs", FPUCS, U16, fpu.CS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), - CPUMREGDESC_RW_AS("fpudp", FPUDP, U32, fpu.FPUDP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpudp, NULL ), - CPUMREGDESC_RW_AS("fpuds", FPUDS, U16, fpu.DS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), - CPUMREGDESC_RW_AS("mxcsr", MXCSR, U32, fpu.MXCSR, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ), - CPUMREGDESC_RW_AS("mxcsr_mask", MXCSR_MASK, U32, fpu.MXCSR_MASK, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ), -#define CPUMREGDESC_ST(n) \ - CPUMREGDESC_RW_AS("st" #n, ST##n, R80, fpu.aRegs[n], cpumR3RegGet_stN, cpumR3RegSet_stN, NULL, g_aCpumRegFields_stN ) - CPUMREGDESC_ST(0), - CPUMREGDESC_ST(1), - CPUMREGDESC_ST(2), - CPUMREGDESC_ST(3), - CPUMREGDESC_ST(4), - CPUMREGDESC_ST(5), - CPUMREGDESC_ST(6), - CPUMREGDESC_ST(7), -#define CPUMREGDESC_MM(n) \ - CPUMREGDESC_RW_AS("mm" #n, MM##n, U64, fpu.aRegs[n].mmx, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mmN ) - CPUMREGDESC_MM(0), - CPUMREGDESC_MM(1), - CPUMREGDESC_MM(2), - CPUMREGDESC_MM(3), - CPUMREGDESC_MM(4), - CPUMREGDESC_MM(5), - CPUMREGDESC_MM(6), - CPUMREGDESC_MM(7), -#define CPUMREGDESC_XMM(n) \ - CPUMREGDESC_RW_AS("xmm" #n, XMM##n, U128, fpu.aXMM[n].xmm, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_xmmN ) - CPUMREGDESC_XMM(0), - CPUMREGDESC_XMM(1), - CPUMREGDESC_XMM(2), - CPUMREGDESC_XMM(3), - CPUMREGDESC_XMM(4), - CPUMREGDESC_XMM(5), - CPUMREGDESC_XMM(6), - CPUMREGDESC_XMM(7), - CPUMREGDESC_XMM(8), - CPUMREGDESC_XMM(9), - CPUMREGDESC_XMM(10), - CPUMREGDESC_XMM(11), - CPUMREGDESC_XMM(12), - CPUMREGDESC_XMM(13), - CPUMREGDESC_XMM(14), - CPUMREGDESC_XMM(15), - CPUMREGDESC_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), - CPUMREGDESC_RW_AS("gdtr_limit", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), - CPUMREGDESC_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), - CPUMREGDESC_RW_AS("idtr_limit", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), - CPUMREGDESC_SEG(LDTR, ldtr), - CPUMREGDESC_SEG(TR, tr), - CPUMREGDESC_EX_AS("cr0", CR0, U32, 0, cpumR3RegGet_crX, cpumR3RegSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ), - CPUMREGDESC_EX_AS("cr2", CR2, U64, 2, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, NULL ), - CPUMREGDESC_EX_AS("cr3", CR3, U64, 3, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, g_aCpumRegFields_cr3 ), - CPUMREGDESC_EX_AS("cr4", CR4, U32, 4, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, g_aCpumRegFields_cr4 ), - CPUMREGDESC_EX_AS("cr8", CR8, U32, 8, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, NULL ), - CPUMREGDESC_EX_AS("dr0", DR0, U64, 0, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL ), - CPUMREGDESC_EX_AS("dr1", DR1, U64, 1, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL ), - CPUMREGDESC_EX_AS("dr2", DR2, U64, 2, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL ), - CPUMREGDESC_EX_AS("dr3", DR3, U64, 3, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL ), - CPUMREGDESC_EX_AS("dr6", DR6, U32, 6, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, g_aCpumRegFields_dr6 ), - CPUMREGDESC_EX_AS("dr7", DR7, U32, 7, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, g_aCpumRegFields_dr7 ), -#define CPUMREGDESC_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \ - CPUMREGDESC_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, a_paSubFields ) - CPUMREGDESC_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ), - CPUMREGDESC_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ), - CPUMREGDESC_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status), - CPUMREGDESC_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ), - CPUMREGDESC_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ), - CPUMREGDESC_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ), - CPUMREGDESC_MSR("tsc", IA32_TSC, U32, NULL ), - CPUMREGDESC_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ), - CPUMREGDESC_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ), - CPUMREGDESC_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ), - CPUMREGDESC_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ), - CPUMREGDESC_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ), - CPUMREGDESC_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ), - CPUMREGDESC_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ), - CPUMREGDESC_MSR("sf_mask", K8_SF_MASK, U64, NULL ), - CPUMREGDESC_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ), - CPUMREGDESC_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCTX, rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), - CPUMREGDESC_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCTX, rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), - CPUMREGDESC_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCTX, rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), - CPUMREGDESC_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCTX, rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), - CPUMREGDESC_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ), - CPUMREGDESC_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ), +/** @name Macros for producing register descriptor table entries. + * @{ */ +#define CPU_REG_EX_AS(a_szName, a_RegSuff, a_TypeSuff, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \ + { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields } + +#define CPU_REG_REG(UName, LName) \ + CPU_REG_RW_AS(#LName, UName, U64, LName, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_##LName, NULL) + +#define CPU_REG_SEG(UName, LName) \ + CPU_REG_RW_AS(#LName, UName, U16, LName, cpumR3RegGet_Generic, cpumR3RegSet_seg, NULL, NULL ), \ + CPU_REG_RW_AS(#LName "_attr", UName##_ATTR, U32, LName##Hid.Attr.u, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_seg), \ + CPU_REG_RW_AS(#LName "_base", UName##_BASE, U64, LName##Hid.u64Base, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), \ + CPU_REG_RW_AS(#LName "_lim", UName##_LIMIT, U32, LName##Hid.u32Limit, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ) + +#define CPU_REG_MM(n) \ + CPU_REG_RW_AS("mm" #n, MM##n, U64, fpu.aRegs[n].mmx, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mmN) + +#define CPU_REG_XMM(n) \ + CPU_REG_RW_AS("xmm" #n, XMM##n, U128, fpu.aXMM[n].xmm, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_xmmN) +/** @} */ + + +/** + * The guest register descriptors. + */ +static DBGFREGDESC const g_aCpumRegGstDescs[] = +{ +#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \ + { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields } +#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \ + { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Guest.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields } +#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \ + CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegGstGet_msr, cpumR3RegGstSet_msr, NULL, a_paSubFields) +#define CPU_REG_ST(n) \ + CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegGstGet_stN, cpumR3RegGstSet_stN, NULL, g_aCpumRegFields_stN) + + CPU_REG_REG(RAX, rax), + CPU_REG_REG(RCX, rcx), + CPU_REG_REG(RDX, rdx), + CPU_REG_REG(RBX, rbx), + CPU_REG_REG(RSP, rsp), + CPU_REG_REG(RBP, rbp), + CPU_REG_REG(RSI, rsi), + CPU_REG_REG(RDI, rdi), + CPU_REG_REG(R8, r8), + CPU_REG_REG(R9, r9), + CPU_REG_REG(R10, r10), + CPU_REG_REG(R11, r11), + CPU_REG_REG(R12, r12), + CPU_REG_REG(R13, r13), + CPU_REG_REG(R14, r14), + CPU_REG_REG(R15, r15), + CPU_REG_SEG(CS, cs), + CPU_REG_SEG(DS, ds), + CPU_REG_SEG(ES, es), + CPU_REG_SEG(FS, fs), + CPU_REG_SEG(GS, gs), + CPU_REG_SEG(SS, ss), + CPU_REG_REG(RIP, rip), + CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ), + CPU_REG_RW_AS("fcw", FCW, U16, fpu.FCW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fcw ), + CPU_REG_RW_AS("fsw", FSW, U16, fpu.FSW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fsw ), + CPU_REG_RO_AS("ftw", FTW, U16, fpu, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ), + CPU_REG_RW_AS("fop", FOP, U16, fpu.FOP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_RW_AS("fpuip", FPUIP, U32, fpu.FPUIP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpuip, NULL ), + CPU_REG_RW_AS("fpucs", FPUCS, U16, fpu.CS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_RW_AS("fpudp", FPUDP, U32, fpu.FPUDP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpudp, NULL ), + CPU_REG_RW_AS("fpuds", FPUDS, U16, fpu.DS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_RW_AS("mxcsr", MXCSR, U32, fpu.MXCSR, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ), + CPU_REG_RW_AS("mxcsr_mask", MXCSR_MASK, U32, fpu.MXCSR_MASK, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ), + CPU_REG_ST(0), + CPU_REG_ST(1), + CPU_REG_ST(2), + CPU_REG_ST(3), + CPU_REG_ST(4), + CPU_REG_ST(5), + CPU_REG_ST(6), + CPU_REG_ST(7), + CPU_REG_MM(0), + CPU_REG_MM(1), + CPU_REG_MM(2), + CPU_REG_MM(3), + CPU_REG_MM(4), + CPU_REG_MM(5), + CPU_REG_MM(6), + CPU_REG_MM(7), + CPU_REG_XMM(0), + CPU_REG_XMM(1), + CPU_REG_XMM(2), + CPU_REG_XMM(3), + CPU_REG_XMM(4), + CPU_REG_XMM(5), + CPU_REG_XMM(6), + CPU_REG_XMM(7), + CPU_REG_XMM(8), + CPU_REG_XMM(9), + CPU_REG_XMM(10), + CPU_REG_XMM(11), + CPU_REG_XMM(12), + CPU_REG_XMM(13), + CPU_REG_XMM(14), + CPU_REG_XMM(15), + CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_RW_AS("gdtr_limit", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_RW_AS("idtr_limit", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_SEG(LDTR, ldtr), + CPU_REG_SEG(TR, tr), + CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ), + CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ), + CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr3 ), + CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, g_aCpumRegFields_cr4 ), + CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegGstGet_crX, cpumR3RegGstSet_crX, NULL, NULL ), + CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ), + CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ), + CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ), + CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, NULL ), + CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr6 ), + CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegGstGet_drX, cpumR3RegGstSet_drX, NULL, g_aCpumRegFields_dr7 ), + CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ), + CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ), + CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status), + CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ), + CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ), + CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ), + CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ), + CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ), + CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ), + CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ), + CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ), + CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ), + CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ), + CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ), + CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ), + CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ), + CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Guest.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Guest.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Guest.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Guest.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ), + CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ), DBGFREGDESC_TERMINATOR() -#undef CPUMREGDESC_REG -#undef CPUMREGDESC_SEG -#undef CPUMREGDESC_ST -#undef CPUMREGDESC_MM -#undef CPUMREGDESC_XMM -#undef CPUMREGDESC_MSR + +#undef CPU_REG_RW_AS +#undef CPU_REG_RO_AS +#undef CPU_REG_MSR +#undef CPU_REG_ST +}; + + +/** + * The hypervisor (raw-mode) register descriptors. + */ +static DBGFREGDESC const g_aCpumRegHyperDescs[] = +{ +#define CPU_REG_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \ + { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /*fFlags*/, RT_OFFSETOF(CPUMCPU, Hyper.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields } +#define CPU_REG_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \ + { a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCPU, Hyper.a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields } +#define CPU_REG_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \ + CPU_REG_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegHyperGet_msr, cpumR3RegHyperSet_msr, NULL, a_paSubFields) +#define CPU_REG_ST(n) \ + CPU_REG_EX_AS("st" #n, ST##n, R80, n, cpumR3RegHyperGet_stN, cpumR3RegHyperSet_stN, NULL, g_aCpumRegFields_stN) + + CPU_REG_REG(RAX, rax), + CPU_REG_REG(RCX, rcx), + CPU_REG_REG(RDX, rdx), + CPU_REG_REG(RBX, rbx), + CPU_REG_REG(RSP, rsp), + CPU_REG_REG(RBP, rbp), + CPU_REG_REG(RSI, rsi), + CPU_REG_REG(RDI, rdi), + CPU_REG_REG(R8, r8), + CPU_REG_REG(R9, r9), + CPU_REG_REG(R10, r10), + CPU_REG_REG(R11, r11), + CPU_REG_REG(R12, r12), + CPU_REG_REG(R13, r13), + CPU_REG_REG(R14, r14), + CPU_REG_REG(R15, r15), + CPU_REG_SEG(CS, cs), + CPU_REG_SEG(DS, ds), + CPU_REG_SEG(ES, es), + CPU_REG_SEG(FS, fs), + CPU_REG_SEG(GS, gs), + CPU_REG_SEG(SS, ss), + CPU_REG_REG(RIP, rip), + CPU_REG_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ), + CPU_REG_RW_AS("fcw", FCW, U16, fpu.FCW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fcw ), + CPU_REG_RW_AS("fsw", FSW, U16, fpu.FSW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fsw ), + CPU_REG_RO_AS("ftw", FTW, U16, fpu, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ), + CPU_REG_RW_AS("fop", FOP, U16, fpu.FOP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_RW_AS("fpuip", FPUIP, U32, fpu.FPUIP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpuip, NULL ), + CPU_REG_RW_AS("fpucs", FPUCS, U16, fpu.CS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_RW_AS("fpudp", FPUDP, U32, fpu.FPUDP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpudp, NULL ), + CPU_REG_RW_AS("fpuds", FPUDS, U16, fpu.DS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_RW_AS("mxcsr", MXCSR, U32, fpu.MXCSR, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ), + CPU_REG_RW_AS("mxcsr_mask", MXCSR_MASK, U32, fpu.MXCSR_MASK, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ), + CPU_REG_ST(0), + CPU_REG_ST(1), + CPU_REG_ST(2), + CPU_REG_ST(3), + CPU_REG_ST(4), + CPU_REG_ST(5), + CPU_REG_ST(6), + CPU_REG_ST(7), + CPU_REG_MM(0), + CPU_REG_MM(1), + CPU_REG_MM(2), + CPU_REG_MM(3), + CPU_REG_MM(4), + CPU_REG_MM(5), + CPU_REG_MM(6), + CPU_REG_MM(7), + CPU_REG_XMM(0), + CPU_REG_XMM(1), + CPU_REG_XMM(2), + CPU_REG_XMM(3), + CPU_REG_XMM(4), + CPU_REG_XMM(5), + CPU_REG_XMM(6), + CPU_REG_XMM(7), + CPU_REG_XMM(8), + CPU_REG_XMM(9), + CPU_REG_XMM(10), + CPU_REG_XMM(11), + CPU_REG_XMM(12), + CPU_REG_XMM(13), + CPU_REG_XMM(14), + CPU_REG_XMM(15), + CPU_REG_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_RW_AS("gdtr_limit", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_RW_AS("idtr_limit", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_SEG(LDTR, ldtr), + CPU_REG_SEG(TR, tr), + CPU_REG_EX_AS("cr0", CR0, U32, 0, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ), + CPU_REG_EX_AS("cr2", CR2, U64, 2, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, NULL ), + CPU_REG_EX_AS("cr3", CR3, U64, 3, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, g_aCpumRegFields_cr3 ), + CPU_REG_EX_AS("cr4", CR4, U32, 4, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, g_aCpumRegFields_cr4 ), + CPU_REG_EX_AS("cr8", CR8, U32, 8, cpumR3RegHyperGet_crX, cpumR3RegHyperSet_crX, NULL, NULL ), + CPU_REG_EX_AS("dr0", DR0, U64, 0, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ), + CPU_REG_EX_AS("dr1", DR1, U64, 1, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ), + CPU_REG_EX_AS("dr2", DR2, U64, 2, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ), + CPU_REG_EX_AS("dr3", DR3, U64, 3, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, NULL ), + CPU_REG_EX_AS("dr6", DR6, U32, 6, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr6 ), + CPU_REG_EX_AS("dr7", DR7, U32, 7, cpumR3RegHyperGet_drX, cpumR3RegHyperSet_drX, NULL, g_aCpumRegFields_dr7 ), + CPU_REG_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ), + CPU_REG_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ), + CPU_REG_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status), + CPU_REG_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ), + CPU_REG_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ), + CPU_REG_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ), + CPU_REG_MSR("tsc", IA32_TSC, U32, NULL ), + CPU_REG_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ), + CPU_REG_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ), + CPU_REG_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ), + CPU_REG_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ), + CPU_REG_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ), + CPU_REG_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ), + CPU_REG_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ), + CPU_REG_MSR("sf_mask", K8_SF_MASK, U64, NULL ), + CPU_REG_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ), + CPU_REG_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCPU, Hyper.rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), + CPU_REG_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ), + CPU_REG_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ), + DBGFREGDESC_TERMINATOR() +#undef CPU_REG_RW_AS +#undef CPU_REG_RO_AS +#undef CPU_REG_MSR +#undef CPU_REG_ST }; @@ -986,6 +1291,8 @@ for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++) { - int rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegDescs); + int rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegGstDescs, true /*fGuestRegs*/); AssertLogRelRCReturn(rc, rc); + rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegHyperDescs, false /*fGuestRegs*/); + AssertLogRelRCReturn(rc, rc); } Index: /trunk/src/VBox/VMM/VMMR3/DBGFReg.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/DBGFReg.cpp (revision 35600) +++ /trunk/src/VBox/VMM/VMMR3/DBGFReg.cpp (revision 35601) @@ -268,5 +268,6 @@ * pszPrefix when creating the set name. */ -static int dbgfR3RegRegisterCommon(PVM pVM, PCDBGFREGDESC paRegisters, DBGFREGSETTYPE enmType, void *pvUserArg, const char *pszPrefix, uint32_t iInstance) +static int dbgfR3RegRegisterCommon(PVM pVM, PCDBGFREGDESC paRegisters, DBGFREGSETTYPE enmType, void *pvUserArg, + const char *pszPrefix, uint32_t iInstance) { /* @@ -457,5 +458,8 @@ if (pRegSet->cDescs > DBGFREG_ALL_COUNT) pVM->dbgf.s.cRegs -= pRegSet->cDescs - DBGFREG_ALL_COUNT; - pVM->aCpus[iInstance].dbgf.s.pRegSet = pRegSet; + if (!strcmp(pszPrefix, "cpu")) + pVM->aCpus[iInstance].dbgf.s.pGuestRegSet = pRegSet; + else + pVM->aCpus[iInstance].dbgf.s.pHyperRegSet = pRegSet; } @@ -494,6 +498,8 @@ * @param pVCpu The virtual CPU handle. * @param paRegisters The register descriptors. - */ -VMMR3_INT_DECL(int) DBGFR3RegRegisterCpu(PVM pVM, PVMCPU pVCpu, PCDBGFREGDESC paRegisters) + * @param fGuestRegs Set if it's the guest registers, clear if + * hypervisor registers. + */ +VMMR3_INT_DECL(int) DBGFR3RegRegisterCpu(PVM pVM, PVMCPU pVCpu, PCDBGFREGDESC paRegisters, bool fGuestRegs) { if (!pVM->dbgf.s.fRegDbInitialized) @@ -504,5 +510,5 @@ } - return dbgfR3RegRegisterCommon(pVM, paRegisters, DBGFREGSETTYPE_CPU, pVCpu, "cpu", pVCpu->idCpu); + return dbgfR3RegRegisterCommon(pVM, paRegisters, DBGFREGSETTYPE_CPU, pVCpu, fGuestRegs ? "cpu" : "hypercpu", pVCpu->idCpu); } @@ -788,5 +794,5 @@ * Look up the register set of the specified CPU. */ - PDBGFREGSET pSet = pVM->aCpus[idCpu].dbgf.s.pRegSet; + PDBGFREGSET pSet = pVM->aCpus[idCpu].dbgf.s.pGuestRegSet; if (RT_LIKELY(pSet)) { @@ -1128,5 +1134,5 @@ VM_ASSERT_VALID_EXT_RETURN(pVM, NULL); - PCDBGFREGSET pSet = pVM->aCpus[0].dbgf.s.pRegSet; + PCDBGFREGSET pSet = pVM->aCpus[0].dbgf.s.pGuestRegSet; if (RT_UNLIKELY(!pSet)) return NULL; @@ -1726,11 +1732,11 @@ /* - * My CPU registers. + * My guest CPU registers. */ size_t iCpuReg = pVCpu->idCpu * DBGFREG_ALL_COUNT; - if (pVCpu->dbgf.s.pRegSet) + if (pVCpu->dbgf.s.pGuestRegSet) { if (iCpuReg < cRegs) - dbgfR3RegNmQueryAllInSet(pVCpu->dbgf.s.pRegSet, DBGFREG_ALL_COUNT, &paRegs[iCpuReg], cRegs - iCpuReg); + dbgfR3RegNmQueryAllInSet(pVCpu->dbgf.s.pGuestRegSet, DBGFREG_ALL_COUNT, &paRegs[iCpuReg], cRegs - iCpuReg); } else @@ -1738,9 +1744,21 @@ /* + * My hypervisor CPU registers. + */ + iCpuReg = pVM->cCpus * DBGFREG_ALL_COUNT + pVCpu->idCpu * DBGFREG_ALL_COUNT; + if (pVCpu->dbgf.s.pHyperRegSet) + { + if (iCpuReg < cRegs) + dbgfR3RegNmQueryAllInSet(pVCpu->dbgf.s.pHyperRegSet, DBGFREG_ALL_COUNT, &paRegs[iCpuReg], cRegs - iCpuReg); + } + else + dbgfR3RegNmQueryAllPadEntries(paRegs, cRegs, iCpuReg, DBGFREG_ALL_COUNT); + + /* * The primary CPU does all the other registers. */ if (pVCpu->idCpu == 0) { - pArgs->iReg = pVM->cCpus * DBGFREG_ALL_COUNT; + pArgs->iReg = pVM->cCpus * DBGFREG_ALL_COUNT * 2; RTStrSpaceEnumerate(&pVM->dbgf.s.RegSetSpace, dbgfR3RegNmQueryAllEnum, pArgs); dbgfR3RegNmQueryAllPadEntries(paRegs, cRegs, pArgs->iReg, cRegs); Index: /trunk/src/VBox/VMM/include/DBGFInternal.h =================================================================== --- /trunk/src/VBox/VMM/include/DBGFInternal.h (revision 35600) +++ /trunk/src/VBox/VMM/include/DBGFInternal.h (revision 35601) @@ -321,6 +321,8 @@ bool afReserved[7]; - /** The register set for this CPU. Can be NULL. */ - R3PTRTYPE(struct DBGFREGSET *) pRegSet; + /** The guest register set for this CPU. Can be NULL. */ + R3PTRTYPE(struct DBGFREGSET *) pGuestRegSet; + /** The hypervisor register set for this CPU. Can be NULL. */ + R3PTRTYPE(struct DBGFREGSET *) pHyperRegSet; } DBGFCPU; /** Pointer to DBGFCPU data. */ Index: /trunk/src/VBox/VMM/testcase/tstVMStructRC.cpp =================================================================== --- /trunk/src/VBox/VMM/testcase/tstVMStructRC.cpp (revision 35600) +++ /trunk/src/VBox/VMM/testcase/tstVMStructRC.cpp (revision 35601) @@ -134,5 +134,6 @@ GEN_CHECK_OFF(DBGFCPU, iActiveBp); GEN_CHECK_OFF(DBGFCPU, fSingleSteppingRaw); - GEN_CHECK_OFF(DBGFCPU, pRegSet); + GEN_CHECK_OFF(DBGFCPU, pGuestRegSet); + GEN_CHECK_OFF(DBGFCPU, pHyperRegSet); GEN_CHECK_SIZE(EM);