Index: /trunk/include/VBox/err.h =================================================================== --- /trunk/include/VBox/err.h (revision 35512) +++ /trunk/include/VBox/err.h (revision 35513) @@ -279,4 +279,6 @@ /** The requested type conversion was not supported. */ #define VERR_DBGF_UNSUPPORTED_CAST (-1213) +/** The register is read-only and cannot be modified. */ +#define VERR_DBGF_READ_ONLY_REGISTER (-1214) /** @} */ Index: /trunk/include/VBox/vmm/dbgf.h =================================================================== --- /trunk/include/VBox/vmm/dbgf.h (revision 35512) +++ /trunk/include/VBox/vmm/dbgf.h (revision 35513) @@ -1232,5 +1232,5 @@ DBGFREGVALTYPE_U128, /** Long double register value. */ - DBGFREGVALTYPE_LRD, + DBGFREGVALTYPE_R80, /** Descriptor table register value. */ DBGFREGVALTYPE_DTR, @@ -1253,5 +1253,5 @@ uint64_t u64; /**< The 64-bit view. */ RTUINT128U u128; /**< The 128-bit view. */ - long double lrd; /**< The long double view. */ + RTFLOAT80U2 r80; /**< The 80-bit floating point view. */ /** GDTR or LDTR (DBGFREGVALTYPE_DTR). */ struct @@ -1447,5 +1447,5 @@ VMMR3DECL(int) DBGFR3RegNmQueryU64( PVM pVM, VMCPUID idDefCpu, const char *pszReg, uint64_t *pu64); VMMR3DECL(int) DBGFR3RegNmQueryU128(PVM pVM, VMCPUID idDefCpu, const char *pszReg, PRTUINT128U pu128); -VMMR3DECL(int) DBGFR3RegNmQueryLrd( PVM pVM, VMCPUID idDefCpu, const char *pszReg, long double *plrd); +/*VMMR3DECL(int) DBGFR3RegNmQueryLrd( PVM pVM, VMCPUID idDefCpu, const char *pszReg, long double *plrd);*/ VMMR3DECL(int) DBGFR3RegNmQueryXdtr(PVM pVM, VMCPUID idDefCpu, const char *pszReg, uint64_t *pu64Base, uint16_t *pu16Limit); VMMR3DECL(int) DBGFR3RegNmQueryBatch(PVM pVM,VMCPUID idDefCpu, DBGFREGENTRYNM paRegs, size_t cRegs); Index: /trunk/include/VBox/x86.h =================================================================== --- /trunk/include/VBox/x86.h (revision 35512) +++ /trunk/include/VBox/x86.h (revision 35513) @@ -1935,4 +1935,6 @@ /** FPU view - todo. */ X86FPUMMX fpu; + /** Extended precision floating point view. */ + RTFLOAT80U2 r80; /** 8-bit view. */ uint8_t au8[16]; @@ -1987,4 +1989,6 @@ /** FPU view - todo. */ X86FPUMMX fpu; + /** Extended precision floating point view. */ + RTFLOAT80U2 r80; /** 8-bit view. */ uint8_t au8[16]; Index: /trunk/src/VBox/Debugger/DBGCOps.cpp =================================================================== --- /trunk/src/VBox/Debugger/DBGCOps.cpp (revision 35512) +++ /trunk/src/VBox/Debugger/DBGCOps.cpp (revision 35513) @@ -522,6 +522,10 @@ return VINF_SUCCESS; - case DBGFREGVALTYPE_LRD: - DBGCVAR_INIT_NUMBER(pResult, (uint64_t)Value.lrd); + case DBGFREGVALTYPE_R80: +#ifdef RT_COMPILER_WITH_80BIT_LONG_DOUBLE + DBGCVAR_INIT_NUMBER(pResult, (uint64_t)Value.r80.lrd); +#else + DBGCVAR_INIT_NUMBER(pResult, (uint64_t)Value.r80.sj64.u63Fraction); +#endif return VINF_SUCCESS; Index: /trunk/src/VBox/Main/src-client/MachineDebuggerImpl.cpp =================================================================== --- /trunk/src/VBox/Main/src-client/MachineDebuggerImpl.cpp (revision 35512) +++ /trunk/src/VBox/Main/src-client/MachineDebuggerImpl.cpp (revision 35513) @@ -1085,12 +1085,51 @@ return S_OK; - case DBGFREGVALTYPE_LRD: - /** @todo long double -> string conversion. */ - /** @todo long double == double on MSC. Stupid, stupid, - * microsoft! */ - RTStrFormatNumber(szHex, a_pValue->au16[5], 16, 2+4, 0, RTSTR_F_SPECIAL | RTSTR_F_ZEROPAD | RTSTR_F_16BIT); - RTStrFormatNumber(&szHex[2+4], a_pValue->au64[0], 16, 16, 0, RTSTR_F_ZEROPAD | RTSTR_F_64BIT); + case DBGFREGVALTYPE_R80: + { + char *pszHex = szHex; + if (a_pValue->r80.s.fSign) + *pszHex++ = '-'; + + if (a_pValue->r80.s.uExponent == 0) + { + if ( !a_pValue->r80.sj64.u63Fraction + && a_pValue->r80.sj64.fInteger) + *pszHex++ = '0'; + /* else: Denormal, handled way below. */ + } + else if (a_pValue->r80.sj64.uExponent == UINT16_C(0x7fff)) + { + /** @todo Figure out Pseudo inf/nan... */ + if (a_pValue->r80.sj64.fInteger) + *pszHex++ = 'P'; + if (a_pValue->r80.sj64.u63Fraction == 0) + { + *pszHex++ = 'I'; + *pszHex++ = 'n'; + *pszHex++ = 'f'; + } + else + { + *pszHex++ = 'N'; + *pszHex++ = 'a'; + *pszHex++ = 'N'; + } + } + if (pszHex != &szHex[1]) + *pszHex = '\0'; + else + { + *pszHex++ = a_pValue->r80.sj64.fInteger ? '1' : '0'; + *pszHex++ = 'm'; + pszHex += RTStrFormatNumber(pszHex, a_pValue->r80.sj64.u63Fraction, 16, 2+16, 0, + RTSTR_F_SPECIAL | RTSTR_F_ZEROPAD | RTSTR_F_64BIT); + + *pszHex++ = 'e'; + pszHex += RTStrFormatNumber(pszHex, (int32_t)a_pValue->r80.sj64.uExponent - 16383, 10, 0, 0, + RTSTR_F_ZEROPAD | RTSTR_F_32BIT | RTSTR_F_VALSIGNED); + } *a_pbstr = szHex; return S_OK; + } case DBGFREGVALTYPE_DTR: Index: /trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp (revision 35512) +++ /trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp (revision 35513) @@ -397,4 +397,55 @@ } + +/** + * Is the FPU state in FXSAVE format or not. + * + * @returns true if it is, false if it's in FNSAVE. + * @param pVCpu The virtual CPU handle. + */ +DECLINLINE(bool) cpumR3RegIsFxSaveFormat(PVMCPU pVCpu) +{ +#ifdef RT_ARCH_AMD64 + return true; +#else + return pVCpu->pVMR3->cpum.s.CPUFeatures.edx.u1FXSR; +#endif +} + + +/** + * Determins the tag register value for a CPU register when the FPU state + * format is FXSAVE. + * + * @returns The tag register value. + * @param pVCpu The virtual CPU handle. + * @param iReg The register number (0..7). + */ +DECLINLINE(uint16_t) cpumR3RegCalcFpuTagFromFxSave(PVMCPU pVCpu, unsigned iReg) +{ + /* + * See table 11-1 in the AMD docs. + */ + if (!(pVCpu->cpum.s.Guest.fpu.FTW & RT_BIT_32(iReg))) + return 3; /* b11 - empty */ + + uint16_t const uExp = pVCpu->cpum.s.Guest.fpu.aRegs[iReg].au16[4]; + if (uExp == 0) + { + if (pVCpu->cpum.s.Guest.fpu.aRegs[iReg].au64[0] == 0) /* J & M == 0 */ + return 1; /* b01 - zero */ + return 2; /* b10 - special */ + } + + if (uExp == UINT16_C(0xffff)) + return 2; /* b10 - special */ + + if (!(pVCpu->cpum.s.Guest.fpu.aRegs[iReg].au64[0] >> 63)) /* J == 0 */ + return 2; /* b10 - special */ + + return 0; /* b00 - valid (normal) */ +} + + /** * @interface_method_impl{DBGFREGDESC, pfnGet} @@ -402,6 +453,27 @@ static DECLCALLBACK(int) cpumR3RegGet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) { - return VERR_NOT_IMPLEMENTED; -} + PVMCPU pVCpu = (PVMCPU)pvUser; + void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest + pDesc->offRegister; + + VMCPU_ASSERT_EMT(pVCpu); + Assert(pDesc->enmType == DBGFREGVALTYPE_U16); + + if (cpumR3RegIsFxSaveFormat(pVCpu)) + pValue->u16 = cpumR3RegCalcFpuTagFromFxSave(pVCpu, 0) + | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 1) << 2) + | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 2) << 4) + | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 3) << 6) + | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 4) << 8) + | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 5) << 10) + | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 6) << 12) + | (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 7) << 14); + else + { + PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.fpu; + pValue->u16 = pOldFpu->FTW; + } + return VINF_SUCCESS; +} + /** @@ -410,6 +482,7 @@ static DECLCALLBACK(int) cpumR3RegSet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) { - return VERR_NOT_IMPLEMENTED; -} + return VERR_DBGF_READ_ONLY_REGISTER; +} + /** @@ -418,5 +491,29 @@ static DECLCALLBACK(int) cpumR3RegGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) { - return VERR_NOT_IMPLEMENTED; + PVMCPU pVCpu = (PVMCPU)pvUser; + void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest + pDesc->offRegister; + + VMCPU_ASSERT_EMT(pVCpu); + Assert(pDesc->enmType == DBGFREGVALTYPE_R80); + + if (cpumR3RegIsFxSaveFormat(pVCpu)) + { + unsigned iReg = (pVCpu->cpum.s.Guest.fpu.FSW >> 11) & 7; + iReg += pDesc->offRegister; + iReg &= 7; + pValue->r80 = pVCpu->cpum.s.Guest.fpu.aRegs[iReg].r80; + } + else + { + PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.fpu; + + unsigned iReg = (pOldFpu->FSW >> 11) & 7; + iReg += pDesc->offRegister; + iReg &= 7; + + pValue->r80 = pOldFpu->regs[iReg].r80; + } + + return VINF_SUCCESS; } @@ -780,5 +877,5 @@ CPUMREGDESC_RW_AS("fcw", FCW, U16, fpu.FCW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fcw ), CPUMREGDESC_RW_AS("fsw", FSW, U16, fpu.FSW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fsw ), - CPUMREGDESC_RW_AS("ftw", FTW, U16, fpu.FTW, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ), + CPUMREGDESC_RO_AS("ftw", FTW, U16, fpu.FTW, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ), CPUMREGDESC_RW_AS("fop", FOP, U16, fpu.FOP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), CPUMREGDESC_RW_AS("fpuip", FPUIP, U32, fpu.FPUIP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpuip, NULL ), @@ -789,5 +886,5 @@ CPUMREGDESC_RW_AS("mxcsr_mask", MXCSR_MASK, U32, fpu.MXCSR_MASK, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ), #define CPUMREGDESC_ST(n) \ - CPUMREGDESC_RW_AS("st" #n, ST##n, LRD, fpu.aRegs[n], cpumR3RegGet_stN, cpumR3RegSet_stN, NULL, g_aCpumRegFields_stN ) + CPUMREGDESC_RW_AS("st" #n, ST##n, R80, fpu.aRegs[n], cpumR3RegGet_stN, cpumR3RegSet_stN, NULL, g_aCpumRegFields_stN ) CPUMREGDESC_ST(0), CPUMREGDESC_ST(1), Index: /trunk/src/VBox/VMM/VMMR3/DBGFReg.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/DBGFReg.cpp (revision 35512) +++ /trunk/src/VBox/VMM/VMMR3/DBGFReg.cpp (revision 35513) @@ -470,4 +470,68 @@ /** + * Sets a 80-bit floating point variable to a 64-bit unsigned interger value. + * + * @param pValue The value. + * @param u64 The integer value. + */ +DECLINLINE(void) dbgfR3RegValR80SetU64(PDBGFREGVAL pValue, uint64_t u64) +{ + /** @todo fixme */ + pValue->r80.s.fSign = 0; + pValue->r80.s.uExponent = 16383; + pValue->r80.s.u64Mantissa = u64; +} + + +/** + * Sets a 80-bit floating point variable to a 64-bit unsigned interger value. + * + * @param pValue The value. + * @param u128 The integer value. + */ +DECLINLINE(void) dbgfR3RegValR80SetU128(PDBGFREGVAL pValue, RTUINT128U u128) +{ + /** @todo fixme */ + pValue->r80.s.fSign = 0; + pValue->r80.s.uExponent = 16383; + pValue->r80.s.u64Mantissa = u128.s.Lo; +} + + +/** + * Get a 80-bit floating point variable as a 64-bit unsigned integer. + * + * @returns 64-bit unsigned integer. + * @param pValue The value. + */ +DECLINLINE(uint64_t) dbgfR3RegValR80GetU64(PCDBGFREGVAL pValue) +{ + /** @todo stupid, stupid MSC. */ + return pValue->r80.s.u64Mantissa; +} + + +/** + * Get a 80-bit floating point variable as a 128-bit unsigned integer. + * + * @returns 128-bit unsigned integer. + * @param pValue The value. + */ +DECLINLINE(RTUINT128U) dbgfR3RegValR80GetU128(PCDBGFREGVAL pValue) +{ + /** @todo stupid, stupid MSC. */ + RTUINT128U uRet; +#if 0 + uRet.s.Lo = (uint64_t)InVal.lrd; + uRet.s.Hi = (uint64_t)InVal.lrd / _4G / _4G; +#else + uRet.s.Lo = pValue->r80.s.u64Mantissa; + uRet.s.Hi = 0; +#endif + return uRet; +} + + +/** * Performs a cast between register value types. * @@ -498,5 +562,5 @@ case DBGFREGVALTYPE_U64: pValue->u64 = InVal.u8; return VINF_DBGF_ZERO_EXTENDED_REGISTER; case DBGFREGVALTYPE_U128: pValue->u128.s.Lo = InVal.u8; return VINF_DBGF_ZERO_EXTENDED_REGISTER; - case DBGFREGVALTYPE_LRD: pValue->lrd = InVal.u8; return VINF_DBGF_ZERO_EXTENDED_REGISTER; + case DBGFREGVALTYPE_R80: dbgfR3RegValR80SetU64(pValue, InVal.u8); return VINF_DBGF_ZERO_EXTENDED_REGISTER; case DBGFREGVALTYPE_DTR: return VERR_DBGF_UNSUPPORTED_CAST; @@ -516,5 +580,5 @@ case DBGFREGVALTYPE_U64: pValue->u64 = InVal.u16; return VINF_DBGF_ZERO_EXTENDED_REGISTER; case DBGFREGVALTYPE_U128: pValue->u128.s.Lo = InVal.u16; return VINF_DBGF_ZERO_EXTENDED_REGISTER; - case DBGFREGVALTYPE_LRD: pValue->lrd = InVal.u16; return VINF_DBGF_ZERO_EXTENDED_REGISTER; + case DBGFREGVALTYPE_R80: dbgfR3RegValR80SetU64(pValue, InVal.u16); return VINF_DBGF_ZERO_EXTENDED_REGISTER; case DBGFREGVALTYPE_DTR: return VERR_DBGF_UNSUPPORTED_CAST; @@ -534,5 +598,5 @@ case DBGFREGVALTYPE_U64: pValue->u64 = InVal.u32; return VINF_DBGF_ZERO_EXTENDED_REGISTER; case DBGFREGVALTYPE_U128: pValue->u128.s.Lo = InVal.u32; return VINF_DBGF_ZERO_EXTENDED_REGISTER; - case DBGFREGVALTYPE_LRD: pValue->lrd = InVal.u32; return VINF_DBGF_ZERO_EXTENDED_REGISTER; + case DBGFREGVALTYPE_R80: dbgfR3RegValR80SetU64(pValue, InVal.u32); return VINF_DBGF_ZERO_EXTENDED_REGISTER; case DBGFREGVALTYPE_DTR: return VERR_DBGF_UNSUPPORTED_CAST; @@ -552,5 +616,5 @@ case DBGFREGVALTYPE_U64: pValue->u64 = InVal.u64; return VINF_SUCCESS; case DBGFREGVALTYPE_U128: pValue->u128.s.Lo = InVal.u64; return VINF_DBGF_TRUNCATED_REGISTER; - case DBGFREGVALTYPE_LRD: pValue->lrd = InVal.u64; return VINF_DBGF_ZERO_EXTENDED_REGISTER; + case DBGFREGVALTYPE_R80: dbgfR3RegValR80SetU64(pValue, InVal.u64); return VINF_DBGF_TRUNCATED_REGISTER; case DBGFREGVALTYPE_DTR: return VERR_DBGF_UNSUPPORTED_CAST; @@ -570,5 +634,5 @@ case DBGFREGVALTYPE_U64: pValue->u64 = InVal.u128.s.Lo; return VINF_DBGF_TRUNCATED_REGISTER; case DBGFREGVALTYPE_U128: pValue->u128 = InVal.u128; return VINF_SUCCESS; - case DBGFREGVALTYPE_LRD: pValue->lrd = InVal.u64; return VINF_DBGF_TRUNCATED_REGISTER; + case DBGFREGVALTYPE_R80: dbgfR3RegValR80SetU128(pValue, InVal.u128); return VINF_DBGF_TRUNCATED_REGISTER; case DBGFREGVALTYPE_DTR: return VERR_DBGF_UNSUPPORTED_CAST; @@ -580,17 +644,14 @@ break; - case DBGFREGVALTYPE_LRD: + case DBGFREGVALTYPE_R80: switch (enmToType) { - case DBGFREGVALTYPE_U8: pValue->u8 = (uint8_t)InVal.lrd; return VINF_DBGF_TRUNCATED_REGISTER; - case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)InVal.lrd; return VINF_DBGF_TRUNCATED_REGISTER; - case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)InVal.lrd; return VINF_DBGF_TRUNCATED_REGISTER; - case DBGFREGVALTYPE_U64: pValue->u64 = (uint64_t)InVal.lrd; return VINF_DBGF_TRUNCATED_REGISTER; - case DBGFREGVALTYPE_U128: - pValue->u128.s.Lo = (uint64_t)InVal.lrd; - pValue->u128.s.Hi = (uint64_t)InVal.lrd / _4G / _4G; - return VINF_DBGF_TRUNCATED_REGISTER; - case DBGFREGVALTYPE_LRD: pValue->lrd = InVal.lrd; return VINF_SUCCESS; - case DBGFREGVALTYPE_DTR: return VERR_DBGF_UNSUPPORTED_CAST; + case DBGFREGVALTYPE_U8: pValue->u8 = (uint8_t )dbgfR3RegValR80GetU64(&InVal); return VINF_DBGF_TRUNCATED_REGISTER; + case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)dbgfR3RegValR80GetU64(&InVal); return VINF_DBGF_TRUNCATED_REGISTER; + case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)dbgfR3RegValR80GetU64(&InVal); return VINF_DBGF_TRUNCATED_REGISTER; + case DBGFREGVALTYPE_U64: pValue->u64 = (uint64_t)dbgfR3RegValR80GetU64(&InVal); return VINF_DBGF_TRUNCATED_REGISTER; + case DBGFREGVALTYPE_U128: pValue->u128 = dbgfR3RegValR80GetU128(&InVal); return VINF_DBGF_TRUNCATED_REGISTER; + case DBGFREGVALTYPE_R80: pValue->r80 = InVal.r80; return VINF_SUCCESS; + case DBGFREGVALTYPE_DTR: return VERR_DBGF_UNSUPPORTED_CAST; case DBGFREGVALTYPE_32BIT_HACK: @@ -609,5 +670,5 @@ case DBGFREGVALTYPE_U64: pValue->u64 = InVal.dtr.u64Base; return VINF_DBGF_TRUNCATED_REGISTER; case DBGFREGVALTYPE_U128: pValue->u128.s.Lo = InVal.dtr.u64Base; return VINF_DBGF_TRUNCATED_REGISTER; - case DBGFREGVALTYPE_LRD: pValue->lrd = InVal.dtr.u64Base; return VINF_DBGF_TRUNCATED_REGISTER; + case DBGFREGVALTYPE_R80: dbgfR3RegValR80SetU64(pValue, InVal.dtr.u64Base); return VINF_DBGF_TRUNCATED_REGISTER; case DBGFREGVALTYPE_DTR: pValue->dtr = InVal.dtr; return VINF_SUCCESS; @@ -873,5 +934,5 @@ pReg->Val.au64[1] = pu->au64[1]; break; - case DBGFREGVALTYPE_LRD: + case DBGFREGVALTYPE_R80: pReg->Val.au64[0] = pu->au64[0]; pReg->Val.au16[5] = pu->au16[5]; @@ -1417,4 +1478,5 @@ +#if 0 /** * Queries a long double register value. @@ -1439,5 +1501,5 @@ { DBGFREGVAL Value; - int rc = dbgfR3RegNmQueryWorker(pVM, idDefCpu, pszReg, DBGFREGVALTYPE_LRD, &Value, NULL); + int rc = dbgfR3RegNmQueryWorker(pVM, idDefCpu, pszReg, DBGFREGVALTYPE_R80, &Value, NULL); if (RT_SUCCESS(rc)) *plrd = Value.lrd; @@ -1446,4 +1508,5 @@ return rc; } +#endif