Index: /trunk/include/VBox/vmm/dbgf.h =================================================================== --- /trunk/include/VBox/vmm/dbgf.h (revision 35467) +++ /trunk/include/VBox/vmm/dbgf.h (revision 35468) @@ -1305,4 +1305,13 @@ /** @} */ +/** Macro for creating a read-write sub-field entry without getters. */ +#define DBGFREGSUBFIELD_RW(a_szName, a_iFirstBit, a_cBits, a_cShift) \ + { a_szName, a_iFirstBit, a_cBits, a_cShift, 0 /*fFlags*/, NULL /*pfnGet*/, NULL /*pfnSet*/ } +/** Macro for creating a read-write sub-field entry with getters. */ +#define DBGFREGSUBFIELD_RW_SG(a_szName, a_cBits, a_cShift, a_pfnGet, a_pfnSet) \ + { a_szName, 0 /*iFirstBit*/, a_cBits, a_cShift, 0 /*fFlags*/, a_pfnGet, a_pfnSet } +/** Macro for creating a terminator sub-field entry. */ +#define DBGFREGSUBFIELD_TERMINATOR() \ + { NULL, 0, 0, 0, 0, NULL, NULL } /** @@ -1337,7 +1346,7 @@ uint32_t offRegister; /** Getter. */ - DECLCALLBACKMEMBER(int, pfnGet)(void *pvUser, struct DBGFREGDESC const *pDesc, PDBGFREGVAL puValue); + DECLCALLBACKMEMBER(int, pfnGet)(void *pvUser, struct DBGFREGDESC const *pDesc, PDBGFREGVAL pValue); /** Setter. */ - DECLCALLBACKMEMBER(int, pfnSet)(void *pvUser, struct DBGFREGDESC const *pDesc, PCDBGFREGVAL puValue, PCDBGFREGVAL pfMask); + DECLCALLBACKMEMBER(int, pfnSet)(void *pvUser, struct DBGFREGDESC const *pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask); /** Aliases (optional). */ PCDBGFREGALIAS paAliases; Index: /trunk/src/VBox/VMM/Makefile.kmk =================================================================== --- /trunk/src/VBox/VMM/Makefile.kmk (revision 35467) +++ /trunk/src/VBox/VMM/Makefile.kmk (revision 35468) @@ -78,4 +78,5 @@ VMMR3/CFGM.cpp \ VMMR3/CPUM.cpp \ + VMMR3/CPUMDbg.cpp \ VMMR3/DBGF.cpp \ VMMR3/DBGFAddr.cpp \ Index: /trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp (revision 35467) +++ /trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp (revision 35468) @@ -5,5 +5,5 @@ /* - * Copyright (C) 2010 Oracle Corporation + * Copyright (C) 2010-2011 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as @@ -21,87 +21,168 @@ *******************************************************************************/ #define LOG_GROUP LOG_GROUP_DBGF +#include #include -#include "DBGFInternal.h" +#include "CPUMInternal.h" #include #include #include #include - - -static DECLCALLBACK(int) dbgfR3RegSet_seg(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask) -{ - return VERR_NOT_IMPLEMENTED; -} - -static DECLCALLBACK(int) dbgfR3RegGet_crX(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue) -{ - return VERR_NOT_IMPLEMENTED; -} - -static DECLCALLBACK(int) dbgfR3RegSet_crX(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask) -{ - return VERR_NOT_IMPLEMENTED; -} - -static DECLCALLBACK(int) dbgfR3RegGet_drX(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue) -{ - return VERR_NOT_IMPLEMENTED; -} - -static DECLCALLBACK(int) dbgfR3RegSet_drX(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask) -{ - return VERR_NOT_IMPLEMENTED; -} - -static DECLCALLBACK(int) dbgfR3RegGet_msr(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue) -{ - return VERR_NOT_IMPLEMENTED; -} - -static DECLCALLBACK(int) dbgfR3RegSet_msr(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask) -{ - return VERR_NOT_IMPLEMENTED; -} - -static DECLCALLBACK(int) dbgfR3RegGet_gdtr(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue) -{ - return VERR_NOT_IMPLEMENTED; -} - -static DECLCALLBACK(int) dbgfR3RegSet_gdtr(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask) -{ - return VERR_NOT_IMPLEMENTED; -} - -static DECLCALLBACK(int) dbgfR3RegGet_idtr(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue) -{ - return VERR_NOT_IMPLEMENTED; -} - -static DECLCALLBACK(int) dbgfR3RegSet_idtr(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask) -{ - return VERR_NOT_IMPLEMENTED; -} - -static DECLCALLBACK(int) dbgfR3RegGet_ftw(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue) -{ - return VERR_NOT_IMPLEMENTED; -} - -static DECLCALLBACK(int) dbgfR3RegSet_ftw(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask) -{ - return VERR_NOT_IMPLEMENTED; -} - -static DECLCALLBACK(int) dbgfR3RegGet_stN(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue) -{ - return VERR_NOT_IMPLEMENTED; -} - -static DECLCALLBACK(int) dbgfR3RegSet_stN(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask) -{ - return VERR_NOT_IMPLEMENTED; -} - +#include + + +#if 0 +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegGet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) +{ + PVMCPU pVCpu = (PVMCPU)pvUser; + void const *pv = (uint8_t const *)&pVCpu->cpum.s.Guest + pDesc->offRegister; + + VMCPU_ASSERT_EMT(pVCpu); + + switch (pDesc->enmType) + { + case DBGFREGVALTYPE_U8: pValue->u8 = *(uint8_t const *)pv; return VINF_SUCCESS; + case DBGFREGVALTYPE_U16: pValue->u16 = *(uint16_t const *)pv; return VINF_SUCCESS; + case DBGFREGVALTYPE_U32: pValue->u32 = *(uint32_t const *)pv; return VINF_SUCCESS; + case DBGFREGVALTYPE_U64: pValue->u64 = *(uint64_t const *)pv; return VINF_SUCCESS; + case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS; + default: + AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_INTERNAL_ERROR_3); + } +} + + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegSet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) +{ + PVMCPU pVCpu = (PVMCPU)pvUser; + void *pv = (uint8_t *)&pVCpu->cpum.s.Guest + pDesc->offRegister; + + VMCPU_ASSERT_EMT(pVCpu); + + switch (pDesc->enmType) + { + case DBGFREGVALTYPE_U8: + *(uint8_t *)pv &= ~pfMask->u8; + *(uint8_t *)pv |= pValue->u8 & pfMask->u8; + return VINF_SUCCESS; + + case DBGFREGVALTYPE_U16: + *(uint16_t *)pv &= ~pfMask->u16; + *(uint16_t *)pv |= pValue->u16 & pfMask->u16; + return VINF_SUCCESS; + + case DBGFREGVALTYPE_U32: + *(uint32_t *)pv &= ~pfMask->u32; + *(uint32_t *)pv |= pValue->u32 & pfMask->u32; + return VINF_SUCCESS; + + case DBGFREGVALTYPE_U64: + *(uint64_t *)pv &= ~pfMask->u64; + *(uint64_t *)pv |= pValue->u64 & pfMask->u64; + return VINF_SUCCESS; + + case DBGFREGVALTYPE_U128: + ((PRTUINT128U)pv)->s.Hi &= ~pfMask->u128.s.Hi; + ((PRTUINT128U)pv)->s.Lo &= ~pfMask->u128.s.Lo; + ((PRTUINT128U)pv)->s.Hi |= pValue->u128.s.Hi & pfMask->u128.s.Hi; + ((PRTUINT128U)pv)->s.Lo |= pValue->u128.s.Lo & pfMask->u128.s.Lo; + return VINF_SUCCESS; + + default: + AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_INTERNAL_ERROR_3); + } +} + + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegSet_seg(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) +{ + /** @todo perform a selector load, updating hidden selectors and stuff. */ + return VERR_NOT_IMPLEMENTED; +} + + +static DECLCALLBACK(int) cpumR3RegGet_crX(PVMCPU pVCpu, PCDBGFREGDESC pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue) +{ + return VERR_NOT_IMPLEMENTED; +} + +static DECLCALLBACK(int) cpumR3RegSet_crX(PVMCPU pVCpu, PCDBGFREGDESC pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask) +{ + return VERR_NOT_IMPLEMENTED; +} + +static DECLCALLBACK(int) cpumR3RegGet_drX(PVMCPU pVCpu, PCDBGFREGDESC pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue) +{ + return VERR_NOT_IMPLEMENTED; +} + +static DECLCALLBACK(int) cpumR3RegSet_drX(PVMCPU pVCpu, PCDBGFREGDESC pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask) +{ + return VERR_NOT_IMPLEMENTED; +} + +static DECLCALLBACK(int) cpumR3RegGet_msr(PVMCPU pVCpu, PCDBGFREGDESC pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue) +{ + return VERR_NOT_IMPLEMENTED; +} + +static DECLCALLBACK(int) cpumR3RegSet_msr(PVMCPU pVCpu, PCDBGFREGDESC pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask) +{ + return VERR_NOT_IMPLEMENTED; +} + +static DECLCALLBACK(int) cpumR3RegGet_gdtr(PVMCPU pVCpu, PCDBGFREGDESC pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue) +{ + return VERR_NOT_IMPLEMENTED; +} + +static DECLCALLBACK(int) cpumR3RegSet_gdtr(PVMCPU pVCpu, PCDBGFREGDESC pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask) +{ + return VERR_NOT_IMPLEMENTED; +} + +static DECLCALLBACK(int) cpumR3RegGet_idtr(PVMCPU pVCpu, PCDBGFREGDESC pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue) +{ + return VERR_NOT_IMPLEMENTED; +} + +static DECLCALLBACK(int) cpumR3RegSet_idtr(PVMCPU pVCpu, PCDBGFREGDESC pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask) +{ + return VERR_NOT_IMPLEMENTED; +} + +static DECLCALLBACK(int) cpumR3RegGet_ftw(PVMCPU pVCpu, PCDBGFREGDESC pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue) +{ + return VERR_NOT_IMPLEMENTED; +} + +static DECLCALLBACK(int) cpumR3RegSet_ftw(PVMCPU pVCpu, PCDBGFREGDESC pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask) +{ + return VERR_NOT_IMPLEMENTED; +} + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) +{ + return VERR_NOT_IMPLEMENTED; +} + +/** + * @interface_method_impl{DBGFREGDESC, pfnGet} + */ +static DECLCALLBACK(int) cpumR3RegSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) +{ + return VERR_NOT_IMPLEMENTED; +} @@ -109,33 +190,33 @@ * Set up aliases. */ -#define DBGFREGALIAS_STD(Name, psz32, psz16, psz8) \ - static DBGFREGALIAS const g_aDbgfRegAliases_##Name[] = \ +#define CPUMREGALIAS_STD(Name, psz32, psz16, psz8) \ + static DBGFREGALIAS const g_aCpumRegAliases_##Name[] = \ { \ - { psz32, DBGFREGVALTYPE_U32 }, \ - { psz16, DBGFREGVALTYPE_U16 }, \ - { psz8, DBGFREGVALTYPE_U8 }, \ - { NULL, DBGFREGVALTYPE_INVALID } \ + { psz32, DBGFREGVALTYPE_U32 }, \ + { psz16, DBGFREGVALTYPE_U16 }, \ + { psz8, DBGFREGVALTYPE_U8 }, \ + { NULL, DBGFREGVALTYPE_INVALID } \ } -DBGFREGALIAS_STD(rax, "eax", "ax", "al"); -DBGFREGALIAS_STD(rcx, "ecx", "cx", "cl"); -DBGFREGALIAS_STD(rdx, "edx", "dx", "dl"); -DBGFREGALIAS_STD(rbx, "ebx", "bx", "bl"); -DBGFREGALIAS_STD(rsp, "esp", "sp", NULL); -DBGFREGALIAS_STD(rbp, "ebp", "bp", NULL); -DBGFREGALIAS_STD(rsi, "esi", "si", "sil"); -DBGFREGALIAS_STD(rdi, "edi", "di", "dil"); -DBGFREGALIAS_STD(r8, "r8d", "r8w", "r8b"); -DBGFREGALIAS_STD(r9, "r9d", "r9w", "r9b"); -DBGFREGALIAS_STD(r10, "r10d", "r10w", "r10b"); -DBGFREGALIAS_STD(r11, "r11d", "r11w", "r11b"); -DBGFREGALIAS_STD(r12, "r12d", "r12w", "r12b"); -DBGFREGALIAS_STD(r13, "r13d", "r13w", "r13b"); -DBGFREGALIAS_STD(r14, "r14d", "r14w", "r14b"); -DBGFREGALIAS_STD(r15, "r15d", "r15w", "r15b"); -DBGFREGALIAS_STD(rip, "eip", "ip", NULL); -DBGFREGALIAS_STD(rflags, "eflags", "flags", NULL); -#undef DBGFREGALIAS_STD - -static DBGFREGALIAS const g_aDbgfRegAliases_fpuip[] = +CPUMREGALIAS_STD(rax, "eax", "ax", "al"); +CPUMREGALIAS_STD(rcx, "ecx", "cx", "cl"); +CPUMREGALIAS_STD(rdx, "edx", "dx", "dl"); +CPUMREGALIAS_STD(rbx, "ebx", "bx", "bl"); +CPUMREGALIAS_STD(rsp, "esp", "sp", NULL); +CPUMREGALIAS_STD(rbp, "ebp", "bp", NULL); +CPUMREGALIAS_STD(rsi, "esi", "si", "sil"); +CPUMREGALIAS_STD(rdi, "edi", "di", "dil"); +CPUMREGALIAS_STD(r8, "r8d", "r8w", "r8b"); +CPUMREGALIAS_STD(r9, "r9d", "r9w", "r9b"); +CPUMREGALIAS_STD(r10, "r10d", "r10w", "r10b"); +CPUMREGALIAS_STD(r11, "r11d", "r11w", "r11b"); +CPUMREGALIAS_STD(r12, "r12d", "r12w", "r12b"); +CPUMREGALIAS_STD(r13, "r13d", "r13w", "r13b"); +CPUMREGALIAS_STD(r14, "r14d", "r14w", "r14b"); +CPUMREGALIAS_STD(r15, "r15d", "r15w", "r15b"); +CPUMREGALIAS_STD(rip, "eip", "ip", NULL); +CPUMREGALIAS_STD(rflags, "eflags", "flags", NULL); +#undef CPUMREGALIAS_STD + +static DBGFREGALIAS const g_aCpumRegAliases_fpuip[] = { { "fpuip", DBGFREGVALTYPE_U16 }, @@ -143,5 +224,5 @@ }; -static DBGFREGALIAS const g_aDbgfRegAliases_fpudp[] = +static DBGFREGALIAS const g_aCpumRegAliases_fpudp[] = { { "fpudp", DBGFREGVALTYPE_U16 }, @@ -149,5 +230,5 @@ }; -static DBGFREGALIAS const g_aDbgfRegAliases_cr0[] = +static DBGFREGALIAS const g_aCpumRegAliases_cr0[] = { { "msw", DBGFREGVALTYPE_U16 }, @@ -159,252 +240,252 @@ */ /** Sub-fields for the (hidden) segment attribute register. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_seg[] = -{ - { "type", 0, 4, 0 }, - { "s", 4, 1, 0 }, - { "dpl", 5, 2, 0 }, - { "p", 7, 1, 0 }, - { "avl", 12, 1, 0 }, - { "l", 13, 1, 0 }, - { "d", 14, 1, 0 }, - { "g", 15, 1, 0 }, - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_seg[] = +{ + DBGFREGSUBFIELD_RW("type", 0, 4, 0), + DBGFREGSUBFIELD_RW("s", 4, 1, 0), + DBGFREGSUBFIELD_RW("dpl", 5, 2, 0), + DBGFREGSUBFIELD_RW("p", 7, 1, 0), + DBGFREGSUBFIELD_RW("avl", 12, 1, 0), + DBGFREGSUBFIELD_RW("l", 13, 1, 0), + DBGFREGSUBFIELD_RW("d", 14, 1, 0), + DBGFREGSUBFIELD_RW("g", 15, 1, 0), + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the flags register. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_rflags[] = -{ - { "cf", 0, 1, 0 }, - { "pf", 2, 1, 0 }, - { "af", 4, 1, 0 }, - { "zf", 6, 1, 0 }, - { "sf", 7, 1, 0 }, - { "tf", 8, 1, 0 }, - { "if", 9, 1, 0 }, - { "df", 10, 1, 0 }, - { "of", 11, 1, 0 }, - { "iopl", 12, 2, 0 }, - { "nt", 14, 1, 0 }, - { "rf", 16, 1, 0 }, - { "vm", 17, 1, 0 }, - { "ac", 18, 1, 0 }, - { "vif", 19, 1, 0 }, - { "vip", 20, 1, 0 }, - { "id", 21, 1, 0 }, - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_rflags[] = +{ + DBGFREGSUBFIELD_RW("cf", 0, 1, 0), + DBGFREGSUBFIELD_RW("pf", 2, 1, 0), + DBGFREGSUBFIELD_RW("af", 4, 1, 0), + DBGFREGSUBFIELD_RW("zf", 6, 1, 0), + DBGFREGSUBFIELD_RW("sf", 7, 1, 0), + DBGFREGSUBFIELD_RW("tf", 8, 1, 0), + DBGFREGSUBFIELD_RW("if", 9, 1, 0), + DBGFREGSUBFIELD_RW("df", 10, 1, 0), + DBGFREGSUBFIELD_RW("of", 11, 1, 0), + DBGFREGSUBFIELD_RW("iopl", 12, 2, 0), + DBGFREGSUBFIELD_RW("nt", 14, 1, 0), + DBGFREGSUBFIELD_RW("rf", 16, 1, 0), + DBGFREGSUBFIELD_RW("vm", 17, 1, 0), + DBGFREGSUBFIELD_RW("ac", 18, 1, 0), + DBGFREGSUBFIELD_RW("vif", 19, 1, 0), + DBGFREGSUBFIELD_RW("vip", 20, 1, 0), + DBGFREGSUBFIELD_RW("id", 21, 1, 0), + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the FPU control word register. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_fcw[] = -{ - { "im", 1, 1, 0 }, - { "dm", 2, 1, 0 }, - { "zm", 3, 1, 0 }, - { "om", 4, 1, 0 }, - { "um", 5, 1, 0 }, - { "pm", 6, 1, 0 }, - { "pc", 8, 2, 0 }, - { "rc", 10, 2, 0 }, - { "x", 12, 1, 0 }, - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_fcw[] = +{ + DBGFREGSUBFIELD_RW("im", 1, 1, 0), + DBGFREGSUBFIELD_RW("dm", 2, 1, 0), + DBGFREGSUBFIELD_RW("zm", 3, 1, 0), + DBGFREGSUBFIELD_RW("om", 4, 1, 0), + DBGFREGSUBFIELD_RW("um", 5, 1, 0), + DBGFREGSUBFIELD_RW("pm", 6, 1, 0), + DBGFREGSUBFIELD_RW("pc", 8, 2, 0), + DBGFREGSUBFIELD_RW("rc", 10, 2, 0), + DBGFREGSUBFIELD_RW("x", 12, 1, 0), + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the FPU status word register. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_fsw[] = -{ - { "ie", 0, 1, 0 }, - { "de", 1, 1, 0 }, - { "ze", 2, 1, 0 }, - { "oe", 3, 1, 0 }, - { "ue", 4, 1, 0 }, - { "pe", 5, 1, 0 }, - { "se", 6, 1, 0 }, - { "es", 7, 1, 0 }, - { "c0", 8, 1, 0 }, - { "c1", 9, 1, 0 }, - { "c2", 10, 1, 0 }, - { "top", 11, 3, 0 }, - { "c3", 14, 1, 0 }, - { "b", 15, 1, 0 }, - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_fsw[] = +{ + DBGFREGSUBFIELD_RW("ie", 0, 1, 0), + DBGFREGSUBFIELD_RW("de", 1, 1, 0), + DBGFREGSUBFIELD_RW("ze", 2, 1, 0), + DBGFREGSUBFIELD_RW("oe", 3, 1, 0), + DBGFREGSUBFIELD_RW("ue", 4, 1, 0), + DBGFREGSUBFIELD_RW("pe", 5, 1, 0), + DBGFREGSUBFIELD_RW("se", 6, 1, 0), + DBGFREGSUBFIELD_RW("es", 7, 1, 0), + DBGFREGSUBFIELD_RW("c0", 8, 1, 0), + DBGFREGSUBFIELD_RW("c1", 9, 1, 0), + DBGFREGSUBFIELD_RW("c2", 10, 1, 0), + DBGFREGSUBFIELD_RW("top", 11, 3, 0), + DBGFREGSUBFIELD_RW("c3", 14, 1, 0), + DBGFREGSUBFIELD_RW("b", 15, 1, 0), + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the FPU tag word register. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_ftw[] = -{ - { "tag0", 0, 2, 0 }, - { "tag1", 2, 2, 0 }, - { "tag2", 4, 2, 0 }, - { "tag3", 6, 2, 0 }, - { "tag4", 8, 2, 0 }, - { "tag5", 10, 2, 0 }, - { "tag6", 12, 2, 0 }, - { "tag7", 14, 2, 0 }, - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_ftw[] = +{ + DBGFREGSUBFIELD_RW("tag0", 0, 2, 0), + DBGFREGSUBFIELD_RW("tag1", 2, 2, 0), + DBGFREGSUBFIELD_RW("tag2", 4, 2, 0), + DBGFREGSUBFIELD_RW("tag3", 6, 2, 0), + DBGFREGSUBFIELD_RW("tag4", 8, 2, 0), + DBGFREGSUBFIELD_RW("tag5", 10, 2, 0), + DBGFREGSUBFIELD_RW("tag6", 12, 2, 0), + DBGFREGSUBFIELD_RW("tag7", 14, 2, 0), + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the Multimedia Extensions Control and Status Register. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_mxcsr[] = -{ - { "ie", 0, 1, 0 }, - { "de", 1, 1, 0 }, - { "ze", 2, 1, 0 }, - { "oe", 3, 1, 0 }, - { "ue", 4, 1, 0 }, - { "pe", 5, 1, 0 }, - { "daz", 6, 1, 0 }, - { "im", 7, 1, 0 }, - { "dm", 8, 1, 0 }, - { "zm", 9, 1, 0 }, - { "om", 10, 1, 0 }, - { "um", 11, 1, 0 }, - { "pm", 12, 1, 0 }, - { "rc", 13, 2, 0 }, - { "fz", 14, 1, 0 }, - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_mxcsr[] = +{ + DBGFREGSUBFIELD_RW("ie", 0, 1, 0), + DBGFREGSUBFIELD_RW("de", 1, 1, 0), + DBGFREGSUBFIELD_RW("ze", 2, 1, 0), + DBGFREGSUBFIELD_RW("oe", 3, 1, 0), + DBGFREGSUBFIELD_RW("ue", 4, 1, 0), + DBGFREGSUBFIELD_RW("pe", 5, 1, 0), + DBGFREGSUBFIELD_RW("daz", 6, 1, 0), + DBGFREGSUBFIELD_RW("im", 7, 1, 0), + DBGFREGSUBFIELD_RW("dm", 8, 1, 0), + DBGFREGSUBFIELD_RW("zm", 9, 1, 0), + DBGFREGSUBFIELD_RW("om", 10, 1, 0), + DBGFREGSUBFIELD_RW("um", 11, 1, 0), + DBGFREGSUBFIELD_RW("pm", 12, 1, 0), + DBGFREGSUBFIELD_RW("rc", 13, 2, 0), + DBGFREGSUBFIELD_RW("fz", 14, 1, 0), + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the FPU tag word register. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_stN[] = -{ - { "man", 0, 64, 0 }, - { "exp", 64, 15, 0 }, - { "sig", 79, 1, 0 }, - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_stN[] = +{ + DBGFREGSUBFIELD_RW("man", 0, 64, 0), + DBGFREGSUBFIELD_RW("exp", 64, 15, 0), + DBGFREGSUBFIELD_RW("sig", 79, 1, 0), + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the MMX registers. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_mmN[] = -{ - { "dw0", 0, 32, 0 }, - { "dw1", 32, 32, 0 }, - { "w0", 0, 16, 0 }, - { "w1", 16, 16, 0 }, - { "w2", 32, 16, 0 }, - { "w3", 48, 16, 0 }, - { "b0", 0, 8, 0 }, - { "b1", 8, 8, 0 }, - { "b2", 16, 8, 0 }, - { "b3", 24, 8, 0 }, - { "b4", 32, 8, 0 }, - { "b5", 40, 8, 0 }, - { "b6", 48, 8, 0 }, - { "b7", 56, 8, 0 }, - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_mmN[] = +{ + DBGFREGSUBFIELD_RW("dw0", 0, 32, 0), + DBGFREGSUBFIELD_RW("dw1", 32, 32, 0), + DBGFREGSUBFIELD_RW("w0", 0, 16, 0), + DBGFREGSUBFIELD_RW("w1", 16, 16, 0), + DBGFREGSUBFIELD_RW("w2", 32, 16, 0), + DBGFREGSUBFIELD_RW("w3", 48, 16, 0), + DBGFREGSUBFIELD_RW("b0", 0, 8, 0), + DBGFREGSUBFIELD_RW("b1", 8, 8, 0), + DBGFREGSUBFIELD_RW("b2", 16, 8, 0), + DBGFREGSUBFIELD_RW("b3", 24, 8, 0), + DBGFREGSUBFIELD_RW("b4", 32, 8, 0), + DBGFREGSUBFIELD_RW("b5", 40, 8, 0), + DBGFREGSUBFIELD_RW("b6", 48, 8, 0), + DBGFREGSUBFIELD_RW("b7", 56, 8, 0), + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the XMM registers. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_xmmN[] = -{ - { "r0", 0, 32, 0 }, - { "r0.man", 0+ 0, 23, 0 }, - { "r0.exp", 0+23, 8, 0 }, - { "r0.sig", 0+31, 1, 0 }, - { "r1", 32, 32, 0 }, - { "r1.man", 32+ 0, 23, 0 }, - { "r1.exp", 32+23, 8, 0 }, - { "r1.sig", 32+31, 1, 0 }, - { "r2", 64, 32, 0 }, - { "r2.man", 64+ 0, 23, 0 }, - { "r2.exp", 64+23, 8, 0 }, - { "r2.sig", 64+31, 1, 0 }, - { "r3", 96, 32, 0 }, - { "r3.man", 96+ 0, 23, 0 }, - { "r3.exp", 96+23, 8, 0 }, - { "r3.sig", 96+31, 1, 0 }, - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_xmmN[] = +{ + DBGFREGSUBFIELD_RW("r0", 0, 32, 0), + DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0), + DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0), + DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0), + DBGFREGSUBFIELD_RW("r1", 32, 32, 0), + DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0), + DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0), + DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0), + DBGFREGSUBFIELD_RW("r2", 64, 32, 0), + DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0), + DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0), + DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0), + DBGFREGSUBFIELD_RW("r3", 96, 32, 0), + DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0), + DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0), + DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0), + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the CR0 register. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_cr0[] = -{ - /** @todo */ - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_cr0[] = +{ + /** @todo */ + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the CR3 register. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_cr3[] = -{ - /** @todo */ - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_cr3[] = +{ + /** @todo */ + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the CR4 register. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_cr4[] = -{ - /** @todo */ - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_cr4[] = +{ + /** @todo */ + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the DR6 register. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_dr6[] = -{ - /** @todo */ - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_dr6[] = +{ + /** @todo */ + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the DR7 register. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_dr7[] = -{ - /** @todo */ - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_dr7[] = +{ + /** @todo */ + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the CR_PAT MSR. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_apic_base[] = -{ - { "bsp", 8, 1, 0 }, - { "ge", 9, 1, 0 }, - { "base", 12, 20, 12 }, - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_apic_base[] = +{ + DBGFREGSUBFIELD_RW("bsp", 8, 1, 0), + DBGFREGSUBFIELD_RW("ge", 9, 1, 0), + DBGFREGSUBFIELD_RW("base", 12, 20, 12), + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the CR_PAT MSR. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_cr_pat[] = -{ - /** @todo */ - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_cr_pat[] = +{ + /** @todo */ + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the PERF_STATUS MSR. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_perf_status[] = -{ - /** @todo */ - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_perf_status[] = +{ + /** @todo */ + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the EFER MSR. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_efer[] = -{ - /** @todo */ - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_efer[] = +{ + /** @todo */ + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the STAR MSR. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_star[] = -{ - /** @todo */ - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_star[] = +{ + /** @todo */ + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the CSTAR MSR. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_cstar[] = -{ - /** @todo */ - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_cstar[] = +{ + /** @todo */ + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the LSTAR MSR. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_lstar[] = -{ - /** @todo */ - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_lstar[] = +{ + /** @todo */ + DBGFREGSUBFIELD_TERMINATOR() }; /** Sub-fields for the SF_MASK MSR. */ -static DBGFREGSUBFIELD const g_aDbgfRegFields_sf_mask[] = -{ - /** @todo */ - { NULL, 0, 0, 0 } +static DBGFREGSUBFIELD const g_aCpumRegFields_sf_mask[] = +{ + /** @todo */ + DBGFREGSUBFIELD_TERMINATOR() }; @@ -414,127 +495,128 @@ * The register descriptors. */ -static DBGFREGDESC const g_aDbgfRegDescs[] = -{ -#define DBGFREGDESC_REG(UName, LName) \ - { #LName, DBGFREG_##UName, DBGFREGVALTYPE_U64, RT_OFFSETOF(CPUMCTX, LName), NULL, NULL, g_aDbgfRegAliases_##LName, NULL } - DBGFREGDESC_REG(RAX, rax), - DBGFREGDESC_REG(RCX, rcx), - DBGFREGDESC_REG(RDX, rdx), - DBGFREGDESC_REG(RSP, rsp), - DBGFREGDESC_REG(RBP, rbp), - DBGFREGDESC_REG(RSI, rsi), - DBGFREGDESC_REG(RDI, rdi), - DBGFREGDESC_REG(R8, r8), - DBGFREGDESC_REG(R9, r9), - DBGFREGDESC_REG(R10, r10), - DBGFREGDESC_REG(R11, r11), - DBGFREGDESC_REG(R12, r12), - DBGFREGDESC_REG(R13, r13), - DBGFREGDESC_REG(R14, r14), - DBGFREGDESC_REG(R15, r15), -#define DBGFREGDESC_SEG(UName, LName) \ - { #LName, DBGFREG_##UName, DBGFREGVALTYPE_U16, RT_OFFSETOF(CPUMCTX, LName), NULL, dbgfR3RegSet_seg, NULL, NULL }, \ - { #LName "_attr", DBGFREG_##UName##_ATTR, DBGFREGVALTYPE_U32, RT_OFFSETOF(CPUMCTX, LName##Hid.Attr.u), NULL, NULL, NULL, g_aDbgfRegFields_seg }, \ - { #LName "_base", DBGFREG_##UName##_ATTR, DBGFREGVALTYPE_U64, RT_OFFSETOF(CPUMCTX, LName##Hid.u64Base), NULL, NULL, NULL, NULL }, \ - { #LName "_lim", DBGFREG_##UName##_ATTR, DBGFREGVALTYPE_U32, RT_OFFSETOF(CPUMCTX, LName##Hid.u32Limit), NULL, NULL, NULL, NULL } - DBGFREGDESC_SEG(CS, cs), - DBGFREGDESC_SEG(DS, ds), - DBGFREGDESC_SEG(ES, es), - DBGFREGDESC_SEG(FS, fs), - DBGFREGDESC_SEG(GS, gs), - DBGFREGDESC_SEG(SS, ss), - DBGFREGDESC_REG(RIP, rip), - { "rflags", DBGFREG_RFLAGS, DBGFREGVALTYPE_U64, RT_OFFSETOF(CPUMCTX, rflags), NULL, NULL, g_aDbgfRegAliases_rflags, g_aDbgfRegFields_rflags }, - { "fcw", DBGFREG_FCW, DBGFREGVALTYPE_U16, RT_OFFSETOF(CPUMCTX, fpu.FCW), NULL, NULL, NULL, g_aDbgfRegFields_fcw }, - { "fsw", DBGFREG_FSW, DBGFREGVALTYPE_U16, RT_OFFSETOF(CPUMCTX, fpu.FSW), NULL, NULL, NULL, g_aDbgfRegFields_fsw }, - { "ftw", DBGFREG_FTW, DBGFREGVALTYPE_U16, RT_OFFSETOF(CPUMCTX, fpu.FTW), dbgfR3RegGet_ftw, dbgfR3RegSet_ftw, NULL, g_aDbgfRegFields_ftw }, - { "fop", DBGFREG_FOP, DBGFREGVALTYPE_U16, RT_OFFSETOF(CPUMCTX, fpu.FOP), NULL, NULL, NULL, NULL }, - { "fpuip", DBGFREG_FPUIP, DBGFREGVALTYPE_U32, RT_OFFSETOF(CPUMCTX, fpu.FPUIP), NULL, NULL, g_aDbgfRegAliases_fpuip, NULL }, - { "fpucs", DBGFREG_FPUCS, DBGFREGVALTYPE_U16, RT_OFFSETOF(CPUMCTX, fpu.CS), NULL, NULL, NULL, NULL }, - { "fpudp", DBGFREG_FPUDP, DBGFREGVALTYPE_U32, RT_OFFSETOF(CPUMCTX, fpu.FPUDP), NULL, NULL, g_aDbgfRegAliases_fpudp, NULL }, - { "fpuds", DBGFREG_FPUDS, DBGFREGVALTYPE_U16, RT_OFFSETOF(CPUMCTX, fpu.DS), NULL, NULL, NULL, NULL }, - { "mxcsr", DBGFREG_MXCSR, DBGFREGVALTYPE_U32, RT_OFFSETOF(CPUMCTX, fpu.MXCSR), NULL, NULL, NULL, g_aDbgfRegFields_mxcsr }, - { "mxcsr_mask", DBGFREG_MXCSR_MASK, DBGFREGVALTYPE_U32, RT_OFFSETOF(CPUMCTX, fpu.MXCSR_MASK), NULL, NULL, NULL, g_aDbgfRegFields_mxcsr }, -#define DBGFREGDESC_ST(n) \ - { "st" #n, DBGFREG_ST##n, DBGFREGVALTYPE_80, ~(size_t)0, dbgfR3RegGet_stN, dbgfR3RegSet_stN, NULL, g_aDbgfRegFields_stN } - DBGFREGDESC_ST(0), - DBGFREGDESC_ST(1), - DBGFREGDESC_ST(2), - DBGFREGDESC_ST(3), - DBGFREGDESC_ST(4), - DBGFREGDESC_ST(5), - DBGFREGDESC_ST(6), - DBGFREGDESC_ST(7), -#define DBGFREGDESC_MM(n) \ - { "mm" #n, DBGFREG_MM##n, DBGFREGVALTYPE_U64, RT_OFFSETOF(CPUMCTX, fpu.aRegs[n].mmx), NULL, NULL, NULL, g_aDbgfRegFields_mmN } - DBGFREGDESC_MM(0), - DBGFREGDESC_MM(1), - DBGFREGDESC_MM(2), - DBGFREGDESC_MM(3), - DBGFREGDESC_MM(4), - DBGFREGDESC_MM(5), - DBGFREGDESC_MM(6), - DBGFREGDESC_MM(7), -#define DBGFREGDESC_XMM(n) \ - { "xmm" #n, DBGFREG_XMM##n, DBGFREGVALTYPE_U128, RT_OFFSETOF(CPUMCTX, fpu.aXMM[n].xmm), NULL, NULL, NULL, g_aDbgfRegFields_xmmN } - DBGFREGDESC_XMM(0), - DBGFREGDESC_XMM(1), - DBGFREGDESC_XMM(2), - DBGFREGDESC_XMM(3), - DBGFREGDESC_XMM(4), - DBGFREGDESC_XMM(5), - DBGFREGDESC_XMM(6), - DBGFREGDESC_XMM(7), - DBGFREGDESC_XMM(8), - DBGFREGDESC_XMM(9), - DBGFREGDESC_XMM(10), - DBGFREGDESC_XMM(11), - DBGFREGDESC_XMM(12), - DBGFREGDESC_XMM(13), - DBGFREGDESC_XMM(14), - DBGFREGDESC_XMM(15), - { "gdtr_base", DBGFREG_GDTR_BASE, DBGFREGVALTYPE_U64, RT_OFFSETOF(CPUMCTX, gdtr.pGdt), NULL, NULL, NULL, NULL }, - { "gdtr_limit", DBGFREG_GDTR_LIMIT, DBGFREGVALTYPE_U16, RT_OFFSETOF(CPUMCTX, gdtr.cbGdt), NULL, NULL, NULL, NULL }, - { "idtr_base", DBGFREG_IDTR_BASE, DBGFREGVALTYPE_U64, RT_OFFSETOF(CPUMCTX, idtr.pIdt), NULL, NULL, NULL, NULL }, - { "idtr_limit", DBGFREG_IDTR_LIMIT, DBGFREGVALTYPE_U16, RT_OFFSETOF(CPUMCTX, idtr.cbIdt), NULL, NULL, NULL, NULL }, - DBGFREGDESC_SEG(LDTR, ldtr), - DBGFREGDESC_SEG(TR, tr), - { "cr0", DBGFREG_CR0, DBGFREGVALTYPE_U32, 0, dbgfR3RegGet_crX, dbgfR3RegSet_crX, g_aDbgfRegAliases_cr0, g_aDbgfRegFields_cr0 }, - { "cr2", DBGFREG_CR2, DBGFREGVALTYPE_U64, 2, dbgfR3RegGet_crX, dbgfR3RegSet_crX, NULL, NULL }, - { "cr3", DBGFREG_CR3, DBGFREGVALTYPE_U64, 3, dbgfR3RegGet_crX, dbgfR3RegSet_crX, NULL, g_aDbgfRegFields_cr3 }, - { "cr4", DBGFREG_CR4, DBGFREGVALTYPE_U32, 4, dbgfR3RegGet_crX, dbgfR3RegSet_crX, NULL, g_aDbgfRegFields_cr4 }, - { "cr8", DBGFREG_CR8, DBGFREGVALTYPE_U32, 8, dbgfR3RegGet_crX, dbgfR3RegSet_crX, NULL, NULL }, - { "dr0", DBGFREG_DR0, DBGFREGVALTYPE_U64, 0, dbgfR3RegGet_drX, dbgfR3RegSet_drX, NULL, NULL }, - { "dr1", DBGFREG_DR1, DBGFREGVALTYPE_U64, 1, dbgfR3RegGet_drX, dbgfR3RegSet_drX, NULL, NULL }, - { "dr2", DBGFREG_DR2, DBGFREGVALTYPE_U64, 2, dbgfR3RegGet_drX, dbgfR3RegSet_drX, NULL, NULL }, - { "dr3", DBGFREG_DR3, DBGFREGVALTYPE_U64, 3, dbgfR3RegGet_drX, dbgfR3RegSet_drX, NULL, NULL }, - { "dr6", DBGFREG_DR6, DBGFREGVALTYPE_U32, 6, dbgfR3RegGet_drX, dbgfR3RegSet_drX, NULL, g_aDbgfRegFields_dr6 }, - { "dr7", DBGFREG_DR7, DBGFREGVALTYPE_U32, 7, dbgfR3RegGet_drX, dbgfR3RegSet_drX, NULL, g_aDbgfRegFields_dr7 }, - { "apic_base", DBGFREG_MSR_IA32_APICBASE, DBGFREGVALTYPE_U32, MSR_IA32_APICBASE, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, g_aDbgfRegFields_apic_base }, - { "pat", DBGFREG_MSR_IA32_CR_PAT, DBGFREGVALTYPE_U64, MSR_IA32_CR_PAT, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, g_aDbgfRegFields_cr_pat }, - { "perf_status", DBGFREG_MSR_IA32_PERF_STATUS, DBGFREGVALTYPE_U64, MSR_IA32_PERF_STATUS, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, g_aDbgfRegFields_perf_status }, - { "sysenter_cs", DBGFREG_MSR_IA32_SYSENTER_CS, DBGFREGVALTYPE_U16, MSR_IA32_SYSENTER_CS, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, NULL }, - { "sysenter_eip", DBGFREG_MSR_IA32_SYSENTER_EIP, DBGFREGVALTYPE_U32, MSR_IA32_SYSENTER_EIP, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, NULL }, - { "sysenter_esp", DBGFREG_MSR_IA32_SYSENTER_ESP, DBGFREGVALTYPE_U32, MSR_IA32_SYSENTER_ESP, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, NULL }, - { "tsc", DBGFREG_MSR_IA32_TSC, DBGFREGVALTYPE_U32, MSR_IA32_TSC, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, NULL }, - { "efer", DBGFREG_MSR_K6_EFER, DBGFREGVALTYPE_U32, MSR_K6_EFER, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, g_aDbgfRegFields_efer }, - { "star", DBGFREG_MSR_K6_STAR, DBGFREGVALTYPE_U64, MSR_K6_STAR, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, g_aDbgfRegFields_star }, - { "cstar", DBGFREG_MSR_K8_CSTAR, DBGFREGVALTYPE_U64, MSR_K8_CSTAR, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, g_aDbgfRegFields_cstar }, - { "msr_fs_base", DBGFREG_MSR_K8_FS_BASE, DBGFREGVALTYPE_U64, MSR_K8_FS_BASE, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, NULL }, - { "msr_gs_base", DBGFREG_MSR_K8_GS_BASE, DBGFREGVALTYPE_U64, MSR_K8_GS_BASE, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, NULL }, - { "krnl_gs_base", DBGFREG_MSR_K8_KERNEL_GS_BASE, DBGFREGVALTYPE_U64, MSR_K8_KERNEL_GS_BASE, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, NULL }, - { "lstar", DBGFREG_MSR_K8_LSTAR, DBGFREGVALTYPE_U64, MSR_K8_LSTAR, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, g_aDbgfRegFields_lstar }, - { "tsc_aux", DBGFREG_MSR_K8_TSC_AUX, DBGFREGVALTYPE_U64, MSR_K8_TSC_AUX, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, NULL }, - { "ah", DBGFREG_AH, DBGFREGVALTYPE_U8, RT_OFFSETOF(CPUMCTX, rax) + 1, NULL, NULL, NULL, NULL }, - { "ch", DBGFREG_CH, DBGFREGVALTYPE_U8, RT_OFFSETOF(CPUMCTX, rcx) + 1, NULL, NULL, NULL, NULL }, - { "dh", DBGFREG_DH, DBGFREGVALTYPE_U8, RT_OFFSETOF(CPUMCTX, rdx) + 1, NULL, NULL, NULL, NULL }, - { "bh", DBGFREG_BH, DBGFREGVALTYPE_U8, RT_OFFSETOF(CPUMCTX, rbx) + 1, NULL, NULL, NULL, NULL }, - { "gdtr", DBGFREG_GDTR, DBGFREGVALTYPE_DTR, ~(size_t)0, dbgfR3RegGet_gdtr, dbgfR3RegSet_gdtr, NULL, NULL }, - { "idtr", DBGFREG_IDTR, DBGFREGVALTYPE_DTR, ~(size_t)0, dbgfR3RegGet_idtr, dbgfR3RegSet_idtr, NULL, NULL }, -#undef DBGFREGDESC_REG -#undef DBGFREGDESC_SEG -#undef DBGFREGDESC_ST -#undef DBGFREGDESC_MM -#undef DBGFREGDESC_XMM -}; - +static DBGFREGDESC const g_aCpumRegDescs[] = +{ +#define CPUMREGDESC_REG(UName, LName) \ + { #LName, DBGFREG_##UName, DBGFREGVALTYPE_U64, 0, RT_OFFSETOF(CPUMCTX, LName), cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_##LName, NULL } + CPUMREGDESC_REG(RAX, rax), + CPUMREGDESC_REG(RCX, rcx), + CPUMREGDESC_REG(RDX, rdx), + CPUMREGDESC_REG(RSP, rsp), + CPUMREGDESC_REG(RBP, rbp), + CPUMREGDESC_REG(RSI, rsi), + CPUMREGDESC_REG(RDI, rdi), + CPUMREGDESC_REG(R8, r8), + CPUMREGDESC_REG(R9, r9), + CPUMREGDESC_REG(R10, r10), + CPUMREGDESC_REG(R11, r11), + CPUMREGDESC_REG(R12, r12), + CPUMREGDESC_REG(R13, r13), + CPUMREGDESC_REG(R14, r14), + CPUMREGDESC_REG(R15, r15), +#define CPUMREGDESC_SEG(UName, LName) \ + { #LName, DBGFREG_##UName, DBGFREGVALTYPE_U16, 0, RT_OFFSETOF(CPUMCTX, LName), cpumR3RegGet_Generic, cpumR3RegSet_seg, NULL, NULL }, \ + { #LName "_attr", DBGFREG_##UName##_ATTR, DBGFREGVALTYPE_U32, 0, RT_OFFSETOF(CPUMCTX, LName##Hid.Attr.u), cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_seg }, \ + { #LName "_base", DBGFREG_##UName##_ATTR, DBGFREGVALTYPE_U64, 0, RT_OFFSETOF(CPUMCTX, LName##Hid.u64Base), cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL }, \ + { #LName "_lim", DBGFREG_##UName##_ATTR, DBGFREGVALTYPE_U32, 0, RT_OFFSETOF(CPUMCTX, LName##Hid.u32Limit), cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL } + CPUMREGDESC_SEG(CS, cs), + CPUMREGDESC_SEG(DS, ds), + CPUMREGDESC_SEG(ES, es), + CPUMREGDESC_SEG(FS, fs), + CPUMREGDESC_SEG(GS, gs), + CPUMREGDESC_SEG(SS, ss), + CPUMREGDESC_REG(RIP, rip), + { "rflags", DBGFREG_RFLAGS, DBGFREGVALTYPE_U64, 0, RT_OFFSETOF(CPUMCTX, rflags), cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags }, + { "fcw", DBGFREG_FCW, DBGFREGVALTYPE_U16, 0, RT_OFFSETOF(CPUMCTX, fpu.FCW), cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fcw }, + { "fsw", DBGFREG_FSW, DBGFREGVALTYPE_U16, 0, RT_OFFSETOF(CPUMCTX, fpu.FSW), cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fsw }, + { "ftw", DBGFREG_FTW, DBGFREGVALTYPE_U16, 0, RT_OFFSETOF(CPUMCTX, fpu.FTW), cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw }, + { "fop", DBGFREG_FOP, DBGFREGVALTYPE_U16, 0, RT_OFFSETOF(CPUMCTX, fpu.FOP), cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL }, + { "fpuip", DBGFREG_FPUIP, DBGFREGVALTYPE_U32, 0, RT_OFFSETOF(CPUMCTX, fpu.FPUIP), cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpuip, NULL }, + { "fpucs", DBGFREG_FPUCS, DBGFREGVALTYPE_U16, 0, RT_OFFSETOF(CPUMCTX, fpu.CS), cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL }, + { "fpudp", DBGFREG_FPUDP, DBGFREGVALTYPE_U32, 0, RT_OFFSETOF(CPUMCTX, fpu.FPUDP), cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpudp, NULL }, + { "fpuds", DBGFREG_FPUDS, DBGFREGVALTYPE_U16, 0, RT_OFFSETOF(CPUMCTX, fpu.DS), cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL }, + { "mxcsr", DBGFREG_MXCSR, DBGFREGVALTYPE_U32, 0, RT_OFFSETOF(CPUMCTX, fpu.MXCSR), cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr }, + { "mxcsr_mask", DBGFREG_MXCSR_MASK, DBGFREGVALTYPE_U32, 0, RT_OFFSETOF(CPUMCTX, fpu.MXCSR_MASK), cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr }, +#define CPUMREGDESC_ST(n) \ + { "st" #n, DBGFREG_ST##n, DBGFREGVALTYPE_LRD, 0, ~(size_t)0, cpumR3RegGet_stN, cpumR3RegSet_stN, NULL, g_aCpumRegFields_stN } + CPUMREGDESC_ST(0), + CPUMREGDESC_ST(1), + CPUMREGDESC_ST(2), + CPUMREGDESC_ST(3), + CPUMREGDESC_ST(4), + CPUMREGDESC_ST(5), + CPUMREGDESC_ST(6), + CPUMREGDESC_ST(7), +#define CPUMREGDESC_MM(n) \ + { "mm" #n, DBGFREG_MM##n, DBGFREGVALTYPE_U64, 0, RT_OFFSETOF(CPUMCTX, fpu.aRegs[n].mmx), cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mmN } + CPUMREGDESC_MM(0), + CPUMREGDESC_MM(1), + CPUMREGDESC_MM(2), + CPUMREGDESC_MM(3), + CPUMREGDESC_MM(4), + CPUMREGDESC_MM(5), + CPUMREGDESC_MM(6), + CPUMREGDESC_MM(7), +#define CPUMREGDESC_XMM(n) \ + { "xmm" #n, DBGFREG_XMM##n, DBGFREGVALTYPE_U128, 0, RT_OFFSETOF(CPUMCTX, fpu.aXMM[n].xmm), cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_xmmN } + CPUMREGDESC_XMM(0), + CPUMREGDESC_XMM(1), + CPUMREGDESC_XMM(2), + CPUMREGDESC_XMM(3), + CPUMREGDESC_XMM(4), + CPUMREGDESC_XMM(5), + CPUMREGDESC_XMM(6), + CPUMREGDESC_XMM(7), + CPUMREGDESC_XMM(8), + CPUMREGDESC_XMM(9), + CPUMREGDESC_XMM(10), + CPUMREGDESC_XMM(11), + CPUMREGDESC_XMM(12), + CPUMREGDESC_XMM(13), + CPUMREGDESC_XMM(14), + CPUMREGDESC_XMM(15), + { "gdtr_base", DBGFREG_GDTR_BASE, DBGFREGVALTYPE_U64, 0, RT_OFFSETOF(CPUMCTX, gdtr.pGdt), cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL }, + { "gdtr_limit", DBGFREG_GDTR_LIMIT, DBGFREGVALTYPE_U16, 0, RT_OFFSETOF(CPUMCTX, gdtr.cbGdt), cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL }, + { "idtr_base", DBGFREG_IDTR_BASE, DBGFREGVALTYPE_U64, 0, RT_OFFSETOF(CPUMCTX, idtr.pIdt), cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL }, + { "idtr_limit", DBGFREG_IDTR_LIMIT, DBGFREGVALTYPE_U16, 0, RT_OFFSETOF(CPUMCTX, idtr.cbIdt), cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL }, + CPUMREGDESC_SEG(LDTR, ldtr), + CPUMREGDESC_SEG(TR, tr), + { "cr0", DBGFREG_CR0, DBGFREGVALTYPE_U32, 0, 0, cpumR3RegGet_crX, cpumR3RegSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 }, + { "cr2", DBGFREG_CR2, DBGFREGVALTYPE_U64, 0, 2, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, NULL }, + { "cr3", DBGFREG_CR3, DBGFREGVALTYPE_U64, 0, 3, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, g_aCpumRegFields_cr3 }, + { "cr4", DBGFREG_CR4, DBGFREGVALTYPE_U32, 0, 4, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, g_aCpumRegFields_cr4 }, + { "cr8", DBGFREG_CR8, DBGFREGVALTYPE_U32, 0, 8, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, NULL }, + { "dr0", DBGFREG_DR0, DBGFREGVALTYPE_U64, 0, 0, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL }, + { "dr1", DBGFREG_DR1, DBGFREGVALTYPE_U64, 0, 1, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL }, + { "dr2", DBGFREG_DR2, DBGFREGVALTYPE_U64, 0, 2, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL }, + { "dr3", DBGFREG_DR3, DBGFREGVALTYPE_U64, 0, 3, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL }, + { "dr6", DBGFREG_DR6, DBGFREGVALTYPE_U32, 0, 6, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, g_aCpumRegFields_dr6 }, + { "dr7", DBGFREG_DR7, DBGFREGVALTYPE_U32, 0, 7, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, g_aCpumRegFields_dr7 }, + { "apic_base", DBGFREG_MSR_IA32_APICBASE, DBGFREGVALTYPE_U32, 0, MSR_IA32_APICBASE, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, g_aCpumRegFields_apic_base }, + { "pat", DBGFREG_MSR_IA32_CR_PAT, DBGFREGVALTYPE_U64, 0, MSR_IA32_CR_PAT, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, g_aCpumRegFields_cr_pat }, + { "perf_status", DBGFREG_MSR_IA32_PERF_STATUS, DBGFREGVALTYPE_U64, 0, MSR_IA32_PERF_STATUS, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, g_aCpumRegFields_perf_status }, + { "sysenter_cs", DBGFREG_MSR_IA32_SYSENTER_CS, DBGFREGVALTYPE_U16, 0, MSR_IA32_SYSENTER_CS, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, NULL }, + { "sysenter_eip", DBGFREG_MSR_IA32_SYSENTER_EIP, DBGFREGVALTYPE_U32, 0, MSR_IA32_SYSENTER_EIP, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, NULL }, + { "sysenter_esp", DBGFREG_MSR_IA32_SYSENTER_ESP, DBGFREGVALTYPE_U32, 0, MSR_IA32_SYSENTER_ESP, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, NULL }, + { "tsc", DBGFREG_MSR_IA32_TSC, DBGFREGVALTYPE_U32, 0, MSR_IA32_TSC, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, NULL }, + { "efer", DBGFREG_MSR_K6_EFER, DBGFREGVALTYPE_U32, 0, MSR_K6_EFER, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, g_aCpumRegFields_efer }, + { "star", DBGFREG_MSR_K6_STAR, DBGFREGVALTYPE_U64, 0, MSR_K6_STAR, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, g_aCpumRegFields_star }, + { "cstar", DBGFREG_MSR_K8_CSTAR, DBGFREGVALTYPE_U64, 0, MSR_K8_CSTAR, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, g_aCpumRegFields_cstar }, + { "msr_fs_base", DBGFREG_MSR_K8_FS_BASE, DBGFREGVALTYPE_U64, 0, MSR_K8_FS_BASE, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, NULL }, + { "msr_gs_base", DBGFREG_MSR_K8_GS_BASE, DBGFREGVALTYPE_U64, 0, MSR_K8_GS_BASE, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, NULL }, + { "krnl_gs_base", DBGFREG_MSR_K8_KERNEL_GS_BASE, DBGFREGVALTYPE_U64, 0, MSR_K8_KERNEL_GS_BASE, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, NULL }, + { "lstar", DBGFREG_MSR_K8_LSTAR, DBGFREGVALTYPE_U64, 0, MSR_K8_LSTAR, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, g_aCpumRegFields_lstar }, + { "tsc_aux", DBGFREG_MSR_K8_TSC_AUX, DBGFREGVALTYPE_U64, 0, MSR_K8_TSC_AUX, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, NULL }, + { "ah", DBGFREG_AH, DBGFREGVALTYPE_U8, 0, RT_OFFSETOF(CPUMCTX, rax) + 1, NULL, NULL, NULL, NULL }, + { "ch", DBGFREG_CH, DBGFREGVALTYPE_U8, 0, RT_OFFSETOF(CPUMCTX, rcx) + 1, NULL, NULL, NULL, NULL }, + { "dh", DBGFREG_DH, DBGFREGVALTYPE_U8, 0, RT_OFFSETOF(CPUMCTX, rdx) + 1, NULL, NULL, NULL, NULL }, + { "bh", DBGFREG_BH, DBGFREGVALTYPE_U8, 0, RT_OFFSETOF(CPUMCTX, rbx) + 1, NULL, NULL, NULL, NULL }, + { "gdtr", DBGFREG_GDTR, DBGFREGVALTYPE_DTR, 0, ~(size_t)0, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL }, + { "idtr", DBGFREG_IDTR, DBGFREGVALTYPE_DTR, 0, ~(size_t)0, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL }, +#undef CPUMREGDESC_REG +#undef CPUMREGDESC_SEG +#undef CPUMREGDESC_ST +#undef CPUMREGDESC_MM +#undef CPUMREGDESC_XMM +}; + +#endif Index: /trunk/src/VBox/VMM/VMMR3/DBGFReg.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR3/DBGFReg.cpp (revision 35467) +++ /trunk/src/VBox/VMM/VMMR3/DBGFReg.cpp (revision 35468) @@ -5,5 +5,5 @@ /* - * Copyright (C) 2010 Oracle Corporation + * Copyright (C) 2010-2011 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as