Index: /trunk/src/VBox/Devices/Network/DevE1000.cpp
===================================================================
--- /trunk/src/VBox/Devices/Network/DevE1000.cpp	(revision 32862)
+++ /trunk/src/VBox/Devices/Network/DevE1000.cpp	(revision 32863)
@@ -43,4 +43,5 @@
 //#define E1K_REL_STATS
 //#define E1K_USE_SUPLIB_SEMEVENT
+//#define E1K_WITH_MSI
 
 #include <iprt/crc.h>
@@ -145,5 +146,12 @@
 {
     /* Vendor Device SSVendor SubSys  Name */
-    { 0x8086, 0x100E, 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
+    { 0x8086,
+      /* Temporary code, as MSI-aware driver dislike 0x100E. How to do that right? */
+#ifdef E1K_WITH_MSI
+      0x105E,
+#else
+      0x100E,
+#endif
+                      0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
     { 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC   in Intel PRO/1000 T  Server */
     { 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" }  /* Intel 82545EM-A in VMWare Network Adapter */
@@ -5589,10 +5597,14 @@
     /* Capability ID: PCI-X Configuration Registers */
     e1kPCICfgSetU8( pci, 0xE4,                           VBOX_PCI_CAP_ID_PCIX);
+#ifdef E1K_WITH_MSI
+    e1kPCICfgSetU8( pci, 0xE4 + 1,                      0x80);
+#else
     /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
     e1kPCICfgSetU8( pci, 0xE4 + 1,                      0x00);
+#endif
     /* PCI-X Command: Enable Relaxed Ordering */
     e1kPCICfgSetU16(pci, 0xE4 + 2,                    VBOX_PCI_X_CMD_ERO);
     /* PCI-X Status: 32-bit, 66MHz*/
-    /// @todo: is this value really correct? fff8 doesn't look like actual PCI address 
+    /// @todo: is this value really correct? fff8 doesn't look like actual PCI address
     e1kPCICfgSetU32(pci, 0xE4 + 4,                0x0040FFF8);
 }
@@ -5730,4 +5742,17 @@
     if (RT_FAILURE(rc))
         return rc;
+
+#ifdef E1K_WITH_MSI
+    PDMMSIREG aMsiReg;
+    aMsiReg.cVectors = 1;
+    aMsiReg.iCapOffset = 0x80;
+    aMsiReg.iNextOffset = 0x0;
+    aMsiReg.iMsiFlags = 0;
+    rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
+    AssertRC(rc);
+    if (RT_FAILURE (rc))
+        return rc;
+#endif
+
 
     /* Map our registers to memory space (region 0, see e1kConfigurePCI)*/
