Index: /trunk/src/VBox/VMM/PGMGstDefs.h =================================================================== --- /trunk/src/VBox/VMM/PGMGstDefs.h (revision 31068) +++ /trunk/src/VBox/VMM/PGMGstDefs.h (revision 31069) @@ -82,5 +82,5 @@ # define PGSTPDE PSHWPDE # define GST_PTE_PG_MASK SHW_PTE_PG_MASK -# define GST_IS_NX_ACTIVE(pVCpu) (CPUMIsGuestNXEnabled(pVCpu)) /** @todo shadow this variable */ +# define GST_IS_NX_ACTIVE(pVCpu) (pgmGstIsNoExecuteActive(pVCpu)) # if PGM_GST_TYPE == PGM_TYPE_PROT /* (comment at top of PGMAllBth.h) */ # define BTH_IS_NP_ACTIVE(pVM) (pVM->pgm.s.fNestedPaging) @@ -127,5 +127,5 @@ //# define GST_IS_BIG_PDPE_VALID(pVCpu, Pdpe) (false) //# define GST_IS_PML4E_VALID(pVCpu, Pml4e) (false) -# define GST_IS_PSE_ACTIVE(pVCpu) (CPUMIsGuestPageSizeExtEnabled(pVCpu)) /** @todo ( (pVCpu)->pgm.s.fGst32BitPageSizeExtension ) */ +# define GST_IS_PSE_ACTIVE(pVCpu) pgmGstIsPageSizeExtActive(pVCpu) # define GST_IS_NX_ACTIVE(pVCpu) (false) # define BTH_IS_NP_ACTIVE(pVM) (false) @@ -186,6 +186,7 @@ # define GST_PT_MASK X86_PT_PAE_MASK # define GST_IS_PSE_ACTIVE(pVCpu) (true) -# define GST_IS_NX_ACTIVE(pVCpu) (CPUMIsGuestNXEnabled(pVCpu)) /** @todo shadow this variable */ +# define GST_IS_NX_ACTIVE(pVCpu) (pgmGstIsNoExecuteActive(pVCpu)) # define BTH_IS_NP_ACTIVE(pVM) (false) #endif + Index: /trunk/src/VBox/VMM/PGMInline.h =================================================================== --- /trunk/src/VBox/VMM/PGMInline.h (revision 31068) +++ /trunk/src/VBox/VMM/PGMInline.h (revision 31069) @@ -553,4 +553,35 @@ #endif /* !IN_RC */ + + +/** + * Checks if the no-execute (NX) feature is active (EFER.NXE=1). + * + * This is inlined so that we can perform consistency checks in debug builds. + * + * @returns true if it is, false if it isn't. + * @param pVCpu The current CPU. + */ +DECL_FORCE_INLINE(bool) pgmGstIsNoExecuteActive(PVMCPU pVCpu) +{ + /** @todo shadow this variable */ + return CPUMIsGuestNXEnabled(pVCpu); +} + + +/** + * Checks if the page size extension (PSE) is currently enabled (CR4.PSE=1). + * + * This is inlined so that we can perform consistency checks in debug builds. + * + * @returns true if it is, false if it isn't. + * @param pVCpu The current CPU. + */ +DECL_FORCE_INLINE(bool) pgmGstIsPageSizeExtActive(PVMCPU pVCpu) +{ + /** @todo ( (pVCpu)->pgm.s.fGst32BitPageSizeExtension ) */ + return CPUMIsGuestPageSizeExtEnabled(pVCpu); +} + /** Index: /trunk/src/VBox/VMM/VMMAll/PGMAllBth.h =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PGMAllBth.h (revision 31068) +++ /trunk/src/VBox/VMM/VMMAll/PGMAllBth.h (revision 31069) @@ -406,8 +406,5 @@ # if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) if ( PdeSrc.b.u1Size -# if PGM_GST_TYPE == PGM_TYPE_32BIT - && CPUMIsGuestPageSizeExtEnabled(pVCpu) -# endif - ) + && GST_IS_PSE_ACTIVE(pVCpu)) GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(pVM, PdeSrc) | ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK)); @@ -1138,10 +1135,5 @@ PdeSrc.u = 0; # endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */ - -# if PGM_GST_TYPE == PGM_TYPE_32BIT - const bool fIsBigPage = PdeSrc.b.u1Size && CPUMIsGuestPageSizeExtEnabled(pVCpu); -# else - const bool fIsBigPage = PdeSrc.b.u1Size; -# endif + const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu); # ifdef IN_RING3 @@ -1761,9 +1753,5 @@ * Check that the page is present and that the shadow PDE isn't out of sync. */ -# if PGM_GST_TYPE == PGM_TYPE_32BIT - const bool fBigPage = PdeSrc.b.u1Size && CPUMIsGuestPageSizeExtEnabled(pVCpu); -# else - const bool fBigPage = PdeSrc.b.u1Size; -# endif + const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu); const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc); RTGCPHYS GCPhys; @@ -1790,5 +1778,5 @@ && (PdeSrc.n.u1Write == PdeDst.n.u1Write || !PdeDst.n.u1Write) # if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE) - && (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute || !CPUMIsGuestNXEnabled(pVCpu)) + && (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute || !GST_IS_NX_ACTIVE(pVCpu)) # endif ) @@ -2261,5 +2249,5 @@ bool fWriteFault = !!(uErr & X86_TRAP_PF_RW); # if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE) - bool fMaybeNXEFault = (uErr & X86_TRAP_PF_ID) && CPUMIsGuestNXEnabled(pVCpu); + bool fMaybeNXEFault = (uErr & X86_TRAP_PF_ID) && GST_IS_NX_ACTIVE(pVCpu); # endif bool fMaybeWriteProtFault = fWriteFault && (fUserLevelFault || CPUMIsGuestR0WriteProtEnabled(pVCpu)); @@ -2337,9 +2325,5 @@ if (!pPdeSrc->n.u1Present) return PGM_BTH_NAME(CheckPageFaultReturnNP)(pVCpu, uErr, GCPtrPage, 2); -# if PGM_GST_TYPE == PGM_TYPE_32BIT - bool const fBigPage = pPdeSrc->b.u1Size && CPUMIsGuestPageSizeExtEnabled(pVCpu); -# else - bool const fBigPage = pPdeSrc->b.u1Size; -# endif + bool const fBigPage = pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu); if (!fBigPage ? !GST_IS_PDE_VALID(pVCpu, *pPdeSrc) : !GST_IS_BIG_PDE_VALID(pVCpu, *pPdeSrc)) return PGM_BTH_NAME(CheckPageFaultReturnRSVD)(pVCpu, uErr, GCPtrPage, 2); @@ -2455,9 +2439,4 @@ PGM_BTH_DECL(int, CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage) { -# if PGM_GST_TYPE == PGM_TYPE_32BIT - const bool fBigPagesSupported = CPUMIsGuestPageSizeExtEnabled(pVCpu); -# else - const bool fBigPagesSupported = true; -# endif PVM pVM = pVCpu->CTX_SUFF(pVM); PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); @@ -2468,5 +2447,5 @@ * Handle big page. */ - if (pPdeSrc->b.u1Size && fBigPagesSupported) + if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu)) { if ( pPdeDst->n.u1Present @@ -2754,9 +2733,5 @@ */ PSHWPT pPTDst; -# if PGM_GST_TYPE == PGM_TYPE_32BIT - const bool fPageTable = !PdeSrc.b.u1Size || !CPUMIsGuestPageSizeExtEnabled(pVCpu); -# else - const bool fPageTable = !PdeSrc.b.u1Size; -# endif + const bool fPageTable = !PdeSrc.b.u1Size || !GST_IS_PSE_ACTIVE(pVCpu); PPGMPOOLPAGE pShwPage; RTGCPHYS GCPhys; @@ -2774,5 +2749,5 @@ PGMPOOLACCESS enmAccess; # if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE) - const bool fNoExecute = PdeSrc.n.u1NoExecute && CPUMIsGuestNXEnabled(pVCpu); + const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu); # else const bool fNoExecute = false; @@ -3779,9 +3754,5 @@ || PGM_GST_TYPE == PGM_TYPE_AMD64 -# if PGM_GST_TYPE == PGM_TYPE_32BIT - bool fBigPagesSupported = CPUMIsGuestPageSizeExtEnabled(pVCpu); -# else - bool fBigPagesSupported = true; -# endif + bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu); PPGMCPU pPGM = &pVCpu->pgm.s; RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */ Index: /trunk/src/VBox/VMM/VMMAll/PGMAllShw.h =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PGMAllShw.h (revision 31068) +++ /trunk/src/VBox/VMM/VMMAll/PGMAllShw.h (revision 31069) @@ -213,5 +213,5 @@ { *pfFlags = (Pde.u & ~SHW_PDE_PG_MASK); -# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) +# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) /** @todo why do we have to check the guest state here? */ if ((Pde.u & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu)) *pfFlags |= X86_PTE_PAE_NX; @@ -266,5 +266,5 @@ *pfFlags = (Pte.u & ~SHW_PTE_PG_MASK) & ((Pde.u & (X86_PTE_RW | X86_PTE_US)) | ~(uint64_t)(X86_PTE_RW | X86_PTE_US)); -# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) +# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) /** @todo why do we have to check the guest state here? */ /* The NX bit is determined by a bitwise OR between the PT and PD */ if (((Pte.u | Pde.u) & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu))