Index: /trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp
===================================================================
--- /trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp	(revision 31034)
+++ /trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp	(revision 31035)
@@ -81,6 +81,6 @@
 #define WAKEEN(pState) (HDA_REG((pState), WAKEEN))
 
-#define ICH6_HDA_REG_STATES 7 /* range 0x0E */
-#define STATES(pState) (HDA_REG((pState), STATES))
+#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
+#define STATESTS(pState) (HDA_REG((pState), STATESTS))
 #define ICH6_HDA_STATES_SCSF 0x7
 
@@ -377,4 +377,6 @@
     /* size in quad words of RIRB buf */
     uint8_t     cdqRirbBuf;
+    /* indicates if HDA in reset. */
+    bool        fInReset;
     CODECState  Codec;
 } INTELHDLinkState;
@@ -792,11 +794,19 @@
         /* exit reset state */
         GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
+        pState->fInReset = false;
     }
     else
     {
         /* enter reset state*/
+        if (   HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) 
+            || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
+        {
+            Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
+                HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
+                HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
+        }
         hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
         GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
-        //** @todo r=michaln: The device isn't supposed to respond to any writes except to this bit now.
+        pState->fInReset = true;
     }
     if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
@@ -1231,4 +1241,8 @@
     uint32_t  u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
     int index = hdaLookup(&pThis->hda, u32Offset);
+    if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
+    {
+        Log(("hda: access to registers except GCTL is blocked while reset\n"));
+    }
     Assert(   index != -1 
            && u32Offset == s_ichIntelHDRegMap[index].offset 
@@ -1275,4 +1289,8 @@
     uint32_t  u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
     int index = hdaLookup(&pThis->hda, u32Offset);
+    if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
+    {
+        Log(("hda: access to registers except GCTL is blocked while reset\n"));
+    }
     Assert(   index != -1 
            && u32Offset == s_ichIntelHDRegMap[index].offset 
@@ -1396,4 +1414,6 @@
     SDFIFOS(&pThis->hda, 7) = 0xBF;
     
+    /* emulateion of codec "wake up" HDA spec (5.5.1 and 6.5)*/
+    STATESTS(&pThis->hda) = 0x1;
 
     Log(("hda: reset finished\n"));
@@ -1515,6 +1535,6 @@
      * hdaReset shouldn't affects these registers.
      */
-    WAKEEN(&pThis->hda) = 0x1;
-    STATES(&pThis->hda) = 0x1;
+    WAKEEN(&pThis->hda) = 0x0;
+    STATESTS(&pThis->hda) = 0x0;
 
     return VINF_SUCCESS;