Index: /trunk/include/VBox/err.mac
===================================================================
--- /trunk/include/VBox/err.mac	(revision 30968)
+++ /trunk/include/VBox/err.mac	(revision 30969)
@@ -162,7 +162,7 @@
 %define VINF_PGM_SHARED_MODULE_COLLISION    (1649)
 %define VERR_PGM_SHARED_MODULE_REGISTRATION_INCONSISTENCY    (-1650)
-%define VERR_PGM_SHARED_MODULE_FIRST_CHECK    (-1651)
 %define VERR_MM_RAM_CONFLICT    (-1700)
 %define VERR_MM_HYPER_NO_MEMORY    (-1701)
+%define VERR_CPUM_RAISE_GP_0    (-1750)
 %define VERR_SSM_UNIT_EXISTS    (-1800)
 %define VERR_SSM_UNIT_NOT_FOUND    (-1801)
Index: /trunk/include/VBox/param.mac
===================================================================
--- /trunk/include/VBox/param.mac	(revision 30968)
+++ /trunk/include/VBox/param.mac	(revision 30969)
@@ -7,7 +7,7 @@
 %define MM_RAM_MIN                  0x00400000
 %if HC_ARCH_BITS == 64
- %define MM_RAM_MAX                 UINT64_C(0x400000000)
+ %define MM_RAM_MAX                 0x400000000
 %else
- %define MM_RAM_MAX                 UINT64_C(0x0E0000000)
+ %define MM_RAM_MAX                 0x0E0000000
 %endif
 %define MM_RAM_MIN_IN_MB            4
Index: /trunk/include/VBox/various.sed
===================================================================
--- /trunk/include/VBox/various.sed	(revision 30968)
+++ /trunk/include/VBox/various.sed	(revision 30969)
@@ -46,4 +46,6 @@
 s/\([[:space:]][0-9][0-9]*\)ULL\([[:space:]]*\))$/\1\2)/
 
+s/UINT64_C([[:space:]]*\(0[xX][0-9a-fA-F][0-9a-fA-F]*\)[[:space:]]*)/\1/
+s/UINT64_C([[:space:]]*\([0-9][0-9]*\)[[:space:]]*)/\1/
 s/UINT32_C([[:space:]]*\(0[xX][0-9a-fA-F][0-9a-fA-F]*\)[[:space:]]*)/\1/
 s/UINT32_C([[:space:]]*\([0-9][0-9]*\)[[:space:]]*)/\1/
Index: /trunk/include/VBox/x86.mac
===================================================================
--- /trunk/include/VBox/x86.mac	(revision 30968)
+++ /trunk/include/VBox/x86.mac	(revision 30969)
@@ -161,5 +161,5 @@
 %define X86_CR3_PAGE_MASK                   (0xfffff000)
 %define X86_CR3_PAE_PAGE_MASK               (0xffffffe0)
-%define X86_CR3_AMD64_PAGE_MASK             UINT64_C(0x000ffffffffff000)
+%define X86_CR3_AMD64_PAGE_MASK             0x000ffffffffff000
 %define X86_CR4_VME                         RT_BIT(0)
 %define X86_CR4_PVI                         RT_BIT(1)
@@ -181,5 +181,5 @@
 %define X86_DR6_BS                          RT_BIT(14)
 %define X86_DR6_BT                          RT_BIT(15)
-%define X86_DR6_INIT_VAL                    UINT64_C(0xFFFF0FF0)
+%define X86_DR6_INIT_VAL                    0xFFFF0FF0
 %define X86_DR7_L0                          RT_BIT(0)
 %define X86_DR7_G0                          RT_BIT(1)
@@ -364,4 +364,8 @@
 %endif
 %define X86_PTE_PAE_NX                      RT_BIT_64(63)
+%define X86_PTE_PAE_MBZ_MASK_NX             0x7ff0000000000000
+%define X86_PTE_PAE_MBZ_MASK_NO_NX          0xfff0000000000000
+%define X86_PTE_LM_MBZ_MASK_NX              0x0000000000000000
+%define X86_PTE_LM_MBZ_MASK_NO_NX           0x8000000000000000
 %define X86_PT_SHIFT                        12
 %define X86_PT_MASK                         0x3ff
@@ -384,4 +388,8 @@
 %endif
 %define X86_PDE_PAE_NX                      RT_BIT_64(63)
+%define X86_PDE_PAE_MBZ_MASK_NX             0x7ff0000000000080
+%define X86_PDE_PAE_MBZ_MASK_NO_NX          0xfff0000000000080
+%define X86_PDE_LM_MBZ_MASK_NX              0x0000000000000080
+%define X86_PDE_LM_MBZ_MASK_NO_NX           0x8000000000000080
 %define X86_PDE4M_P                         RT_BIT(0)
 %define X86_PDE4M_RW                        RT_BIT(1)
@@ -399,6 +407,11 @@
 %define X86_PDE4M_PG_HIGH_MASK              ( 0x001fe000 )
 %define X86_PDE4M_PG_HIGH_SHIFT             19
-%define X86_PDE2M_PAE_PG_MASK               ( 0x000fffffffe00000 )
-%define X86_PDE2M_PAE_NX                    X86_PDE2M_PAE_NX
+%define X86_PDE4M_MBZ_MASK                  RT_BIT_32(21)
+%define X86_PDE2M_PAE_PG_MASK               0x000fffffffe00000
+%define X86_PDE2M_PAE_NX                    RT_BIT_64(63)
+%define X86_PDE2M_PAE_MBZ_MASK_NX           0x7ff00000001fe000
+%define X86_PDE2M_PAE_MBZ_MASK_NO_NX        0xfff00000001fe000
+%define X86_PDE2M_LM_MBZ_MASK_NX            0x00000000001fe000
+%define X86_PDE2M_LM_MBZ_MASK_NO_NX         0x80000000001fe000
 %define X86_PD_SHIFT                        22
 %define X86_PD_MASK                         0x3ff
@@ -411,12 +424,18 @@
 %define X86_PDPE_PCD                        RT_BIT(4)
 %define X86_PDPE_A                          RT_BIT(5)
+%define X86_PDPE_LM_PS                      RT_BIT(7)
 %define X86_PDPE_AVL_MASK                   (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
 %if 1
-%define X86_PDPE_PG_MASK                    ( 0x0000fffffffff000 )
-%define X86_PDPE_PG_MASK_FULL               ( 0x000ffffffffff000 )
-%else
-%define X86_PDPE_PG_MASK                    ( 0x000ffffffffff000 )
-%endif
-%define X86_PDPE_NX                         RT_BIT_64(63)
+%define X86_PDPE_PG_MASK                    0x0000fffffffff000
+%define X86_PDPE_PG_MASK_FULL               0x000ffffffffff000
+%else
+%define X86_PDPE_PG_MASK                    0x000ffffffffff000
+%endif
+%define X86_PDPE_PAE_MBZ_MASK               0xfff00000000001e6
+%define X86_PDPE_LM_NX                      RT_BIT_64(63)
+%define X86_PDPE_LM_MBZ_MASK_NX             0x0000000000000180
+%define X86_PDPE_LM_MBZ_MASK_NO_NX          0x8000000000000180
+%define X86_PDPE1G_LM_MBZ_MASK_NX           0x000000003fffe000
+%define X86_PDPE1G_LM_MBZ_MASK_NO_NX        0x800000003fffe000
 %define X86_PDPT_SHIFT             30
 %define X86_PDPT_MASK_PAE          0x3
@@ -435,4 +454,6 @@
 %define X86_PML4E_PG_MASK                   ( 0x000ffffffffff000 )
 %endif
+%define X86_PML4E_MBZ_MASK_NX               0x0000000000000080
+%define X86_PML4E_MBZ_MASK_NO_NX            0x8000000000000080
 %define X86_PML4E_NX                        RT_BIT_64(63)
 %define X86_PML4_SHIFT              39