Index: /trunk/src/VBox/VMM/HWACCMInternal.h
===================================================================
--- /trunk/src/VBox/VMM/HWACCMInternal.h	(revision 27437)
+++ /trunk/src/VBox/VMM/HWACCMInternal.h	(revision 27438)
@@ -122,8 +122,8 @@
  */
 #ifdef VBOX_STRICT
-#define HWACCM_VMX_TRAP_MASK                RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF)
+#define HWACCM_VMX_TRAP_MASK                RT_BIT(X86_XCPT_BP) | RT_BIT(X86_XCPT_DB) | RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF)
 #define HWACCM_SVM_TRAP_MASK                HWACCM_VMX_TRAP_MASK
 #else
-#define HWACCM_VMX_TRAP_MASK                RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
+#define HWACCM_VMX_TRAP_MASK                RT_BIT(X86_XCPT_DB) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
 #define HWACCM_SVM_TRAP_MASK                RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
 #endif
Index: /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp	(revision 27437)
+++ /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp	(revision 27438)
@@ -1281,13 +1281,4 @@
         pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
     }
-
-#ifdef DEBUG /* till after branching, enable it by default then. */
-    /* Intercept X86_XCPT_DB if stepping is enabled */
-    if (    DBGFIsStepping(pVCpu)
-        ||  CPUMIsHyperDebugStateActive(pVCpu))
-        u32TrapMask |= RT_BIT(X86_XCPT_DB);
-    /** @todo Don't trap it unless the debugger has armed breakpoints.  */
-    u32TrapMask |= RT_BIT(X86_XCPT_BP);
-#endif
 
 #ifdef VBOX_STRICT
@@ -3001,5 +2992,4 @@
 
                 /* Note that we don't support guest and host-initiated debugging at the same time. */
-                Assert(DBGFIsStepping(pVCpu) || CPUMIsGuestInRealModeEx(pCtx) || CPUMIsHyperDebugStateActive(pVCpu));
 
                 uDR6  = X86_DR6_INIT_VAL;
@@ -3389,5 +3379,6 @@
             errCode |= X86_TRAP_PF_P;
         }
-        else {
+        else 
+        {
             /* Shortcut for APIC TPR reads and writes. */
             if (    (GCPhys & 0xfff) == 0x080