Index: /trunk/include/VBox/hwacc_vmx.h =================================================================== --- /trunk/include/VBox/hwacc_vmx.h (revision 23698) +++ /trunk/include/VBox/hwacc_vmx.h (revision 23699) @@ -398,4 +398,20 @@ /** @} */ + +/** @name VT-x capability qword + * @{ + */ +#pragma pack(1) +typedef union +{ + struct + { + uint32_t disallowed0; + uint32_t allowed1; + } n; + uint64_t u; +} VMX_CAPABILITY; +#pragma pack() +/** @} */ /** @name VMX Basic Exit Reasons. Index: /trunk/include/VBox/sup.h =================================================================== --- /trunk/include/VBox/sup.h (revision 23698) +++ /trunk/include/VBox/sup.h (revision 23699) @@ -293,4 +293,11 @@ /** @} */ +/** SUPR3QueryVTCaps capability flags + * @{ + */ +#define SUPVTCAPS_AMD_V RT_BIT(0) +#define SUPVTCAPS_VT_X RT_BIT(1) +#define SUPVTCAPS_NESTED_PAGING RT_BIT(2) +/** @} */ /** @@ -934,4 +941,12 @@ SUPR3DECL(int) SUPR3QueryVTxSupported(void); + +/** + * Return VT-x/AMD-V capabilities + * + * @returns VINF_SUCCESS if supported, error code indicating why if not. + * @param pCaps Pointer to capability dword (out) + */ +SUPR3DECL(int) SUPR3QueryVTCaps(uint32_t *pCaps); /** @} */ @@ -1000,4 +1015,5 @@ SUPR0DECL(int) SUPR0PageFree(PSUPDRVSESSION pSession, RTR3PTR pvR3); SUPR0DECL(int) SUPR0GipMap(PSUPDRVSESSION pSession, PRTR3PTR ppGipR3, PRTHCPHYS pHCPhysGip); +SUPR0DECL(int) SUPR0QueryVTCaps(PSUPDRVSESSION pSession, uint32_t *pCaps); SUPR0DECL(int) SUPR0GipUnmap(PSUPDRVSESSION pSession); SUPR0DECL(int) SUPR0Printf(const char *pszFormat, ...); Index: /trunk/src/VBox/HostDrivers/Support/SUPDrv.c =================================================================== --- /trunk/src/VBox/HostDrivers/Support/SUPDrv.c (revision 23698) +++ /trunk/src/VBox/HostDrivers/Support/SUPDrv.c (revision 23699) @@ -50,4 +50,6 @@ #include #include +#include +#include #if defined(RT_OS_DARWIN) || defined(RT_OS_SOLARIS) || defined(RT_OS_FREEBSD) # include @@ -1736,4 +1738,18 @@ } + case SUP_CTL_CODE_NO_SIZE(SUP_IOCTL_VT_CAPS): + { + /* validate */ + PSUPVTCAPS pReq = (PSUPVTCAPS)pReqHdr; + REQ_CHECK_SIZES(SUP_IOCTL_VT_CAPS); + REQ_CHECK_EXPR(SUP_IOCTL_VT_CAPS, pReq->Hdr.cbIn <= SUP_IOCTL_VT_CAPS_SIZE_IN); + + /* execute */ + pReq->Hdr.rc = SUPR0QueryVTCaps(pSession, &pReq->u.Out.Caps); + if (RT_FAILURE(pReq->Hdr.rc)) + pReq->Hdr.cbOut = sizeof(pReq->Hdr); + return 0; + } + default: Log(("Unknown IOCTL %#lx\n", (long)uIOCtl)); @@ -3660,4 +3676,101 @@ SUPR0ObjRelease(pObj, pSession); return rc; +} + + +SUPR0DECL(int) SUPR0QueryVTCaps(PSUPDRVSESSION pSession, uint32_t *pCaps) +{ + /* + * Input validation. + */ + AssertReturn(SUP_IS_SESSION_VALID(pSession), VERR_INVALID_PARAMETER); + AssertReturn(pCaps, VERR_INVALID_POINTER); + + *pCaps = 0; + + if (ASMHasCpuId()) + { + uint32_t u32FeaturesECX; + uint32_t u32Dummy; + uint32_t u32FeaturesEDX; + uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX, u32AMDFeatureEDX, u32AMDFeatureECX; + uint64_t val; + + ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX); + ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX); + /* Query AMD features. */ + ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &u32AMDFeatureECX, &u32AMDFeatureEDX); + + if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX + && u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX + && u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX + ) + { + if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX) + && (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR) + && (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR) + ) + { + val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL); + /* + * Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP. + * Once the lock bit is set, this MSR can no longer be modified. + */ + if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON|MSR_IA32_FEATURE_CONTROL_LOCK)) + == (MSR_IA32_FEATURE_CONTROL_VMXON|MSR_IA32_FEATURE_CONTROL_LOCK) /* enabled and locked */ + || !(val & MSR_IA32_FEATURE_CONTROL_LOCK) /* not enabled, but not locked either */) + { + VMX_CAPABILITY vtCaps; + + *pCaps |= SUPVTCAPS_VT_X; + + vtCaps.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS); + if (vtCaps.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL) + { + vtCaps.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2); + if (vtCaps.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT) + *pCaps |= SUPVTCAPS_NESTED_PAGING; + } + return VINF_SUCCESS; + } + else + return VERR_VMX_MSR_LOCKED_OR_DISABLED; + } + else + return VERR_VMX_NO_VMX; + } + else + if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX + && u32VendorECX == X86_CPUID_VENDOR_AMD_ECX + && u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX + ) + { + if ( (u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM) + && (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR) + && (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR) + ) + { + /* Check if SVM is disabled */ + val = ASMRdMsr(MSR_K8_VM_CR); + if (!(val & MSR_K8_VM_CR_SVM_DISABLE)) + { + *pCaps |= SUPVTCAPS_AMD_V; + + /* Query AMD features. */ + ASMCpuId(0x8000000A, &u32Dummy, &u32Dummy, &u32Dummy, &u32FeaturesEDX); + + if (u32FeaturesEDX & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING) + *pCaps |= SUPVTCAPS_NESTED_PAGING; + + return VINF_SUCCESS; + } + else + return VERR_SVM_DISABLED; + } + else + return VERR_SVM_NO_SVM; + } + } + return VERR_UNSUPPORTED_CPU; } Index: /trunk/src/VBox/HostDrivers/Support/SUPDrvIOC.h =================================================================== --- /trunk/src/VBox/HostDrivers/Support/SUPDrvIOC.h (revision 23698) +++ /trunk/src/VBox/HostDrivers/Support/SUPDrvIOC.h (revision 23699) @@ -197,5 +197,5 @@ * - Nothing. */ -#define SUPDRV_IOC_VERSION 0x00100000 +#define SUPDRV_IOC_VERSION 0x00100001 /** SUP_IOCTL_COOKIE. */ @@ -1080,4 +1080,26 @@ /** @} */ +/** @name SUP_IOCTL_VT_CAPS Input. + * @{ + */ +/** Free contious memory. */ +#define SUP_IOCTL_VT_CAPS SUP_CTL_CODE_SIZE(26, SUP_IOCTL_VT_CAPS_SIZE) +#define SUP_IOCTL_VT_CAPS_SIZE sizeof(SUPVTCAPS) +#define SUP_IOCTL_VT_CAPS_SIZE_IN sizeof(SUPREQHDR) +#define SUP_IOCTL_VT_CAPS_SIZE_OUT sizeof(SUPVTCAPS) +typedef struct SUPVTCAPS +{ + /** The header. */ + SUPREQHDR Hdr; + union + { + struct + { + /** The VT capability dword. */ + uint32_t Caps; + } Out; + } u; +} SUPVTCAPS, *PSUPVTCAPS; +/** @} */ #pragma pack() /* paranoia */ Index: /trunk/src/VBox/HostDrivers/Support/SUPLib.cpp =================================================================== --- /trunk/src/VBox/HostDrivers/Support/SUPLib.cpp (revision 23698) +++ /trunk/src/VBox/HostDrivers/Support/SUPLib.cpp (revision 23699) @@ -272,6 +272,6 @@ strcpy(CookieReq.u.In.szMagic, SUPCOOKIE_MAGIC); CookieReq.u.In.u32ReqVersion = SUPDRV_IOC_VERSION; - const uint32_t uMinVersion = (SUPDRV_IOC_VERSION & 0xffff0000) == 0x00100000 - ? 0x00100000 + const uint32_t uMinVersion = (SUPDRV_IOC_VERSION & 0xffff0000) == 0x00100001 + ? 0x00100001 : SUPDRV_IOC_VERSION & 0xffff0000; CookieReq.u.In.u32MinVersion = uMinVersion; @@ -2065,2 +2065,34 @@ #endif } + +SUPR3DECL(int) SUPR3QueryVTCaps(uint32_t *pCaps) +{ + AssertPtrReturn(pCaps, VERR_INVALID_POINTER); + + *pCaps = 0; + + /* fake */ + if (RT_UNLIKELY(g_u32FakeMode)) + return VINF_SUCCESS; + + /* + * Issue IOCtl to the SUPDRV kernel module. + */ + SUPVTCAPS Req; + Req.Hdr.u32Cookie = g_u32Cookie; + Req.Hdr.u32SessionCookie = g_u32SessionCookie; + Req.Hdr.cbIn = SUP_IOCTL_VT_CAPS_SIZE_IN; + Req.Hdr.cbOut = SUP_IOCTL_VT_CAPS_SIZE_OUT; + Req.Hdr.fFlags = SUPREQHDR_FLAGS_DEFAULT; + Req.Hdr.rc = VERR_INTERNAL_ERROR; + Req.u.Out.Caps = 0; + int rc = suplibOsIOCtl(&g_supLibData, SUP_IOCTL_VT_CAPS, &Req, SUP_IOCTL_VT_CAPS_SIZE); + if (RT_SUCCESS(rc)) + { + rc = Req.Hdr.rc; + if (RT_SUCCESS(rc) + *pCaps = Req.u.Out.Caps; + } + return rc; +} + Index: /trunk/src/VBox/VMM/HWACCMInternal.h =================================================================== --- /trunk/src/VBox/VMM/HWACCMInternal.h (revision 23698) +++ /trunk/src/VBox/VMM/HWACCMInternal.h (revision 23699) @@ -178,15 +178,4 @@ } HWACCM_CPUINFO; typedef HWACCM_CPUINFO *PHWACCM_CPUINFO; - -/* VT-x capability qword. */ -typedef union -{ - struct - { - uint32_t disallowed0; - uint32_t allowed1; - } n; - uint64_t u; -} VMX_CAPABILITY; typedef enum