Changeset 20838 in vbox

Timestamp:

Jun 23, 2009 2:15:46 PM (15 years ago)

Author:

vboxsync

Message:

NMI updates

Location:

trunk

Files:

• include/VBox/hwaccm.h (modified) (1 diff)
• include/VBox/vm.h (modified) (1 diff)
• src/VBox/VMM/EM.cpp (modified) (1 diff)
• src/VBox/VMM/HWACCM.cpp (modified) (2 diffs)
• src/VBox/VMM/HWACCMInternal.h (modified) (2 diffs)
• src/VBox/VMM/PDM.cpp (modified) (7 diffs)
• src/VBox/VMM/VMMR0/HWSVMR0.cpp (modified) (2 diffs)
• src/VBox/VMM/VMMR0/HWVMXR0.cpp (modified) (2 diffs)

trunk/include/VBox/hwaccm.h

@@ -118 +118 @@
  * @{
  */
-VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM);
+VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu);
 VMMR3DECL(int)  HWACCMR3Init(PVM pVM);
 VMMR3DECL(int)  HWACCMR3InitCPU(PVM pVM);

trunk/include/VBox/vm.h

@@ -302 +302 @@
 #define VMCPU_FF_TIMER                      RT_BIT_32(2)
 /** This action forces the VM to check any pending NMIs. */
-#define VMCPU_FF_INTERRUPT_NMI              RT_BIT_32(3)
+#define VMCPU_FF_INTERRUPT_NMI_BIT          3
+#define VMCPU_FF_INTERRUPT_NMI              RT_BIT_32(VMCPU_FF_INTERRUPT_NMI_BIT)
 /** This action forces the VM to check any pending SMIs. */
-#define VMCPU_FF_INTERRUPT_SMI              RT_BIT_32(4)
+#define VMCPU_FF_INTERRUPT_SMI_BIT          4
+#define VMCPU_FF_INTERRUPT_SMI              RT_BIT_32(VMCPU_FF_INTERRUPT_SMI_BIT)
 /** PDM critical section unlocking is pending, process promptly upon return to R3. */
 #define VMCPU_FF_PDM_CRITSECT               RT_BIT_32(5)

trunk/src/VBox/VMM/EM.cpp

@@ -3515 +3515 @@
             &&  !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
             &&  PATMAreInterruptsEnabled(pVM)
-            &&  !HWACCMR3IsEventPending(pVM))
+            &&  !HWACCMR3IsEventPending(pVCpu))
         {
             Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);

trunk/src/VBox/VMM/HWACCM.cpp

@@ -1628 +1628 @@
  * @param   pVM         The VM to operate on.
  */
-VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
-{
-    /* @todo SMP */
-    return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
-}
-
-
-/**
- * Inject an NMI into a running VM
+VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
+{
+    return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
+}
+
+
+/**
+ * Inject an NMI into a running VM (only VCPU 0!)
  *
  * @returns boolean
@@ -1643 +1642 @@
 VMMR3DECL(int)  HWACCMR3InjectNMI(PVM pVM)
 {
-    pVM->hwaccm.s.fInjectNMI = true;
+    VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
     return VINF_SUCCESS;
 }

trunk/src/VBox/VMM/HWACCMInternal.h

@@ -197 +197 @@
     bool                        fAllowNestedPaging;
 
-    /** Set if we're supposed to inject an NMI. */
-    bool                        fInjectNMI;
-
     /** Set if we can support 64-bit guests or not. */
     bool                        fAllow64BitGuests;
@@ -208 +205 @@
     /** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
      *  naturally. */
-    bool                        padding[1];
+    bool                        padding[2];
 
     /** And mask for copying register contents. */

trunk/src/VBox/VMM/PDM.cpp

@@ -280 +280 @@
 *******************************************************************************/
 /** The PDM saved state version. */
-#define PDM_SAVED_STATE_VERSION     3
+#define PDM_SAVED_STATE_VERSION             4
+#define PDM_SAVED_STATE_VERSION_PRE_NMI_FF  3
 
 
@@ -635 +636 @@
      * Save interrupt and DMA states.
      */
-    for (unsigned idCpu=0;idCpu<pVM->cCPUs;idCpu++)
+    for (unsigned idCpu = 0; idCpu < pVM->cCPUs; idCpu++)
     {
         PVMCPU pVCpu = &pVM->aCpus[idCpu];
         SSMR3PutUInt(pSSM, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC));
         SSMR3PutUInt(pSSM, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_PIC));
+        SSMR3PutUInt(pSSM, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_NMI));
+        SSMR3PutUInt(pSSM, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_SMI));
     }
     SSMR3PutUInt(pSSM, VM_FF_ISSET(pVM, VM_FF_PDM_DMA));
@@ -699 +702 @@
         VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
         VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
+        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
+        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_SMI);
     }
     VM_FF_CLEAR(pVM, VM_FF_PDM_DMA);
@@ -723 +728 @@
      * Validate version.
      */
-    if (u32Version != PDM_SAVED_STATE_VERSION)
+    if (    u32Version != PDM_SAVED_STATE_VERSION
+        &&  u32Version != PDM_SAVED_STATE_VERSION_PRE_NMI_FF)
     {
         AssertMsgFailed(("pdmR3Load: Invalid version u32Version=%d!\n", u32Version));
@@ -732 +738 @@
      * Load the interrupt and DMA states.
      */
-    for (unsigned idCpu=0;idCpu<pVM->cCPUs;idCpu++)
+    for (unsigned idCpu = 0; idCpu < pVM->cCPUs; idCpu++)
     {
         PVMCPU pVCpu = &pVM->aCpus[idCpu];
@@ -763 +769 @@
         if (fInterruptPending)
             VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
+
+        if (u32Version > PDM_SAVED_STATE_VERSION_PRE_NMI_FF)
+        {
+            /* NMI interrupt */
+            RTUINT fInterruptPending = 0;
+            rc = SSMR3GetUInt(pSSM, &fInterruptPending);
+            if (RT_FAILURE(rc))
+                return rc;
+            if (fInterruptPending & ~1)
+            {
+                AssertMsgFailed(("fInterruptPending=%#x (NMI)\n", fInterruptPending));
+                return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
+            }
+            AssertRelease(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_NMI));
+            if (fInterruptPending)
+                VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI);
+
+            /* SMI interrupt */
+            fInterruptPending = 0;
+            rc = SSMR3GetUInt(pSSM, &fInterruptPending);
+            if (RT_FAILURE(rc))
+                return rc;
+            if (fInterruptPending & ~1)
+            {
+                AssertMsgFailed(("fInterruptPending=%#x (SMI)\n", fInterruptPending));
+                return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
+            }
+            AssertRelease(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_SMI));
+            if (fInterruptPending)
+                VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI);
+        }
     }
 
@@ -925 +962 @@
         VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
         VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
+        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
+        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_SMI);
     }
     VM_FF_CLEAR(pVM, VM_FF_PDM_DMA);

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -426 +426 @@
     }
 
-    if (pVM->hwaccm.s.fInjectNMI)
+    if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI_BIT))
     {
         SVM_EVENT Event;
 
+        Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
         Event.n.u8Vector     = X86_XCPT_NMI;
         Event.n.u1Valid      = 1;
@@ -436 +437 @@
 
         SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
-        pVM->hwaccm.s.fInjectNMI = false;
         return VINF_SUCCESS;
     }
+
+    /* @todo SMI interrupts. */
 
     /* When external interrupts are pending, we should exit the VM when IF is set. */

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -754 +754 @@
     }
 
-    if (pVM->hwaccm.s.fInjectNMI)
+    if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI_BIT))
     {
         RTGCUINTPTR intInfo;
+
+        Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
 
         intInfo  = X86_XCPT_NMI;
@@ -765 +767 @@
         AssertRC(rc);
 
-        pVM->hwaccm.s.fInjectNMI = false;
         return VINF_SUCCESS;
     }
+
+    /* @todo SMI interrupts. */
 
     /* When external interrupts are pending, we should exit the VM when IF is set. */