Index: /trunk/src/VBox/VMM/PGMBth.h
===================================================================
--- /trunk/src/VBox/VMM/PGMBth.h	(revision 20128)
+++ /trunk/src/VBox/VMM/PGMBth.h	(revision 20129)
@@ -167,5 +167,5 @@
 
     /* contruct a fake address. */
-    GCPhysCR3 = PGMPOOL_PHYS_NON_PAGED;
+    GCPhysCR3 = RT_BIT_64(63);
     pVCpu->pgm.s.iShwUser      = SHW_POOL_ROOT_IDX;
     pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
Index: /trunk/src/VBox/VMM/PGMInternal.h
===================================================================
--- /trunk/src/VBox/VMM/PGMInternal.h	(revision 20128)
+++ /trunk/src/VBox/VMM/PGMInternal.h	(revision 20129)
@@ -186,13 +186,4 @@
 #endif
 
-/** @} */
-
-/** @name PGM pool physical address flags
- *
- * These are bit markers for PGM pool physical addresses.
- * @{ */
-#define PGMPOOL_PHYS_NON_PAGED          RT_BIT_64(63)
-#define PGMPOOL_PHYS_ACCESS_USER        RT_BIT_64(62)       /* set = user, cleared = supervisor */
-#define PGMPOOL_PHYS_ACCESS_RW          RT_BIT_64(61)       /* set = read/write, cleared = read-only. */
 /** @} */
 
Index: /trunk/src/VBox/VMM/PGMPhys.cpp
===================================================================
--- /trunk/src/VBox/VMM/PGMPhys.cpp	(revision 20128)
+++ /trunk/src/VBox/VMM/PGMPhys.cpp	(revision 20129)
@@ -3233,6 +3233,6 @@
             else
             {
-                /* Temporarily disabled physical handler(s), since the recompiler
-                   doesn't get notified when it's reset we'll have to pretend it's
+                /* Temporariliy disabled phycial handler(s), since the recompiler
+                   doesn't get notified when it's reset we'll have to pretend its
                    operating normally. */
                 if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
@@ -3266,5 +3266,5 @@
             *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
             /** @todo mapping/locking hell; this isn't horribly efficient since
-             *        pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
+             *        pgmPhysPageLoadIntoTlb will repeate the lookup we've done here. */
 
             Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] *ppv=%p\n", GCPhys, rc, pPage, *ppv));
Index: /trunk/src/VBox/VMM/PGMShw.h
===================================================================
--- /trunk/src/VBox/VMM/PGMShw.h	(revision 20128)
+++ /trunk/src/VBox/VMM/PGMShw.h	(revision 20129)
@@ -180,5 +180,5 @@
 {
 #if PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
-    RTGCPHYS     GCPhysCR3 = PGMPOOL_PHYS_NON_PAGED;
+    RTGCPHYS     GCPhysCR3 = RT_BIT_64(63);
     PPGMPOOLPAGE pNewShwPageCR3;
     PVM          pVM       = pVCpu->pVMR3;
Index: /trunk/src/VBox/VMM/VMMAll/PGMAllBth.h
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/PGMAllBth.h	(revision 20128)
+++ /trunk/src/VBox/VMM/VMMAll/PGMAllBth.h	(revision 20129)
@@ -1188,5 +1188,4 @@
     if (PdeSrc.n.u1Present)
     {
-# ifndef PGM_WITHOUT_MAPPING
         if (PdeDst.u & PGM_PDFLAGS_MAPPING)
         {
@@ -1200,7 +1199,5 @@
             pgmUnlock(pVM);
         }
-        else 
-# endif /* !PGM_WITHOUT_MAPPING */
-             if (   PdeSrc.n.u1User != PdeDst.n.u1User
+        else if (   PdeSrc.n.u1User != PdeDst.n.u1User
                  || (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
         {
@@ -2597,14 +2594,5 @@
             GCPhys |= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
 # endif
-            /* Modify the physical address to distinguish between different access types to prevent incorrect reuse of cached entries. */
-            if (PdeSrc.n.u1Write)
-                GCPhys |= PGMPOOL_PHYS_ACCESS_RW;
-            if (PdeSrc.n.u1User)
-                GCPhys |= PGMPOOL_PHYS_ACCESS_USER;
-
             rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx,      iPDDst, &pShwPage);
-
-            /* Strip the flags again in case we have to construct it. */
-            GCPhys &= ~(PGMPOOL_PHYS_ACCESS_RW|PGMPOOL_PHYS_ACCESS_USER);
         }
         if (rc == VINF_SUCCESS)
@@ -3343,4 +3331,48 @@
 #endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
 }
+
+
+#if PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64
+# if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_AMD64
+/**
+ * Figures out which kind of shadow page this guest PDE warrants.
+ *
+ * @returns Shadow page kind.
+ * @param   pPdeSrc     The guest PDE in question.
+ * @param   cr4         The current guest cr4 value.
+ */
+DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
+{
+#  if PMG_GST_TYPE == PGM_TYPE_AMD64
+    if (!pPdeSrc->n.u1Size)
+#  else
+    if (!pPdeSrc->n.u1Size || !(cr4 & X86_CR4_PSE))
+#  endif
+        return BTH_PGMPOOLKIND_PT_FOR_PT;
+    //switch (pPdeSrc->u & (X86_PDE4M_RW | X86_PDE4M_US /*| X86_PDE4M_PAE_NX*/))
+    //{
+    //    case 0:
+    //      return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
+    //    case X86_PDE4M_RW:
+    //      return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
+    //    case X86_PDE4M_US:
+    //      return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
+    //    case X86_PDE4M_RW | X86_PDE4M_US:
+    //      return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
+#  if 0
+    //    case X86_PDE4M_PAE_NX:
+    //      return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
+    //    case X86_PDE4M_RW | X86_PDE4M_PAE_NX:
+    //      return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
+    //    case X86_PDE4M_US | X86_PDE4M_PAE_NX:
+    //      return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
+    //    case X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PAE_NX:
+    //      return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
+#  endif
+            return BTH_PGMPOOLKIND_PT_FOR_BIG;
+    //}
+}
+# endif
+#endif
 
 #undef MY_STAM_COUNTER_INC