Index: /trunk/src/VBox/VMM/CPUM.cpp
===================================================================
--- /trunk/src/VBox/VMM/CPUM.cpp	(revision 20031)
+++ /trunk/src/VBox/VMM/CPUM.cpp	(revision 20032)
@@ -370,5 +370,5 @@
                                        //| X86_CPUID_AMD_FEATURE_ECX_SVM    - not virtualized.
                                        //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
-                                       //| X86_CPUID_AMD_FEATURE_ECX_CR8L
+                                       | X86_CPUID_AMD_FEATURE_ECX_CR8L         /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
                                        //| X86_CPUID_AMD_FEATURE_ECX_ABM
                                        //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
Index: /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp	(revision 20031)
+++ /trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp	(revision 20032)
@@ -939,8 +939,7 @@
     }
 
-    /* TPR caching using CR8 is only available in 64 bits mode */
-    /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
+    /* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
     /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! */
-    if (CPUMIsGuestInLongModeEx(pCtx))
+    if (pVM->hwaccm.s.fHasIoApic)
     {
         bool fPending;