Changeset 19870 in vbox

Timestamp:

May 20, 2009 2:31:01 PM (15 years ago)

Author:

vboxsync

Message:

Save current EMT state to the saved state. Important for restoring VCPUs, that are in the wait for sipi state.

Location:

trunk/src/VBox/VMM

Files:

• EM.cpp (modified) (4 diffs)
• EMInternal.h (modified) (1 diff)

trunk/src/VBox/VMM/EM.cpp

@@ -519 +519 @@
         int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
         AssertRCReturn(rc, rc);
+
+        Assert(pVCpu->em.s.enmState     == EMSTATE_SUSPENDED);
+        Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
+        rc = SSMR3PutU32(pSSM, pVCpu->em.s.enmPrevState);
+        AssertRCReturn(rc, rc);
     }
     return VINF_SUCCESS;
@@ -539 +544 @@
      * Validate version.
      */
-    if (u32Version != EM_SAVED_STATE_VERSION)
+    if (    u32Version != EM_SAVED_STATE_VERSION
+        &&  u32Version != EM_SAVED_STATE_VERSION_PRE_SMP)
     {
         AssertMsgFailed(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
@@ -556 +562 @@
             pVCpu->em.s.fForceRAW = false;
 
+        if (u32Version > EM_SAVED_STATE_VERSION_PRE_SMP)
+        {
+            EMSTATE     enmState;
+            uint32_t    u32;
+            rc = SSMR3GetU32(pSSM, &u32);
+            AssertRCReturn(rc, rc);
+
+            enmState = (EMSTATE)u32;
+            Assert(enmState != EMSTATE_SUSPENDED);
+            pVCpu->em.s.enmState     = enmState;
+            pVCpu->em.s.enmPrevState = EMSTATE_NONE;
+        }
         Assert(!pVCpu->em.s.pCliStatTree);
     }
@@ -3657 +3675 @@
         rc = VINF_SUCCESS;
 
-        /** @todo doesn't work for the save/restore case */
         if (    pVCpu->em.s.enmState == EMSTATE_SUSPENDED
             &&  (   pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI

trunk/src/VBox/VMM/EMInternal.h

@@ -43 +43 @@
 
 /** The saved state version. */
-#define EM_SAVED_STATE_VERSION                      2
+#define EM_SAVED_STATE_VERSION                          3
+#define EM_SAVED_STATE_VERSION_PRE_SMP                  2
 
 /**