Index: /trunk/src/VBox/VMM/PGMInternal.h
===================================================================
--- /trunk/src/VBox/VMM/PGMInternal.h	(revision 19832)
+++ /trunk/src/VBox/VMM/PGMInternal.h	(revision 19833)
@@ -352,13 +352,13 @@
 #endif
 
-/** @def PGM_INVL_GUEST_TLBS()
+/** @def PGM_INVL_VCPU_TLBS()
  * Invalidates all guest TLBs.
  */
 #ifdef IN_RC
-# define PGM_INVL_GUEST_TLBS(pVCpu)             ASMReloadCR3()
+# define PGM_INVL_VCPU_TLBS(pVCpu)             ASMReloadCR3()
 #elif defined(IN_RING0)
-# define PGM_INVL_GUEST_TLBS(pVCpu)             HWACCMFlushTLB(pVCpu)
+# define PGM_INVL_VCPU_TLBS(pVCpu)             HWACCMFlushTLB(pVCpu)
 #else
-# define PGM_INVL_GUEST_TLBS(pVCpu)             HWACCMFlushTLB(pVCpu)
+# define PGM_INVL_VCPU_TLBS(pVCpu)             HWACCMFlushTLB(pVCpu)
 #endif
 
Index: /trunk/src/VBox/VMM/PGMPhys.cpp
===================================================================
--- /trunk/src/VBox/VMM/PGMPhys.cpp	(revision 19832)
+++ /trunk/src/VBox/VMM/PGMPhys.cpp	(revision 19833)
@@ -2682,5 +2682,5 @@
     pgmUnlock(pVM);
     if (fFlushTLB)
-        PGM_INVL_GUEST_TLBS(VMMGetCpu(pVM));
+        PGM_INVL_VCPU_TLBS(VMMGetCpu(pVM));
 
     return rc;
Index: /trunk/src/VBox/VMM/VMMAll/PGMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/PGMAll.cpp	(revision 19832)
+++ /trunk/src/VBox/VMM/VMMAll/PGMAll.cpp	(revision 19833)
@@ -1867,5 +1867,5 @@
      */
     if (rc == VINF_SUCCESS)
-        PGM_INVL_GUEST_TLBS(pVCpu);
+        PGM_INVL_VCPU_TLBS(pVCpu);
     return rc;
 }
@@ -1924,5 +1924,5 @@
 
     /* Flush the TLB */
-    PGM_INVL_GUEST_TLBS(pVCpu);
+    PGM_INVL_VCPU_TLBS(pVCpu);
 
 #ifdef IN_RING3
Index: /trunk/src/VBox/VMM/VMMAll/PGMAllBth.h
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/PGMAllBth.h	(revision 19832)
+++ /trunk/src/VBox/VMM/VMMAll/PGMAllBth.h	(revision 19833)
@@ -989,5 +989,5 @@
         STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
         if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
-            PGM_INVL_GUEST_TLBS(pVCpu);
+            PGM_INVL_VCPU_TLBS(pVCpu);
         return VINF_SUCCESS;
     }
@@ -1001,5 +1001,5 @@
         STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
         if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
-            PGM_INVL_GUEST_TLBS(pVCpu);
+            PGM_INVL_VCPU_TLBS(pVCpu);
         return VINF_SUCCESS;
     }
@@ -1092,5 +1092,5 @@
         ASMAtomicWriteSize(pPml4eDst, 0);
         STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
-        PGM_INVL_GUEST_TLBS(pVCpu);
+        PGM_INVL_VCPU_TLBS(pVCpu);
         return VINF_SUCCESS;
     }
@@ -1106,5 +1106,5 @@
         ASMAtomicWriteSize(pPml4eDst, 0);
         STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
-        PGM_INVL_GUEST_TLBS(pVCpu);
+        PGM_INVL_VCPU_TLBS(pVCpu);
     }
     else if (!pPml4eSrc->n.u1Accessed)
@@ -1118,5 +1118,5 @@
         ASMAtomicWriteSize(pPml4eDst, 0);
         STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
-        PGM_INVL_GUEST_TLBS(pVCpu);
+        PGM_INVL_VCPU_TLBS(pVCpu);
     }
 
@@ -1132,5 +1132,5 @@
         ASMAtomicWriteSize(pPdpeDst, 0);
         STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
-        PGM_INVL_GUEST_TLBS(pVCpu);
+        PGM_INVL_VCPU_TLBS(pVCpu);
         return VINF_SUCCESS;
     }
@@ -1146,5 +1146,5 @@
         ASMAtomicWriteSize(pPdpeDst, 0);
         STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
-        PGM_INVL_GUEST_TLBS(pVCpu);
+        PGM_INVL_VCPU_TLBS(pVCpu);
     }
     else if (!PdpeSrc.lm.u1Accessed)
@@ -1158,5 +1158,5 @@
         ASMAtomicWriteSize(pPdpeDst, 0);
         STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
-        PGM_INVL_GUEST_TLBS(pVCpu);
+        PGM_INVL_VCPU_TLBS(pVCpu);
     }
 # endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
@@ -1190,5 +1190,5 @@
             ASMAtomicWriteSize(pPdeDst, 0);
             STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
-            PGM_INVL_GUEST_TLBS(pVCpu);
+            PGM_INVL_VCPU_TLBS(pVCpu);
         }
         else if (!PdeSrc.n.u1Accessed)
@@ -1202,5 +1202,5 @@
             ASMAtomicWriteSize(pPdeDst, 0);
             STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
-            PGM_INVL_GUEST_TLBS(pVCpu);
+            PGM_INVL_VCPU_TLBS(pVCpu);
         }
         else if (!fIsBigPage)
@@ -1246,5 +1246,5 @@
                 ASMAtomicWriteSize(pPdeDst, 0);
                 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
-                PGM_INVL_GUEST_TLBS(pVCpu);
+                PGM_INVL_VCPU_TLBS(pVCpu);
             }
         }
@@ -1920,5 +1920,5 @@
     PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
 # endif
-    PGM_INVL_GUEST_TLBS(pVCpu);
+    PGM_INVL_VCPU_TLBS(pVCpu);
     return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
 
Index: /trunk/src/VBox/VMM/VMMAll/PGMAllHandler.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/PGMAllHandler.cpp	(revision 19832)
+++ /trunk/src/VBox/VMM/VMMAll/PGMAllHandler.cpp	(revision 19833)
@@ -237,5 +237,5 @@
     if (fFlushTLBs && rc == VINF_SUCCESS)
     {
-        PGM_INVL_GUEST_TLBS(VMMGetCpu(pVM));
+        PGM_INVL_VCPU_TLBS(VMMGetCpu(pVM));
         Log(("pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs: flushing guest TLBs\n"));
     }
@@ -415,5 +415,5 @@
 # ifdef IN_RC
     if (fFlushTLBs && rc != VINF_PGM_SYNC_CR3)
-        PGM_INVL_GUEST_TLBS(VMMGetCpu0(pVM));
+        PGM_INVL_VCPU_TLBS(VMMGetCpu0(pVM));
 # else
     HWACCMFlushAllTLBs(pVM);
Index: /trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp	(revision 19832)
+++ /trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp	(revision 19833)
@@ -370,5 +370,5 @@
     {
         if (fFlushTLBs)
-            PGM_INVL_GUEST_TLBS(pVCpu);
+            PGM_INVL_VCPU_TLBS(pVCpu);
         Assert(rc2 == VERR_EM_NO_MEMORY);
         return rc2;
@@ -425,5 +425,5 @@
     if (    fFlushTLBs
         &&  rc != VINF_PGM_GCPHYS_ALIASED)
-        PGM_INVL_GUEST_TLBS(pVCpu);
+        PGM_INVL_VCPU_TLBS(pVCpu);
     return rc;
 }
Index: /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp	(revision 19832)
+++ /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp	(revision 19833)
@@ -938,5 +938,5 @@
 
     /* See use in pgmPoolAccessHandlerSimple(). */
-    PGM_INVL_GUEST_TLBS(pVCpu);
+    PGM_INVL_VCPU_TLBS(pVCpu);
 
     LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
@@ -1003,5 +1003,5 @@
 #ifdef IN_RC
     /* See use in pgmPoolAccessHandlerSimple(). */
-    PGM_INVL_GUEST_TLBS(pVCpu);
+    PGM_INVL_VCPU_TLBS(pVCpu);
 #endif
 
@@ -1074,5 +1074,5 @@
      * because we need the stale TLBs in some cases (XP boot). This MUST be fixed properly!
      */
-    PGM_INVL_GUEST_TLBS(pVCpu);
+    PGM_INVL_VCPU_TLBS(pVCpu);
 #endif
 
@@ -1298,5 +1298,5 @@
     int rc = pgmPoolFlushPage(pPool, pPage);
     if (rc == VINF_SUCCESS)
-        PGM_INVL_GUEST_TLBS(VMMGetCpu(pVM)); /* see PT handler. */
+        PGM_INVL_VCPU_TLBS(VMMGetCpu(pVM)); /* see PT handler. */
     return rc;
 }
@@ -1467,5 +1467,5 @@
                     STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
                     pgmPoolFlushPage(pPool, pPage);
-                    PGM_INVL_GUEST_TLBS(VMMGetCpu(pVM)); /* see PT handler. */
+                    PGM_INVL_VCPU_TLBS(VMMGetCpu(pVM)); /* see PT handler. */
                     break;
                 }
@@ -2064,5 +2064,5 @@
     pPool->cPresent = 0;
     pgmUnlock(pVM);
-    PGM_INVL_GUEST_TLBS(VMMGetCpu(pVM));
+    PGM_INVL_VCPU_TLBS(VMMGetCpu(pVM));
     STAM_PROFILE_STOP(&pPool->StatClearAll, c);
     return VINF_SUCCESS;