Index: /trunk/include/VBox/hwaccm.h =================================================================== --- /trunk/include/VBox/hwaccm.h (revision 19807) +++ /trunk/include/VBox/hwaccm.h (revision 19808) @@ -76,15 +76,15 @@ #define HWACCMCanEmulateIoBlockEx(pCtx) (!CPUMIsGuestInPagedProtectedModeEx(pCtx)) -VMMDECL(int) HWACCMInvalidatePage(PVM pVM, RTGCPTR GCVirt); +VMMDECL(int) HWACCMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt); VMMDECL(bool) HWACCMHasPendingIrq(PVM pVM); #ifndef IN_RC -VMMDECL(int) HWACCMFlushTLB(PVM pVM); -VMMDECL(int) HWACCMInvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys); +VMMDECL(int) HWACCMFlushTLB(PVMCPU pVCpu); +VMMDECL(int) HWACCMInvalidatePhysPage(PVMCPU pVCpu, RTGCPHYS GCPhys); VMMDECL(bool) HWACCMIsNestedPagingActive(PVM pVM); VMMDECL(PGMMODE) HWACCMGetShwPagingMode(PVM pVM); #else /* Nop in GC */ -# define HWACCMFlushTLB(pVM) do { } while (0) +# define HWACCMFlushTLB(pVCpu) do { } while (0) # define HWACCMIsNestedPagingActive(pVM) false #endif Index: /trunk/src/VBox/VMM/PGMInternal.h =================================================================== --- /trunk/src/VBox/VMM/PGMInternal.h (revision 19807) +++ /trunk/src/VBox/VMM/PGMInternal.h (revision 19808) @@ -332,9 +332,9 @@ */ #ifdef IN_RC -# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt)) +# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(GCVirt)) #elif defined(IN_RING0) -# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt)) +# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt)) #else -# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt)) +# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt)) #endif @@ -345,9 +345,9 @@ */ #ifdef IN_RC -# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3() +# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3() #elif defined(IN_RING0) -# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM) +# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu) #else -# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM) +# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu) #endif @@ -356,9 +356,9 @@ */ #ifdef IN_RC -# define PGM_INVL_GUEST_TLBS() ASMReloadCR3() +# define PGM_INVL_GUEST_TLBS(pVCpu) ASMReloadCR3() #elif defined(IN_RING0) -# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM) +# define PGM_INVL_GUEST_TLBS(pVCpu) HWACCMFlushTLB(pVCpu) #else -# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM) +# define PGM_INVL_GUEST_TLBS(pVCpu) HWACCMFlushTLB(pVCpu) #endif Index: /trunk/src/VBox/VMM/PGMPhys.cpp =================================================================== --- /trunk/src/VBox/VMM/PGMPhys.cpp (revision 19807) +++ /trunk/src/VBox/VMM/PGMPhys.cpp (revision 19808) @@ -2620,7 +2620,9 @@ * Process the request. */ + pgmLock(pVM); int rc = VINF_SUCCESS; bool fFlushTLB = false; for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3) + { if ( GCPhys <= pRom->GCPhysLast && GCPhysLast >= pRom->GCPhys @@ -2666,5 +2668,10 @@ { int rc = PGMHandlerPhysicalReset(pVM, pRom->GCPhys); - AssertRCReturn(rc, rc); + if (RT_FAILURE(rc)) + { + pgmUnlock(pVM); + AssertRC(rc); + return rc; + } } @@ -2672,7 +2679,9 @@ GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT); } - + } + pgmUnlock(pVM); if (fFlushTLB) - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(VMMGetCpu(pVM)); + return rc; } Index: /trunk/src/VBox/VMM/VMMAll/EMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/EMAll.cpp (revision 19807) +++ /trunk/src/VBox/VMM/VMMAll/EMAll.cpp (revision 19808) @@ -3011,5 +3011,5 @@ /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */ if ((oldval & (MSR_K6_EFER_NXE|MSR_K6_EFER_LME|MSR_K6_EFER_LMA)) != (pCtx->msrEFER & (MSR_K6_EFER_NXE|MSR_K6_EFER_LME|MSR_K6_EFER_LMA))) - HWACCMFlushTLB(pVM); + HWACCMFlushTLB(pVCpu); break; Index: /trunk/src/VBox/VMM/VMMAll/HWACCMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/HWACCMAll.cpp (revision 19807) +++ /trunk/src/VBox/VMM/VMMAll/HWACCMAll.cpp (revision 19808) @@ -48,11 +48,11 @@ * * @returns VBox status code. - * @param pVM The VM to operate on. + * @param pVCpu The VMCPU to operate on. * @param GCVirt Page to invalidate */ -VMMDECL(int) HWACCMInvalidatePage(PVM pVM, RTGCPTR GCVirt) +VMMDECL(int) HWACCMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt) { #ifdef IN_RING0 - PVMCPU pVCpu = VMMGetCpu(pVM); + PVM pVM = pVCpu->CTX_SUFF(pVM); if (pVM->hwaccm.s.vmx.fSupported) return VMXR0InvalidatePage(pVM, pVCpu, GCVirt); @@ -69,10 +69,8 @@ * * @returns VBox status code. - * @param pVM The VM to operate on. + * @param pVCpu The VMCPU to operate on. */ -VMMDECL(int) HWACCMFlushTLB(PVM pVM) +VMMDECL(int) HWACCMFlushTLB(PVMCPU pVCpu) { - PVMCPU pVCpu = VMMGetCpu(pVM); - LogFlow(("HWACCMFlushTLB\n")); @@ -115,14 +113,15 @@ * * @returns VBox status code. - * @param pVM The VM to operate on. + * @param pVCpu The VMCPU to operate on. * @param GCPhys Page to invalidate */ -VMMDECL(int) HWACCMInvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys) +VMMDECL(int) HWACCMInvalidatePhysPage(PVMCPU pVCpu, RTGCPHYS GCPhys) { + PVM pVM = pVCpu->CTX_SUFF(pVM); + if (!HWACCMIsNestedPagingActive(pVM)) return VINF_SUCCESS; #ifdef IN_RING0 - PVMCPU pVCpu = VMMGetCpu(pVM); if (pVM->hwaccm.s.vmx.fSupported) return VMXR0InvalidatePhysPage(pVM, pVCpu, GCPhys); @@ -131,5 +130,5 @@ SVMR0InvalidatePhysPage(pVM, pVCpu, GCPhys); #else - HWACCMFlushTLB(pVM); + HWACCMFlushTLB(pVCpu); #endif return VINF_SUCCESS; Index: /trunk/src/VBox/VMM/VMMAll/PGMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PGMAll.cpp (revision 19807) +++ /trunk/src/VBox/VMM/VMMAll/PGMAll.cpp (revision 19808) @@ -1867,5 +1867,5 @@ */ if (rc == VINF_SUCCESS) - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); return rc; } @@ -1924,5 +1924,5 @@ /* Flush the TLB */ - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); #ifdef IN_RING3 Index: /trunk/src/VBox/VMM/VMMAll/PGMAllBth.h =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PGMAllBth.h (revision 19807) +++ /trunk/src/VBox/VMM/VMMAll/PGMAllBth.h (revision 19808) @@ -989,5 +989,5 @@ STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped)); if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)) - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); return VINF_SUCCESS; } @@ -1001,5 +1001,5 @@ STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped)); if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)) - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); return VINF_SUCCESS; } @@ -1092,5 +1092,5 @@ ASMAtomicWriteSize(pPml4eDst, 0); STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs)); - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); return VINF_SUCCESS; } @@ -1106,5 +1106,5 @@ ASMAtomicWriteSize(pPml4eDst, 0); STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync)); - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); } else if (!pPml4eSrc->n.u1Accessed) @@ -1118,5 +1118,5 @@ ASMAtomicWriteSize(pPml4eDst, 0); STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs)); - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); } @@ -1132,5 +1132,5 @@ ASMAtomicWriteSize(pPdpeDst, 0); STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs)); - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); return VINF_SUCCESS; } @@ -1146,5 +1146,5 @@ ASMAtomicWriteSize(pPdpeDst, 0); STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync)); - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); } else if (!PdpeSrc.lm.u1Accessed) @@ -1158,5 +1158,5 @@ ASMAtomicWriteSize(pPdpeDst, 0); STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs)); - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); } # endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */ @@ -1190,5 +1190,5 @@ ASMAtomicWriteSize(pPdeDst, 0); STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync)); - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); } else if (!PdeSrc.n.u1Accessed) @@ -1202,5 +1202,5 @@ ASMAtomicWriteSize(pPdeDst, 0); STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs)); - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); } else if (!fIsBigPage) @@ -1234,5 +1234,5 @@ # endif STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages)); - PGM_INVL_PG(GCPtrPage); + PGM_INVL_PG(pVCpu, GCPtrPage); } else @@ -1246,5 +1246,5 @@ ASMAtomicWriteSize(pPdeDst, 0); STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync)); - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); } } @@ -1292,5 +1292,5 @@ ASMAtomicWriteSize(pPdeDst, 0); STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages)); - PGM_INVL_BIG_PG(GCPtrPage); + PGM_INVL_BIG_PG(pVCpu, GCPtrPage); } } @@ -1305,5 +1305,5 @@ ASMAtomicWriteSize(pPdeDst, 0); STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs)); - PGM_INVL_PG(GCPtrPage); + PGM_INVL_PG(pVCpu, GCPtrPage); } else @@ -1920,5 +1920,5 @@ PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst); # endif - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); return VINF_PGM_SYNCPAGE_MODIFIED_PDE; @@ -2181,5 +2181,5 @@ pPdeDst->n.u1Accessed = 1; pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY; - PGM_INVL_BIG_PG(GCPtrPage); + PGM_INVL_BIG_PG(pVCpu, GCPtrPage); STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a); return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; @@ -2202,5 +2202,5 @@ /* Stale TLB entry. */ STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale)); - PGM_INVL_PG(GCPtrPage); + PGM_INVL_PG(pVCpu, GCPtrPage); STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a); @@ -2320,5 +2320,5 @@ pPteDst->n.u1Accessed = 1; pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY; - PGM_INVL_PG(GCPtrPage); + PGM_INVL_PG(pVCpu, GCPtrPage); STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a); @@ -2334,5 +2334,5 @@ /* Stale TLB entry. */ STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale)); - PGM_INVL_PG(GCPtrPage); + PGM_INVL_PG(pVCpu, GCPtrPage); STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a); @@ -3389,5 +3389,5 @@ */ /** @todo check if this is really necessary; the call does it as well... */ - HWACCMFlushTLB(pVM); + HWACCMFlushTLB(pVCpu); return VINF_SUCCESS; @@ -4246,5 +4246,5 @@ { # ifdef IN_RC - PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping); + PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping); # endif # if PGM_GST_TYPE == PGM_TYPE_32BIT @@ -4299,5 +4299,5 @@ pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys; # ifdef IN_RC - PGM_INVL_PG(GCPtr); + PGM_INVL_PG(pVCpu, GCPtr); # endif continue; @@ -4313,5 +4313,5 @@ pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS; # ifdef IN_RC - PGM_INVL_PG(GCPtr); /** @todo this shouldn't be necessary? */ + PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */ # endif } Index: /trunk/src/VBox/VMM/VMMAll/PGMAllHandler.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PGMAllHandler.cpp (revision 19807) +++ /trunk/src/VBox/VMM/VMMAll/PGMAllHandler.cpp (revision 19808) @@ -169,5 +169,5 @@ pVM->pgm.s.fPhysCacheFlushPending = true; pgmUnlock(pVM); - HWACCMFlushTLB(pVM); + HWACCMFlushTLB(VMMGetCpu(pVM)); #ifndef IN_RING3 REMNotifyHandlerPhysicalRegister(pVM, enmType, GCPhys, GCPhysLast - GCPhys + 1, !!pfnHandlerR3); @@ -237,5 +237,5 @@ if (fFlushTLBs && rc == VINF_SUCCESS) { - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(VMMGetCpu(pVM)); Log(("pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs: flushing guest TLBs\n")); } @@ -271,5 +271,5 @@ pgmHandlerPhysicalDeregisterNotifyREM(pVM, pCur); pgmUnlock(pVM); - HWACCMFlushTLB(pVM); + HWACCMFlushTLB(VMMGetCpu(pVM)); MMHyperFree(pVM, pCur); return VINF_SUCCESS; @@ -415,7 +415,7 @@ # ifdef IN_RC if (fFlushTLBs && rc != VINF_PGM_SYNC_CR3) - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(VMMGetCpu0(pVM)); # else - HWACCMFlushTLB(pVM); + HWACCMFlushTLB(VMMGetCpu(pVM)); # endif pVM->pgm.s.fPhysCacheFlushPending = true; @@ -553,5 +553,5 @@ #endif pgmUnlock(pVM); - HWACCMFlushTLB(pVM); + HWACCMFlushTLB(VMMGetCpu(pVM)); Log(("PGMHandlerPhysicalModify: GCPhysCurrent=%RGp -> GCPhys=%RGp GCPhysLast=%RGp\n", GCPhysCurrent, GCPhys, GCPhysLast)); @@ -848,5 +848,5 @@ rc = pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs(pVM, pCur, pRam); pVM->pgm.s.fPhysCacheFlushPending = true; - HWACCMFlushTLB(pVM); + HWACCMFlushTLB(VMMGetCpu(pVM)); } @@ -920,5 +920,5 @@ PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, PGM_PAGE_HNDL_PHYS_STATE_DISABLED); #ifndef IN_RC - HWACCMInvalidatePhysPage(pVM, GCPhysPage); + HWACCMInvalidatePhysPage(VMMGetCpu(pVM), GCPhysPage); #endif return VINF_SUCCESS; @@ -1037,5 +1037,5 @@ #ifndef IN_RC - HWACCMInvalidatePhysPage(pVM, GCPhysPage); + HWACCMInvalidatePhysPage(VMMGetCpu(pVM), GCPhysPage); #endif return VINF_SUCCESS; Index: /trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp (revision 19807) +++ /trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp (revision 19808) @@ -189,5 +189,5 @@ /* invalidate tls */ - PGM_INVL_PG((RTGCUINTPTR)pCur->GCPtr + off); + PGM_INVL_PG(VMMGetCpu(pVM), (RTGCUINTPTR)pCur->GCPtr + off); /* next */ Index: /trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp (revision 19807) +++ /trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp (revision 19808) @@ -344,4 +344,5 @@ int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys) { + PVMCPU pVCpu = VMMGetCpu(pVM); LogFlow(("pgmPhysAllocPage: %R[pgmpage] %RGp\n", pPage, GCPhys)); @@ -369,5 +370,5 @@ { if (fFlushTLBs) - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); Assert(rc2 == VERR_EM_NO_MEMORY); return rc2; @@ -424,5 +425,5 @@ if ( fFlushTLBs && rc != VINF_PGM_GCPHYS_ALIASED) - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); return rc; } Index: /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp (revision 19807) +++ /trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp (revision 19808) @@ -938,5 +938,5 @@ /* See use in pgmPoolAccessHandlerSimple(). */ - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc)); @@ -1003,5 +1003,5 @@ #ifdef IN_RC /* See use in pgmPoolAccessHandlerSimple(). */ - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); #endif @@ -1074,5 +1074,5 @@ * because we need the stale TLBs in some cases (XP boot). This MUST be fixed properly! */ - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(pVCpu); #endif @@ -1298,5 +1298,5 @@ int rc = pgmPoolFlushPage(pPool, pPage); if (rc == VINF_SUCCESS) - PGM_INVL_GUEST_TLBS(); /* see PT handler. */ + PGM_INVL_GUEST_TLBS(VMMGetCpu(pVM)); /* see PT handler. */ return rc; } @@ -1467,5 +1467,5 @@ STAM_COUNTER_INC(&pPool->StatCacheKindMismatches); pgmPoolFlushPage(pPool, pPage); - PGM_INVL_GUEST_TLBS(); /* see PT handler. */ + PGM_INVL_GUEST_TLBS(VMMGetCpu(pVM)); /* see PT handler. */ break; } @@ -2064,5 +2064,5 @@ pPool->cPresent = 0; pgmUnlock(pVM); - PGM_INVL_GUEST_TLBS(); + PGM_INVL_GUEST_TLBS(VMMGetCpu(pVM)); STAM_PROFILE_STOP(&pPool->StatClearAll, c); return VINF_SUCCESS; Index: /trunk/src/VBox/VMM/VMMAll/PGMAllShw.h =================================================================== --- /trunk/src/VBox/VMM/VMMAll/PGMAllShw.h (revision 19807) +++ /trunk/src/VBox/VMM/VMMAll/PGMAllShw.h (revision 19808) @@ -359,7 +359,7 @@ Assert(pPT->a[iPTE].n.u1Present); # if PGM_SHW_TYPE == PGM_TYPE_EPT - HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)GCPtr); + HWACCMInvalidatePhysPage(pVCpu, (RTGCPHYS)GCPtr); # else - PGM_INVL_PG(GCPtr); + PGM_INVL_PG(pVCpu, GCPtr); # endif }