Changeset 16172 in vbox

Timestamp:

Jan 22, 2009 3:09:31 PM (16 years ago)

Author:

vboxsync

Message:

Moved amd64 paging data to unified shadow paging section.

Location:

trunk/src/VBox/VMM

Files:

• PGM.cpp (modified) (1 diff)
• PGMInternal.h (modified) (4 diffs)
• PGMShw.h (modified) (2 diffs)
• VMMAll/PGMAll.cpp (modified) (4 diffs)
• VMMAll/PGMAllBth.h (modified) (4 diffs)
• VMMAll/PGMAllGst.h (modified) (3 diffs)
• testcase/tstVMStructGC.cpp (modified) (1 diff)

trunk/src/VBox/VMM/PGM.cpp

@@ -1529 +1529 @@
 #if HC_ARCH_BITS == 64
 # ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
-        LogRel(("Debug: HCPhysShw32BitPD=%RHp aHCPhysPaePDs={%RHp,%RHp,%RHp,%RHp} HCPhysShwPaePdpt=%RHp HCPhysShwPaePml4=%RHp\n",
+        LogRel(("Debug: HCPhysShw32BitPD=%RHp aHCPhysPaePDs={%RHp,%RHp,%RHp,%RHp} HCPhysShwPaePdpt=%RHp\n",
                 pVM->pgm.s.HCPhysShw32BitPD,
                 pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
-                pVM->pgm.s.HCPhysShwPaePdpt,
-                pVM->pgm.s.HCPhysShwPaePml4));
+                pVM->pgm.s.HCPhysShwPaePdpt));
 # endif
         LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",

trunk/src/VBox/VMM/PGMInternal.h

@@ -2227 +2227 @@
     /** @} */
 
-    /** @name 32-bit Shadow Paging
+    /** @name Shadow paging
      * @{ */
-#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
+    /** The root page table - R3 Ptr. */
+    R3PTRTYPE(void *)               pShwRootR3;
+# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
+    /** The root page table - R0 Ptr. */
+    R0PTRTYPE(void *)               pShwRootR0;
+# endif
     /** The Physical Address (HC) of the current active shadow CR3. */
     RTHCPHYS                        HCPhysShwCR3;
@@ -2241 +2246 @@
     RTRCPTR                         alignment6; /**< structure size alignment. */
 # endif
-#else
+    /** @} */
+#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
+    /** @name 32-bit Shadow Paging
+     * @{ */
     /** The 32-Bit PD - R3 Ptr. */
     R3PTRTYPE(PX86PD)               pShw32BitPdR3;
@@ -2284 +2292 @@
     RTRCPTR                         alignment5; /**< structure size alignment. */
 # endif
-
-    /** @name AMD64 Shadow Paging
-     * Extends PAE Paging.
-     * @{ */
-    /** The Page Map Level 4 table - R3 Ptr. */
-    R3PTRTYPE(PX86PML4)             pShwPaePml4R3;
-# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-    /** The Page Map Level 4 table - R0 Ptr. */
-    R0PTRTYPE(PX86PML4)             pShwPaePml4R0;
-# endif
-    /** The Physical Address (HC) of the Page Map Level 4 table. */
-    RTHCPHYS                        HCPhysShwPaePml4;
-    /** The pgm pool page descriptor for the current active CR3 - R3 Ptr. */
-    R3PTRTYPE(PPGMPOOLPAGE)         pShwAmd64CR3R3;
-    /** The pgm pool page descriptor for the current active CR3 - R0 Ptr. */
-    R0PTRTYPE(PPGMPOOLPAGE)         pShwAmd64CR3R0;
-    /** @}*/
 
     /** @name Nested Shadow Paging
@@ -4309 +4300 @@
     return pShwPml4;
 # else
-    Assert(pPGM->CTX_SUFF(pShwPaePml4));
-    return pPGM->CTX_SUFF(pShwPaePml4);
+    Assert(pPGM->CTX_SUFF(pShwRoot));
+    return (PX86PML4)pPGM->CTX_SUFF(pShwRoot);
 # endif
 #endif

trunk/src/VBox/VMM/PGMShw.h

@@ -143 +143 @@
     Log(("Enter nested shadow paging mode: root %RHv phys %RHp\n", pVM->pgm.s.pShwNestedRootR3, pVM->pgm.s.HCPhysShwNestedRoot));
     /* In non-nested mode we allocate the PML4 page on-demand; in nested mode we just use our fixed nested paging root. */
-    pVM->pgm.s.pShwPaePml4R3 = (R3PTRTYPE(PX86PML4))pVM->pgm.s.pShwNestedRootR3;
+    pVM->pgm.s.pShwRootR3 = (R3PTRTYPE(void *))pVM->pgm.s.pShwNestedRootR3;
 # ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-    pVM->pgm.s.pShwPaePml4R0 = (R0PTRTYPE(PX86PML4))pVM->pgm.s.pShwNestedRootR0;
+    pVM->pgm.s.pShwRootR0 = (R0PTRTYPE(void *))pVM->pgm.s.pShwNestedRootR0;
 # endif
-    pVM->pgm.s.HCPhysShwPaePml4 = pVM->pgm.s.HCPhysShwNestedRoot;
+    pVM->pgm.s.HCPhysShwCR3 = pVM->pgm.s.HCPhysShwNestedRoot;
 #endif
     return VINF_SUCCESS;
@@ -177 +177 @@
 #if PGM_SHW_TYPE == PGM_TYPE_NESTED
     Assert(HWACCMIsNestedPagingActive(pVM));
-    pVM->pgm.s.pShwPaePml4R3 = 0;
+    pVM->pgm.s.pShwRootR3 = 0;
 # ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-    pVM->pgm.s.pShwPaePml4R0 = 0;
+    pVM->pgm.s.pShwRootR0 = 0;
 # endif
-    pVM->pgm.s.HCPhysShwPaePml4 = 0;
+    pVM->pgm.s.HCPhysShwCR3 = 0;
     Log(("Leave nested shadow paging mode\n"));
 #endif

trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

@@ -931 +931 @@
              *        trustworthy? (Remove pgmGstGetLongModePML4E if pGstPml4e and pGstPdpe
              *        are fine.) */
-            Assert(pVM->pgm.s.CTX_SUFF(pShwAmd64CR3));
+            Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
             Pml4eGst = pgmGstGetLongModePML4E(&pVM->pgm.s, iPml4);
 
             rc = pgmPoolAlloc(pVM, Pml4eGst.u & X86_PML4E_PG_MASK,
-                              PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->idx, iPml4, &pShwPage);
+                              PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
         }
         else
@@ -1275 +1275 @@
         case PGMMODE_AMD64:
         case PGMMODE_AMD64_NX:
-            return pVM->pgm.s.HCPhysShwPaePml4;
+            return pVM->pgm.s.HCPhysShwCR3;
 
         case PGMMODE_EPT:
@@ -1308 +1308 @@
         case PGMMODE_AMD64:
         case PGMMODE_AMD64_NX:
-            return pVM->pgm.s.HCPhysShwPaePml4;
+            return pVM->pgm.s.HCPhysShwCR3;
 
         default:
@@ -1357 +1357 @@
 VMMDECL(RTHCPHYS) PGMGetHyperAmd64CR3(PVM pVM)
 {
-    return pVM->pgm.s.HCPhysShwPaePml4;
+    return pVM->pgm.s.HCPhysShwCR3;
 }
 

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -910 +910 @@
 # else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
     /* PML4 */
-    AssertReturn(pVM->pgm.s.pShwPaePml4R3, VERR_INTERNAL_ERROR);
+    AssertReturn(CTX_SUFF(pVM->pgm.s.pShwRoot), VERR_INTERNAL_ERROR);
 
     const unsigned  iPml4     = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
@@ -1021 +1021 @@
         LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
                  GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
-        pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->idx, iPml4);
+        pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
         pPml4eDst->u = 0;
         STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
@@ -1035 +1035 @@
         LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
                  GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
-        pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->idx, iPml4);
+        pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
         pPml4eDst->u = 0;
         STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
@@ -1047 +1047 @@
         LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
                  GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
-        pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->idx, iPml4);
+        pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
         pPml4eDst->u = 0;
         STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));

trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

@@ -517 +517 @@
                 /** @todo Move this into PGMAllBth.h. */
                 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
-                if (pVM->pgm.s.CTX_SUFF(pShwAmd64CR3))
+                if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
                 {
                     /* It might have been freed already by a pool flush (see e.g. PGMR3MappingsUnfix). */
                     /** @todo Coordinate this better with the pool. */
-                    if (pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->enmKind != PGMPOOLKIND_FREE)
-                        pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3), PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->GCPhys >> PAGE_SHIFT);
-                    pVM->pgm.s.pShwAmd64CR3R3   = 0;
-                    pVM->pgm.s.pShwAmd64CR3R0   = 0;
-                    pVM->pgm.s.pShwPaePml4R3    = 0;
+                    if (pVM->pgm.s.CTX_SUFF(pShwPageCR3)->enmKind != PGMPOOLKIND_FREE)
+                        pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->GCPhys >> PAGE_SHIFT);
+                    pVM->pgm.s.pShwPageCR3R3 = 0;
+                    pVM->pgm.s.pShwPageCR3R0 = 0;
+                    pVM->pgm.s.pShwRootR3    = 0;
 #  ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-                    pVM->pgm.s.pShwPaePml4R0    = 0;
+                    pVM->pgm.s.pShwRootR0    = 0;
 #  endif
-                    pVM->pgm.s.HCPhysShwPaePml4 = 0;
+                    pVM->pgm.s.HCPhysShwCR3  = 0;
                 }
 
                 Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
-                rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.CTX_SUFF(pShwAmd64CR3));
+                rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.CTX_SUFF(pShwPageCR3));
                 if (rc == VERR_PGM_POOL_FLUSHED)
                 {
@@ -542 +542 @@
                 AssertRCReturn(rc, rc);
 #  ifdef IN_RING0
-                pVM->pgm.s.pShwAmd64CR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3));
+                pVM->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
 #  else
-                pVM->pgm.s.pShwAmd64CR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3));
+                pVM->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
 #  endif
-                pVM->pgm.s.pShwPaePml4R3 = (R3PTRTYPE(PX86PML4))pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->pvPageR3;
-                Assert(pVM->pgm.s.pShwPaePml4R3);
+                pVM->pgm.s.pShwRootR3    = (R3PTRTYPE(void *))pVM->pgm.s.CTX_SUFF(pShwPageCR3)->pvPageR3;
+                Assert(pVM->pgm.s.pShwRootR3);
 #  ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-                pVM->pgm.s.pShwPaePml4R0 = (R0PTRTYPE(PX86PML4))PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.CTX_SUFF(pShwAmd64CR3));
+                pVM->pgm.s.pShwRootR0    = (R0PTRTYPE(void *))PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.CTX_SUFF(pShwPageCR3));
 #  endif
-                pVM->pgm.s.HCPhysShwPaePml4 = pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->Core.Key;
+                pVM->pgm.s.HCPhysShwCR3  = pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
                 rc = VINF_SUCCESS; /* clear it - pgmPoolAlloc returns hints. */
             }
@@ -611 +611 @@
     if (!HWACCMIsNestedPagingActive(pVM))
     {
-        pVM->pgm.s.pShwPaePml4R3 = 0;
+        pVM->pgm.s.pShwRootR3 = 0;
 # ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-        pVM->pgm.s.pShwPaePml4R0 = 0;
-# endif
-        pVM->pgm.s.HCPhysShwPaePml4 = 0;
-        if (pVM->pgm.s.CTX_SUFF(pShwAmd64CR3))
+        pVM->pgm.s.pShwRootR0 = 0;
+# endif
+        pVM->pgm.s.HCPhysShwCR3 = 0;
+        if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
         {
             PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
-            pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3), PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->GCPhys >> PAGE_SHIFT);
-            pVM->pgm.s.pShwAmd64CR3R3 = 0;
-            pVM->pgm.s.pShwAmd64CR3R0 = 0;
+            pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->GCPhys >> PAGE_SHIFT);
+            pVM->pgm.s.pShwPageCR3R3 = 0;
+            pVM->pgm.s.pShwPageCR3R0 = 0;
         }
     }

trunk/src/VBox/VMM/testcase/tstVMStructGC.cpp

@@ -447 +447 @@
     GEN_CHECK_OFF(PGM, pShwPaePdptRC);
     GEN_CHECK_OFF(PGM, HCPhysShwPaePdpt);
-    GEN_CHECK_OFF(PGM, pShwPaePml4R3);
+    GEN_CHECK_OFF(PGM, pShwRootR3);
 #ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
-    GEN_CHECK_OFF(PGM, pShwPaePml4R0);
-#endif
-    GEN_CHECK_OFF(PGM, HCPhysShwPaePml4);
+    GEN_CHECK_OFF(PGM, pShwRootR0);
+#endif
+    GEN_CHECK_OFF(PGM, HCPhysShwCR3);
+    GEN_CHECK_OFF(PGM, pShwPageCR3R3);
+    GEN_CHECK_OFF(PGM, pShwPageCR3R0);
+    GEN_CHECK_OFF(PGM, pShwPageCR3RC);
     GEN_CHECK_OFF(PGM, pfnR3ShwRelocate);
     GEN_CHECK_OFF(PGM, pfnR3ShwExit);