Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
===================================================================
--- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 105925)
+++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 105926)
@@ -8287,4 +8287,58 @@
              /*256:out  */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO,
              /*xcpt?    */ false, false },
+    /*
+     * Infinity.
+     */
+    /* 9*/{ { /*src2     */ { FP32_INF(0),  FP32_INF(0), FP32_INF(0), FP32_INF(0),  FP32_INF(1), FP32_INF(1),  FP32_INF(1),  FP32_INF(1) } },
+            { /*src1     */ { FP32_INF(0),  FP32_INF(0), FP32_INF(1), FP32_INF(1),  FP32_INF(0), FP32_INF(0),  FP32_INF(1),  FP32_INF(1) } },
+            { /* =>      */ { FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } },
+              /*mxcsr:in */ X86_MXCSR_IM,
+              /*128:out  */ X86_MXCSR_IM | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IM | X86_MXCSR_IE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_INF(0),  FP32_INF(0), FP32_INF(0), FP32_INF(0),  FP32_INF(1), FP32_INF(1),  FP32_INF(1),  FP32_INF(1) } },
+            { /*src1     */ { FP32_INF(0),  FP32_INF(0), FP32_INF(1), FP32_INF(1),  FP32_INF(0), FP32_INF(0),  FP32_INF(1),  FP32_INF(1) } },
+            { /* =>      */ { FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO | X86_MXCSR_IE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_INF(0),  FP32_INF(0), FP32_INF(0), FP32_INF(0),  FP32_INF(1), FP32_INF(1),  FP32_INF(1),  FP32_INF(1) } },
+            { /*src1     */ { FP32_INF(0),  FP32_INF(0), FP32_INF(1), FP32_INF(1),  FP32_INF(0), FP32_INF(0),  FP32_INF(1),  FP32_INF(1) } },
+            { /* =>      */ { FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN | X86_MXCSR_IE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_INF(0),  FP32_INF(0), FP32_INF(0), FP32_INF(0),  FP32_INF(1), FP32_INF(1),  FP32_INF(1),  FP32_INF(1) } },
+            { /*src1     */ { FP32_INF(0),  FP32_INF(0), FP32_INF(1), FP32_INF(1),  FP32_INF(0), FP32_INF(0),  FP32_INF(1),  FP32_INF(1) } },
+            { /* =>      */ { FP32_QNAN(1), FP32_INF(0), FP32_INF(1), FP32_QNAN(1), FP32_INF(0), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_INF(1),  FP32_INF(1),  FP32_INF(1) } },
+            { /*src1     */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_INF(0),  FP32_INF(1),  FP32_INF(1) } },
+            { /* =>      */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_QNAN(1), FP32_QNAN(1), FP32_INF(1) } },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
+              /*xcpt?    */ false, true },
+          { { /*src2     */ { FP32_INF(0), FP32_0(0),   FP32_0(0),   FP32_INF(0), FP32_0(1),   FP32_0(1),   FP32_INF(1), FP32_INF(1) } },
+            { /*src1     */ { FP32_0(0),   FP32_INF(0), FP32_INF(1), FP32_0(1),   FP32_INF(0), FP32_INF(0), FP32_0(1),   FP32_0(1)   } },
+            { /* =>      */ { FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP32_INF(0),     FP32_NORM_V1(0), FP32_NORM_V2(0), FP32_INF(0),     FP32_NORM_V3(1), FP32_NORM_V2(1), FP32_INF(1),     FP32_INF(1)     } },
+            { /*src1     */ { FP32_NORM_V0(0), FP32_INF(0),     FP32_INF(1),     FP32_NORM_V3(1), FP32_INF(0),     FP32_INF(0),     FP32_NORM_V1(1), FP32_NORM_V0(1) } },
+            { /* =>      */ { FP32_INF(1),     FP32_INF(0),     FP32_INF(1),     FP32_INF(0),     FP32_INF(0),     FP32_INF(0),     FP32_INF(0),     FP32_INF(1)     } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+    /** @todo More infinity; Denormals; Overflow/Precision; Normals; Invalids;
+     *        Rounding; FZ etc. */
     };