Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac =================================================================== --- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac (revision 105924) +++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac (revision 105925) @@ -408,4 +408,22 @@ EMIT_INSTR_PLUS_ICEBP_C64 vmulsd, XMM8, XMM9, FSxBX +; +;; [v]addsubpd +; +EMIT_INSTR_PLUS_ICEBP addsubps, XMM1, XMM2 +EMIT_INSTR_PLUS_ICEBP addsubps, XMM1, FSxBX +EMIT_INSTR_PLUS_ICEBP_C64 addsubps, XMM8, XMM9 +EMIT_INSTR_PLUS_ICEBP_C64 addsubps, XMM8, FSxBX + +EMIT_INSTR_PLUS_ICEBP vaddsubps, XMM1, XMM2, XMM3 +EMIT_INSTR_PLUS_ICEBP vaddsubps, XMM1, XMM2, FSxBX +EMIT_INSTR_PLUS_ICEBP_C64 vaddsubps, XMM8, XMM9, XMM10 +EMIT_INSTR_PLUS_ICEBP_C64 vaddsubps, XMM8, XMM9, FSxBX + +EMIT_INSTR_PLUS_ICEBP vaddsubps, YMM1, YMM2, YMM3 +EMIT_INSTR_PLUS_ICEBP vaddsubps, YMM1, YMM2, FSxBX +EMIT_INSTR_PLUS_ICEBP_C64 vaddsubps, YMM13, YMM14, YMM15 +EMIT_INSTR_PLUS_ICEBP_C64 vaddsubps, YMM13, YMM14, FSxBX + %endif ; BS3_INSTANTIATING_CMN Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 =================================================================== --- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (revision 105924) +++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (revision 105925) @@ -8214,4 +8214,128 @@ +/* + * [V]ADDSUBPS. + */ +BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_addsubps(uint8_t bMode) +{ + static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] = + { + /* + * Zero. + */ + /* 0*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, + { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, + { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, + /*mxcsr:in */ 0, + /*128:out */ 0, + /*256:out */ 0, + /*xcpt? */ false, false }, + { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, + { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, + { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, + /*mxcsr:in */ 0, + /*128:out */ 0, + /*256:out */ 0, + /*xcpt? */ false, false }, + { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, + { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, + { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, + /*mxcsr:in */ X86_MXCSR_RC_ZERO, + /*128:out */ X86_MXCSR_RC_ZERO, + /*256:out */ X86_MXCSR_RC_ZERO, + /*xcpt? */ false, false }, + { { /*src2 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, + { /*src1 */ { FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, + { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, + /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, + /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, + /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, + /*xcpt? */ false, false }, + { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, + { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, + { /* => */ { FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1) } }, + /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, + /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, + /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, + /*xcpt? */ false, false }, + { { /*src2 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, + { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, + { /* => */ { FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1) } }, + /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, + /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, + /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, + /*xcpt? */ false, false }, + { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, + { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1) } }, + { /* => */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, + /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, + /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, + /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_UP, + /*xcpt? */ false, false }, + { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, + { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1) } }, + { /* => */ { FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1) } }, + /*mxcsr:in */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_DOWN, + /*128:out */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_DOWN, + /*256:out */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_DOWN, + /*xcpt? */ false, false }, + { { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, + { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1) } }, + { /* => */ { FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1) } }, + /*mxcsr:in */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO, + /*128:out */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO, + /*256:out */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_ZERO, + /*xcpt? */ false, false }, + }; + + static BS3CPUINSTR4_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr4_addsubps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_addsubps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + + { bs3CpuInstr4_vaddsubps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_vaddsubps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + + { bs3CpuInstr4_vaddsubps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_vaddsubps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + }; + static BS3CPUINSTR4_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr4_addsubps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_addsubps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + + { bs3CpuInstr4_vaddsubps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_vaddsubps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + + { bs3CpuInstr4_vaddsubps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_vaddsubps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + }; + static BS3CPUINSTR4_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr4_addsubps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_addsubps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + + { bs3CpuInstr4_vaddsubps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_vaddsubps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + + { bs3CpuInstr4_vaddsubps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_vaddsubps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + + { bs3CpuInstr4_addsubps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE3, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_addsubps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE3, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + + { bs3CpuInstr4_vaddsubps_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_vaddsubps_XMM8_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_vaddsubps_YMM13_YMM14_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 13, 14, 15, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_vaddsubps_YMM13_YMM14_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 13, 14, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + }; + + static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); + return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); +} + + /** * The 32-bit protected mode main function. @@ -8233,20 +8357,21 @@ #endif #if defined(ALL_TESTS) - { "[v]addps", bs3CpuInstr4_v_addps, 0 }, - { "[v]addpd", bs3CpuInstr4_v_addpd, 0 }, - { "[v]addss", bs3CpuInstr4_v_addss, 0 }, - { "[v]addsd", bs3CpuInstr4_v_addsd, 0 }, - { "[v]haddps", bs3CpuInstr4_v_haddps, 0 }, - { "[v]haddpd", bs3CpuInstr4_v_haddpd, 0 }, - { "[v]subps", bs3CpuInstr4_v_subps, 0 }, - { "[v]subpd", bs3CpuInstr4_v_subpd, 0 }, - { "[v]subss", bs3CpuInstr4_v_subss, 0 }, - { "[v]subsd", bs3CpuInstr4_v_subsd, 0 }, - { "[v]hsubps", bs3CpuInstr4_v_hsubps, 0 }, - { "[v]hsubpd", bs3CpuInstr4_v_hsubpd, 0 }, - { "[v]mulps", bs3CpuInstr4_v_mulps, 0 }, - { "[v]mulpd", bs3CpuInstr4_v_mulpd, 0 }, - { "[v]mulss", bs3CpuInstr4_v_mulss, 0 }, - { "[v]mulsd", bs3CpuInstr4_v_mulsd, 0 }, + { "[v]addps", bs3CpuInstr4_v_addps, 0 }, + { "[v]addpd", bs3CpuInstr4_v_addpd, 0 }, + { "[v]addss", bs3CpuInstr4_v_addss, 0 }, + { "[v]addsd", bs3CpuInstr4_v_addsd, 0 }, + { "[v]haddps", bs3CpuInstr4_v_haddps, 0 }, + { "[v]haddpd", bs3CpuInstr4_v_haddpd, 0 }, + { "[v]subps", bs3CpuInstr4_v_subps, 0 }, + { "[v]subpd", bs3CpuInstr4_v_subpd, 0 }, + { "[v]subss", bs3CpuInstr4_v_subss, 0 }, + { "[v]subsd", bs3CpuInstr4_v_subsd, 0 }, + { "[v]hsubps", bs3CpuInstr4_v_hsubps, 0 }, + { "[v]hsubpd", bs3CpuInstr4_v_hsubpd, 0 }, + { "[v]mulps", bs3CpuInstr4_v_mulps, 0 }, + { "[v]mulpd", bs3CpuInstr4_v_mulpd, 0 }, + { "[v]mulss", bs3CpuInstr4_v_mulss, 0 }, + { "[v]mulsd", bs3CpuInstr4_v_mulsd, 0 }, + { "[v]addsubps", bs3CpuInstr4_v_addsubps, 0 }, #endif };