Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
===================================================================
--- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 105923)
+++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32	(revision 105924)
@@ -6265,6 +6265,92 @@
               /*256:out  */ X86_MXCSR_XCPT_FLAGS | X86_MXCSR_RC_DOWN | X86_MXCSR_DE,
               /*xcpt?    */ false, true },
-    /** @todo Normals; Invalids; Underflow,
-     *        Precision; Rounding, FZ etc. */
+    /*
+     * Invalids.
+     */
+    /*27*/{ { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1)       } },
+            { /*src1     */ { FP64_QNAN(0),                       FP64_QNAN(0),                       FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },
+            { /* =>      */ { FP64_QNAN(0),                       FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0)       } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1)       } },
+            { /*src1     */ { FP64_QNAN(0), FP64_SNAN(0),                       FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2)       } },
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN(0),                       FP64_QNAN(0),                       FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2),       FP64_SNAN_V(0, FP64_FRAC_V1),       FP64_QNAN_V(0, FP64_FRAC_V2)  } },
+            { /*src1     */ { FP64_SNAN(0),                       FP64_QNAN(0),                       FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V3)  } },
+            { /* =>      */ { FP64_QNAN_V(0, 1),                  FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, 1),                  FP64_QNAN_V(0, FP64_FRAC_V1)  } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_SNAN(0),      FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN) } },
+            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN(0),                       FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX) } },
+            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1),                  FP64_QNAN_V(0, 1),                  FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_QNAN(0), FP64_NORM_V1(0), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1)       } },
+            { /*src1     */ { FP64_QNAN(0), FP64_1(1),       FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1)                    } },
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN(0),    FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK,
+              /*256:out  */ X86_MXCSR_XCPT_MASK,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0),                          FP64_SNAN_V(0, FP64_FRAC_V1),       FP64_NORM_V3(0)              } },
+            { /*src1     */ { FP64_SNAN(0),                       FP64_1(1),                          FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1)              } },
+            { /* =>      */ { FP64_QNAN_V(0, 1),                  FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } },
+              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
+              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_IE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0),       FP64_QNAN_V(0, FP64_FRAC_V1)       } },
+            { /*src1     */ { FP64_QNAN(0),                       FP64_QNAN(0),                       FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },
+            { /* =>      */ { FP64_QNAN(0),                       FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V0)       } },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_QNAN(0), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1)       } },
+            { /*src1     */ { FP64_QNAN(0), FP64_SNAN(0),                       FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_V2)       } },
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN(0),                       FP64_QNAN(0),                       FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
+              /*xcpt?    */ true, true },
+          { { /*src2     */ { FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V2), FP64_SNAN_V(0, FP64_FRAC_V1),       FP64_QNAN_V(0, FP64_FRAC_V2) } },
+            { /*src1     */ { FP64_SNAN(0),                       FP64_QNAN(0),                 FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V3) } },
+            { /* =>      */ { FP64_QNAN_V(0, 1),                  FP64_QNAN_V(0, 1),            FP64_QNAN_V(0, FP64_FRAC_NORM_MIN), FP64_QNAN_V(0, FP64_FRAC_V1) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE,
+              /*xcpt?    */ true, true },
+          { { /*src2     */ { FP64_SNAN(0),      FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_SNAN_V(0, FP64_FRAC_NORM_MIN) } },
+            { /*src1     */ { FP64_SNAN(0),      FP64_SNAN(0),                       FP64_SNAN_V(0, FP64_FRAC_NORM_MIN), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX) } },
+            { /* =>      */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, 1),                  FP64_QNAN_V(0, 1),                  FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },
+              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_UP | X86_MXCSR_IE,
+              /*xcpt?    */ true, true },
+          { { /*src2     */ { FP64_QNAN(0), FP64_NORM_V1(0),  FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1)       } },
+            { /*src1     */ { FP64_QNAN(0), FP64_1(1),        FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1)                    } },
+            { /* =>      */ { FP64_QNAN(0), FP64_QNAN(0),     FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0),                          FP64_SNAN_V(0, FP64_FRAC_V1),       FP64_NORM_V3(0)              } },
+            { /*src1     */ { FP64_SNAN(0),                       FP64_1(1),                          FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1)              } },
+            { /* =>      */ { FP64_QNAN_V(0, 1),                  FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } },
+              /*mxcsr:in */ X86_MXCSR_RC_UP,
+              /*128:out  */ X86_MXCSR_RC_UP|X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_RC_UP|X86_MXCSR_IE,
+              /*xcpt?    */ true, true },
+    /** @todo Underflow, Precision; Rounding, FZ etc. */
     };