Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 =================================================================== --- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (revision 105912) +++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (revision 105913) @@ -1656,5 +1656,5 @@ /*11*/{ { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } }, { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } }, - { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), } }, + { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0) } }, /*mxcsr:in */ 0, /*128:out */ 0, @@ -1741,7 +1741,7 @@ /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_UP, /*xcpt? */ false, false }, - { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_0(1), FP32_1(1), FP32_0(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), } }, - { /*src1 */ { FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), } }, - { /* => */ { FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_0(1), FP32_1(1), FP32_0(1), FP32_1(1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1) } }, + { { /*src2 */ { FP32_NORM_SAFE_INT_MAX(0), FP32_1(1), FP32_0(1), FP32_1(1), FP32_0(1), FP32_1(1), FP32_NORM_SAFE_INT_MAX(0), FP32_1(1) } }, + { /*src1 */ { FP32_1(0), FP32_NORM_SAFE_INT_MAX(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_1(0), FP32_NORM_SAFE_INT_MAX(1) } }, + { /* => */ { FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_0(1), FP32_1(1), FP32_0(1), FP32_1(1), FP32_V(0, 0, FP32_EXP_SAFE_INT_MAX + 1), FP32_V(1, 0, FP32_EXP_SAFE_INT_MAX + 1) } }, /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, @@ -2936,7 +2936,7 @@ /*256:out */ 0, /*xcpt? */ false, false }, - { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, } }, - { /*src1 */ { FP64_V(0, 0, 0x408)/* 512*/, } }, - { /* => */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, } }, + { { /*src2 */ { FP64_V(0, 0, 0x409)/*1024*/, FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } }, + { /*src1 */ { FP64_V(0, 0, 0x408)/* 512*/, FP64_RAND_V2(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, + { /* => */ { FP64_V(0, 0x8000000000000, 0x409)/*1536*/, FP64_RAND_V2(1), FP64_RAND_V1(1), FP64_RAND_V3(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK, /*128:out */ X86_MXCSR_XCPT_MASK, @@ -3505,5 +3505,5 @@ { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, - { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), } }, + { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ, /*128:out */ X86_MXCSR_DAZ, @@ -3624,6 +3624,6 @@ static BS3CPUINSTR4_TEST1_T const s_aTests16[] = { - { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, @@ -3635,6 +3635,6 @@ static BS3CPUINSTR4_TEST1_T const s_aTests32[] = { - { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, @@ -3646,6 +3646,6 @@ static BS3CPUINSTR4_TEST1_T const s_aTests64[] = { - { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, @@ -3655,6 +3655,6 @@ { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_haddps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_haddps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_haddps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE3, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_haddps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE3, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddps_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, @@ -3773,5 +3773,5 @@ { { /*src2 */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MAX(1) } }, - { /* => */ { FP64_INF(1), FP64_V(1, FP32_FRAC_NORM_MIN, FP32_EXP_NORM_MIN + 1), FP64_INF(1), FP64_INF(0), } }, + { /* => */ { FP64_INF(1), FP64_V(1, FP32_FRAC_NORM_MIN, FP32_EXP_NORM_MIN + 1), FP64_INF(1), FP64_INF(0) } }, /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM, /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE, @@ -3990,6 +3990,6 @@ /*256:out */ 0, /*xcpt? */ false, false }, - { { /*src2 */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_NORM_V3(0), } }, - { /*src1 */ { FP64_SNAN(0), FP64_1(1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1), } }, + { { /*src2 */ { FP64_SNAN_V(1, FP64_FRAC_NORM_MAX), FP64_1(0), FP64_SNAN_V(0, FP64_FRAC_V1), FP64_NORM_V3(0) } }, + { /*src1 */ { FP64_SNAN(0), FP64_1(1), FP64_SNAN_V(0, FP64_FRAC_NORM_MAX), FP64_NORM_V2(1) } }, { /* => */ { FP64_QNAN_V(0, 1), FP64_QNAN_V(0, FP64_FRAC_NORM_MAX), FP64_QNAN_V(1, FP64_FRAC_NORM_MAX), FP64_QNAN_V(0, FP64_FRAC_V1) } }, /*mxcsr:in */ X86_MXCSR_RC_UP, @@ -4002,6 +4002,6 @@ static BS3CPUINSTR4_TEST1_T const s_aTests16[] = { - { bs3CpuInstr4_haddpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_haddpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_haddpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_haddpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddpd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, @@ -4013,6 +4013,6 @@ static BS3CPUINSTR4_TEST1_T const s_aTests32[] = { - { bs3CpuInstr4_haddpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_haddpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_haddpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_haddpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddpd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, @@ -4024,6 +4024,6 @@ static BS3CPUINSTR4_TEST1_T const s_aTests64[] = { - { bs3CpuInstr4_haddpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_haddpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_haddpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_haddpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddpd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, @@ -4033,6 +4033,6 @@ { bs3CpuInstr4_vhaddpd_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_haddpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_haddpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_haddpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE3, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_haddpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE3, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhaddpd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, @@ -5891,5 +5891,5 @@ { { /*src2 */ { FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0) } }, { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0) } }, - { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), } }, + { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, /*mxcsr:in */ X86_MXCSR_DAZ, /*128:out */ X86_MXCSR_DAZ, @@ -6010,6 +6010,6 @@ static BS3CPUINSTR4_TEST1_T const s_aTests16[] = { - { bs3CpuInstr4_hsubps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_hsubps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhsubps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, @@ -6021,6 +6021,6 @@ static BS3CPUINSTR4_TEST1_T const s_aTests32[] = { - { bs3CpuInstr4_hsubps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_hsubps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhsubps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, @@ -6032,6 +6032,6 @@ static BS3CPUINSTR4_TEST1_T const s_aTests64[] = { - { bs3CpuInstr4_hsubps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_hsubps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhsubps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, @@ -6041,6 +6041,6 @@ { bs3CpuInstr4_vhsubps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_hsubps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_hsubps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE3, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE3, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhsubps_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, @@ -6178,41 +6178,39 @@ /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, -#if 0 - { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_MAX(0) } }, - { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } }, - { /* => */ { FP64_NORM_MAX(0), FP64_INF(0), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0) } }, + { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0), FP64_NORM_MAX(0) } }, + { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MAX(0), FP64_NORM_MIN(0), FP64_NORM_MAX(1) } }, + { /* => */ { FP64_NORM_MAX(1), FP64_0(0), FP64_INF(0), FP64_NORM_MAX(1) } }, /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP, - /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, + /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_PE, /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_UP | X86_MXCSR_OE | X86_MXCSR_PE, /*xcpt? */ false, false }, - { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_0(0) } }, - { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MIN(0), FP64_NORM_MIN(0) } }, - { /* => */ { FP64_V(1, 0, 2), FP64_NORM_MAX(0), FP64_V(0, 0, 2), FP64_NORM_MAX(0) } }, - /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, - /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, - /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, - /*xcpt? */ false, false }, - { { /*src2 */ { FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, - { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1), FP64_NORM_MIN(1) } }, - { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_NORM_MAX), FP64_NORM_MAX(0), FP64_V(1, 0, 2), FP64_0(0) } }, - /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO, - /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, - /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_RC_ZERO | X86_MXCSR_OE | X86_MXCSR_PE, - /*xcpt? */ false, false }, - { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, - { /*src1 */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, - { /* => */ { FP64_0(0), FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, + { { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MAX(0) } }, + { /*src1 */ { FP64_NORM_MIN(1), FP64_NORM_MIN(1), FP64_NORM_MIN(0), FP64_NORM_MAX(0) } }, + { /* => */ { FP64_0(0), FP64_0(0), FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_NORM_MAX), FP64_NORM_MAX(1) } }, /*mxcsr:in */ X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_RC_ZERO, - /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_OE, + /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*xcpt? */ false, true }, - { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(1) } }, - { /*src1 */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } }, - { /* => */ { FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0) } }, + { { /*src2 */ { FP64_0(0), FP64_NORM_MAX(0), FP64_NORM_MIN(1), FP64_NORM_MIN(0) } }, + { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1), FP64_NORM_MIN(1), FP64_1(1) } }, + { /* => */ { FP64_0(0), FP64_NORM_MAX(1), FP64_INF(0), FP64_NORM_MAX(1) } }, + /*mxcsr:in */ 0, + /*128:out */ 0, + /*256:out */ X86_MXCSR_PE, + /*xcpt? */ false, true }, + { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0) } }, + { /*src1 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } }, + { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(1), FP64_V(0, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_0(0) } }, /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO, /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_RC_ZERO | X86_MXCSR_PE, /*xcpt? */ false, false }, -#endif + { { /*src2 */ { FP64_NORM_SAFE_INT_MIN(1), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0) } }, + { /*src1 */ { FP64_NORM_SAFE_INT_MIN(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MAX(0), FP64_NORM_SAFE_INT_MIN(0) } }, + { /* => */ { FP64_V(1, FP64_FRAC_NORM_MAX - 1, FP64_EXP_SAFE_INT_MAX), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0), FP64_0(0) } }, + /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP, + /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_PE, + /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_RC_UP | X86_MXCSR_PE, + /*xcpt? */ false, false }, /** @todo Denormals; Normals; Invalids; Underflow, * Precision; Rounding, FZ etc. */ @@ -6221,6 +6219,6 @@ static BS3CPUINSTR4_TEST1_T const s_aTests16[] = { - { bs3CpuInstr4_hsubpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_hsubpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhsubpd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, @@ -6232,6 +6230,6 @@ static BS3CPUINSTR4_TEST1_T const s_aTests32[] = { - { bs3CpuInstr4_hsubpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_hsubpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhsubpd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, @@ -6243,6 +6241,6 @@ static BS3CPUINSTR4_TEST1_T const s_aTests64[] = { - { bs3CpuInstr4_hsubpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_hsubpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhsubpd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, @@ -6252,6 +6250,6 @@ { bs3CpuInstr4_vhsubpd_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_hsubpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, - { bs3CpuInstr4_hsubpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE3, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE3, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhsubpd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, @@ -7294,5 +7292,5 @@ */ /*24*/{ { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } }, - { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1), } }, + { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } }, /*mxcsr:in */ 0, @@ -7301,5 +7299,5 @@ /*xcpt? */ true, true }, { { /*src2 */ { FP32_DENORM_MAX(0), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(0), FP32_1(1), FP32_RAND_V0(1), FP32_RAND_V5(1) } }, - { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1), } }, + { /*src1 */ { FP32_0(0), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(0), FP32_RAND_V3(1), FP32_1(1), FP32_1(1) } }, { /* => */ { FP32_0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(1), FP32_RAND_V3(0), FP32_RAND_V0(0), FP32_RAND_V5(0) } }, /*mxcsr:in */ 0,