Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac =================================================================== --- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac (revision 105899) +++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac (revision 105900) @@ -329,4 +329,22 @@ ; +;; [v]hsubpd +; +EMIT_INSTR_PLUS_ICEBP hsubpd, XMM1, XMM2 +EMIT_INSTR_PLUS_ICEBP hsubpd, XMM1, FSxBX +EMIT_INSTR_PLUS_ICEBP_C64 hsubpd, XMM8, XMM9 +EMIT_INSTR_PLUS_ICEBP_C64 hsubpd, XMM8, FSxBX + +EMIT_INSTR_PLUS_ICEBP vhsubpd, XMM1, XMM2, XMM3 +EMIT_INSTR_PLUS_ICEBP vhsubpd, XMM1, XMM2, FSxBX +EMIT_INSTR_PLUS_ICEBP_C64 vhsubpd, XMM8, XMM9, XMM10 +EMIT_INSTR_PLUS_ICEBP_C64 vhsubpd, XMM8, XMM9, FSxBX + +EMIT_INSTR_PLUS_ICEBP vhsubpd, YMM1, YMM2, YMM3 +EMIT_INSTR_PLUS_ICEBP vhsubpd, YMM1, YMM2, FSxBX +EMIT_INSTR_PLUS_ICEBP_C64 vhsubpd, YMM8, YMM9, YMM10 +EMIT_INSTR_PLUS_ICEBP_C64 vhsubpd, YMM8, YMM9, FSxBX + +; ;; [v]mulps ; Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 =================================================================== --- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (revision 105899) +++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (revision 105900) @@ -6048,4 +6048,109 @@ { bs3CpuInstr4_vhsubps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, { bs3CpuInstr4_vhsubps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + }; + + static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); + return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); +} + + +/* + * [V]HSUBPD. + */ +BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_hsubpd(uint8_t bMode) +{ + static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] = + { + /* + * Zero. + */ + /* 0*/{ { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, + { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, + { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, + /*mxcsr:in */ X86_MXCSR_XCPT_MASK, + /*128:out */ X86_MXCSR_XCPT_MASK, + /*256:out */ X86_MXCSR_XCPT_MASK, + /*xcpt? */ false, false }, + { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, + { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, + { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, + /*mxcsr:in */ 0, + /*128:out */ 0, + /*256:out */ 0, + /*xcpt? */ false, false }, + { { /*src2 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, + { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, + { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, + /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, + /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, + /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP, + /*xcpt? */ false, false }, + { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, + { /*src1 */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } }, + { /* => */ { FP64_0(1), FP64_0(1), FP64_0(0), FP64_0(0) } }, + /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, + /*128:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, + /*256:out */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO, + /*xcpt? */ false, false }, + { { /*src2 */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } }, + { /*src1 */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } }, + { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, + /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, + /*128:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, + /*256:out */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO, + /*xcpt? */ false, false }, + { { /*src2 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, + { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } }, + { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, + /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, + /*128:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, + /*256:out */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN, + /*xcpt? */ false, false }, + /** @todo Infinity; Overflow/Precision; Denormals; Normals; Invalids; Underflow, + * Precision; Rounding, FZ etc. */ + }; + + static BS3CPUINSTR4_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr4_hsubpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + + { bs3CpuInstr4_vhsubpd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_vhsubpd_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + + { bs3CpuInstr4_vhsubpd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_vhsubpd_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + }; + static BS3CPUINSTR4_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr4_hsubpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + + { bs3CpuInstr4_vhsubpd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_vhsubpd_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + + { bs3CpuInstr4_vhsubpd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_vhsubpd_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + }; + static BS3CPUINSTR4_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr4_hsubpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + + { bs3CpuInstr4_vhsubpd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_vhsubpd_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + + { bs3CpuInstr4_vhsubpd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_vhsubpd_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + + { bs3CpuInstr4_hsubpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_hsubpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + + { bs3CpuInstr4_vhsubpd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_vhsubpd_XMM8_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_vhsubpd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, + { bs3CpuInstr4_vhsubpd_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues }, }; @@ -7897,4 +8002,5 @@ { "[v]subsd", bs3CpuInstr4_v_subsd, 0 }, { "[v]hsubps", bs3CpuInstr4_v_hsubps, 0 }, + { "[v]hsubpd", bs3CpuInstr4_v_hsubpd, 0 }, { "[v]mulps", bs3CpuInstr4_v_mulps, 0 }, { "[v]mulpd", bs3CpuInstr4_v_mulpd, 0 },