Changeset 105830 in vbox

Timestamp:

Aug 22, 2024 6:13:37 PM (5 weeks ago)

Author:

vboxsync

Message:

Disassembler/ARMv8: Implement decoding of the ldp/stp unsigned variant instructions and add testcases, bugref:10394

Location:

trunk/src/VBox/Disassembler

Files:

• DisasmCore-armv8.cpp (modified) (4 diffs)
• DisasmFormatArmV8.cpp (modified) (1 diff)
• DisasmInternal-armv8.h (modified) (2 diffs)
• DisasmTables-armv8-a64.cpp (modified) (2 diffs)
• testcase/tstDisasmArmv8-1-asm.S (modified) (3 diffs)

trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp

@@ -89 +89 @@
 static FNDISPARSEARMV8 disArmV8ParseShiftAmount;
 static FNDISPARSEARMV8 disArmV8ParseImmMemOff;
+static FNDISPARSEARMV8 disArmV8ParseSImmMemOff;
 /** @}  */
 
@@ -122 +123 @@
     disArmV8ParseShift,
     disArmV8ParseShiftAmount,
-    disArmV8ParseImmMemOff
+    disArmV8ParseImmMemOff,
+    disArmV8ParseSImmMemOff
 };
 
@@ -460 +462 @@
             AssertReleaseFailed();
     }
-    pParam->armv8.cb = sizeof(uint16_t);
+    pParam->armv8.cb = sizeof(int16_t);
+    return VINF_SUCCESS;
+}
+
+
+static int disArmV8ParseSImmMemOff(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit)
+{
+    RT_NOREF(pInsnClass, pf64Bit);
+
+    AssertReturn(pInsnParm->cBits <= 7, VERR_INTERNAL_ERROR_2);
+    AssertReturn(   (pOp->fFlags & DISARMV8INSNCLASS_F_FORCED_32BIT)
+                 || (pOp->fFlags & DISARMV8INSNCLASS_F_FORCED_64BIT),
+                 VERR_INTERNAL_ERROR_2);
+
+    pParam->armv8.cb = sizeof(int16_t);
+    pParam->armv8.u.offBase = disArmV8ExtractBitVecFromInsnSignExtend(u32Insn, pInsnParm->idxBitStart, pInsnParm->cBits);
+    pParam->armv8.u.offBase <<= (pOp->fFlags & DISARMV8INSNCLASS_F_FORCED_32BIT) ? 2 : 3; 
+    pDis->armv8.cbOperand   =   (pOp->fFlags & DISARMV8INSNCLASS_F_FORCED_32BIT) ? sizeof(uint32_t) : sizeof(uint64_t);
     return VINF_SUCCESS;
 }
@@ -591 +610 @@
     bool f64Bit = false;
 
+    /** @todo Get rid of these and move them to the per opcode
+     * (SF can become a decoder step). */
     if (pInsnClass->fClass & DISARMV8INSNCLASS_F_SF)
         f64Bit = RT_BOOL(u32Insn & RT_BIT_32(31));
     else if (pInsnClass->fClass & DISARMV8INSNCLASS_F_FORCED_64BIT)
+        f64Bit = true;
+
+    if (pOp->fFlags & DISARMV8INSNCLASS_F_FORCED_32BIT)
+        f64Bit = false;
+    else if (pOp->fFlags & DISARMV8INSNCLASS_F_FORCED_64BIT)
         f64Bit = true;
 

trunk/src/VBox/Disassembler/DisasmFormatArmV8.cpp

@@ -724 +724 @@
                     {
                         PUT_SZ(", #");
-                        PUT_NUM_16(pParam->armv8.u.offBase);
+                        PUT_NUM_S16(pParam->armv8.u.offBase);
                     }
 

trunk/src/VBox/Disassembler/DisasmInternal-armv8.h

@@ -67 +67 @@
     kDisParmParseShiftAmount,
     kDisParmParseImmMemOff,
+    kDisParmParseSImmMemOff,
     kDisParmParseMax
 } DISPARMPARSEIDX;
@@ -184 +185 @@
 /** The instruction class is using the 64-bit register encoding only. */
 #define DISARMV8INSNCLASS_F_FORCED_64BIT                RT_BIT_32(2)
+/** The instruction class is using the 32-bit register encoding only. */
+#define DISARMV8INSNCLASS_F_FORCED_32BIT                RT_BIT_32(3)
 
 

trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp

@@ -611 +611 @@
 
 /*
+ * STP/LDP/STGP/LDPSW
+ *
+ * Note: The opc,L bitfields are concatenated to form an index.
+ */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairOff)
+ DIS_ARMV8_OP_EX(0x29000000, "stp",             OP_ARMV8_A64_STP,       DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
+ DIS_ARMV8_OP_EX(0x29400000, "ldp",             OP_ARMV8_A64_LDP,       DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
+    INVALID_OPCODE,
+    INVALID_OPCODE,
+ DIS_ARMV8_OP_EX(0xa9000000, "stp",             OP_ARMV8_A64_STP,       DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
+ DIS_ARMV8_OP_EX(0xa9400000, "ldp",             OP_ARMV8_A64_LDP,       DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
+    INVALID_OPCODE,
+    INVALID_OPCODE,
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairOff)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,           10,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseReg,            5,  5, 2 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff,    15,  7, 2 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(LdStRegPairOff, 0xffc00000 /*fFixedInsn*/, 0 /*fClass*/,
+                                                kDisArmV8OpcDecodeCollate,
+                                                RT_BIT_32(22) | RT_BIT_32(30) | RT_BIT_32(31), 22,
+                                                kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmAddrInGpr);
+
+
+/*
+ * C4.1.94 - Loads and Stores - Load/Store register pair variants
+ *
+ * Differentiate further based on the op2<14:13> field.
+ *
+ *     Bit  24 23
+ *     +-------------------------------------------
+ *           0  0 Load/store no-allocate pair (offset)
+ *           0  1 Load/store register pair (post-indexed)
+ *           1  0 Load/store register pair (offset).
+ *           1  1 Load/store register pair (pre-indexed).
+ */
+DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegPair)
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairOff),
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
+DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegPair, RT_BIT_32(23) | RT_BIT_32(24), 23);
+
+
+/*
  * C4.1.94 - Loads and Stores
  *
@@ -628 +673 @@
     DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
     DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
-    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPair),
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStReg),
 DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStOp0Lo, RT_BIT_32(28) | RT_BIT_32(29), 28);

trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S

@@ -28 +28 @@
 .private_extern _TestProcA64
 _TestProcA64:
+
         ; Miscellaneous instructions without a parameter
         nop
@@ -409 +410 @@
         ldrsw x0, [x28, #16380]
 
+        ldp w0, w1, [x28]
+        ldp w0, w1, [x28, #4]
+        ldp w0, w1, [x28, #-256]
+        ldp w0, w1, [x28, #252]
+
+        ldp x0, x1, [x28]
+        ldp x0, x1, [x28, #8]
+        ldp x0, x1, [x28, #-512]
+        ldp x0, x1, [x28, #504]
+
         ; Memory stores
         strb w0, [x28]
@@ -425 +436 @@
         str w0, [x28, #4]
         str w0, [x28, #16380]
+
+        stp w0, w1, [x28]
+        stp w0, w1, [x28, #4]
+        stp w0, w1, [x28, #-256]
+        stp w0, w1, [x28, #252]
+
+        stp x0, x1, [x28]
+        stp x0, x1, [x28, #8]
+        stp x0, x1, [x28, #-512]
+        stp x0, x1, [x28, #504]
 
         ; Conditional compare