Changeset 105806 in vbox
- Timestamp:
- Aug 22, 2024 7:36:59 AM (5 weeks ago)
- Location:
- trunk/src/VBox/Disassembler
- Files:
-
- 3 edited
-
DisasmCore-armv8.cpp (modified) (2 diffs)
-
DisasmInternal-armv8.h (modified) (7 diffs)
-
DisasmTables-armv8-a64.cpp (modified) (9 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp
r105796 r105806 537 537 538 538 int rc = VINF_SUCCESS; 539 for (uint32_t i = 0; i < RT_ELEMENTS(pInsnClass->aParms) && RT_SUCCESS(rc); i++) 540 { 541 PCDISARMV8INSNPARAM pInsnParm = &pInsnClass->aParms[i]; 542 if (pInsnParm->idxParse != kDisParmParseNop) 543 rc = g_apfnDisasm[pInsnClass->aParms[i].idxParse](pDis, u32Insn, pInsnClass, 544 pInsnParm->idxParam != DIS_ARMV8_INSN_PARAM_UNSET 545 ? &pDis->aParams[pInsnParm->idxParam] 546 : NULL, 547 pInsnParm, &f64Bit); 548 else 549 break; 539 PCDISARMV8INSNPARAM pDecode = &pInsnClass->paParms[0]; 540 while ( (pDecode->idxParse != kDisParmParseNop) 541 && RT_SUCCESS(rc)) 542 { 543 rc = g_apfnDisasm[pDecode->idxParse](pDis, u32Insn, pInsnClass, 544 pDecode->idxParam != DIS_ARMV8_INSN_PARAM_UNSET 545 ? &pDis->aParams[pDecode->idxParam] 546 : NULL, 547 pDecode, &f64Bit); 548 pDecode++; 550 549 } 551 550 … … 662 661 pDis->cbInstr = sizeof(u32Insn); 663 662 664 return disInstrArmV8DecodeWorker(pDis, u32Insn, &g_ ArmV8A64DecodeL0.Hdr);663 return disInstrArmV8DecodeWorker(pDis, u32Insn, &g_aArmV8A64InsnDecodeL0.Hdr); 665 664 } 666 665 -
trunk/src/VBox/Disassembler/DisasmInternal-armv8.h
r105789 r105806 88 88 typedef struct DISARMV8INSNPARAM 89 89 { 90 /** The parser to use for the parameter. */90 /** The parser to use for the decode step. */ 91 91 DISPARMPARSEIDX idxParse; 92 92 /** Bit index at which the field starts. */ … … 169 169 /** Parameter types. */ 170 170 DISARMV8OPPARM aenmParamTypes[4]; 171 /** The decoding steps. */172 DISARMV8INSNPARAM aParms[5];171 /** The array of decoding steps. */ 172 PCDISARMV8INSNPARAM paParms; 173 173 } DISARMV8INSNCLASS; 174 174 /** Pointer to a constant instruction class descriptor. */ … … 184 184 185 185 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(a_Name) \ 186 static const DISARMV8OPCODE a_Name ## Opcodes[] = { 187 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_4(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 188 a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4) \ 189 }; \ 190 static const DISARMV8INSNCLASS a_Name = { { kDisArmV8DecodeType_InsnClass, RT_ELEMENTS(a_Name ## Opcodes) }, &a_Name ## Opcodes[0],\ 191 a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 192 { a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4 }, { 193 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_3(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 194 a_enmParamType1, a_enmParamType2, a_enmParamType3) \ 195 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_4(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 196 a_enmParamType1, a_enmParamType2, a_enmParamType3, kDisArmv8OpParmNone) 197 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_2(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 198 a_enmParamType1, a_enmParamType2) \ 199 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_3(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 200 a_enmParamType1, a_enmParamType2, kDisArmv8OpParmNone) 201 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 202 a_enmParamType1) \ 203 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_2(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 204 a_enmParamType1, kDisArmv8OpParmNone) 205 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_0(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift) \ 206 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 207 kDisArmv8OpParmNone) 208 209 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END } } 186 static const DISARMV8OPCODE g_aArmV8A64Insn ## a_Name ## Opcodes[] = { 187 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(a_Name) \ 188 }; \ 189 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = { 190 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 191 a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4) \ 192 DIS_ARMV8_INSN_PARAM_NONE \ 193 }; \ 194 static const DISARMV8INSNCLASS g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_InsnClass, \ 195 RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## Opcodes) }, \ 196 & g_aArmV8A64Insn ## a_Name ## Opcodes[0], \ 197 a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 198 { a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4 }, \ 199 & g_aArmV8A64Insn ## a_Name ## Decode[0] }; 200 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 201 a_enmParamType1, a_enmParamType2, a_enmParamType3) \ 202 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 203 a_enmParamType1, a_enmParamType2, a_enmParamType3, kDisArmv8OpParmNone) 204 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 205 a_enmParamType1, a_enmParamType2) \ 206 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 207 a_enmParamType1, a_enmParamType2, kDisArmv8OpParmNone) 208 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 209 a_enmParamType1) \ 210 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 211 a_enmParamType1, kDisArmv8OpParmNone) 212 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_0(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift) \ 213 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(a_Name, a_fFixedInsn, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 214 kDisArmv8OpParmNone) 215 216 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END \ 217 DIS_ARMV8_INSN_PARAM_NONE } 210 218 211 219 /** … … 226 234 227 235 #define DIS_ARMV8_DECODE_TBL_ENTRY_INIT(a_fMask, a_fValue, a_pNext) \ 228 { a_fMask, a_fValue, & a_pNext.Hdr }236 { a_fMask, a_fValue, & g_aArmV8A64Insn ## a_pNext.Hdr } 229 237 230 238 … … 244 252 245 253 #define DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(a_Name) \ 246 static const DISARMV8DECODETBLENTRY a_Name ## TblEnt[] = {254 static const DISARMV8DECODETBLENTRY g_aArmV8A64Insn ## a_Name ## TblEnt[] = { 247 255 248 256 #define DIS_ARMV8_DECODE_TBL_DEFINE_END(a_Name) \ 249 257 }; \ 250 static const DISARMV8DECODETBL a_Name = { { kDisArmV8DecodeType_Table, RT_ELEMENTS(a_Name ## TblEnt) }, &a_Name ## TblEnt[0] } 258 static const DISARMV8DECODETBL g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Table, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## TblEnt) }, \ 259 & g_aArmV8A64Insn ## a_Name ## TblEnt[0] } 251 260 252 261 … … 269 278 270 279 #define DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(a_Name) \ 271 static const PCDISARMV8DECODEHDR a_Name ## MapHdrs[] = {280 static const PCDISARMV8DECODEHDR g_aArmV8A64Insn ## a_Name ## MapHdrs[] = { 272 281 273 282 #define DIS_ARMV8_DECODE_MAP_DEFINE_END(a_Name, a_fMask, a_cShift) \ 274 283 }; \ 275 static const DISARMV8DECODEMAP a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(a_Name ## MapHdrs) }, a_fMask, a_cShift, &a_Name ## MapHdrs[0] } 284 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \ 285 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] } 276 286 277 287 #define DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(a_Name, a_fMask, a_cShift) \ 278 288 }; \ 279 DECL_HIDDEN_CONST(DISARMV8DECODEMAP) a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(a_Name ## MapHdrs) }, a_fMask, a_cShift, &a_Name ## MapHdrs[0] } 289 DECL_HIDDEN_CONST(DISARMV8DECODEMAP) g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \ 290 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] } 280 291 281 292 #define DIS_ARMV8_DECODE_MAP_INVALID_ENTRY NULL 282 #define DIS_ARMV8_DECODE_MAP_ENTRY(a_Next) & a_Next.Hdr293 #define DIS_ARMV8_DECODE_MAP_ENTRY(a_Next) & g_aArmV8A64Insn ## a_Next.Hdr 283 294 284 295 … … 287 298 extern DECL_HIDDEN_DATA(DISOPCODE) g_ArmV8A64InvalidOpcode[1]; 288 299 289 extern DECL_HIDDEN_DATA(DISARMV8DECODEMAP) g_ ArmV8A64DecodeL0;300 extern DECL_HIDDEN_DATA(DISARMV8DECODEMAP) g_aArmV8A64InsnDecodeL0; 290 301 /** @} */ 291 302 -
trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp
r105793 r105806 58 58 59 59 /* UDF */ 60 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_aArmV8A64InsnRsvd)60 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Rsvd) 61 61 DIS_ARMV8_OP(0x00000000, "udf" , OP_ARMV8_A64_UDF, DISOPTYPE_INVALID) 62 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(g_aArmV8A64InsnRsvd, 0xffff0000 /*fFixedInsn*/, 0 /*fClass*/, 62 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Rsvd) 63 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 0, 16, 0 /*idxParam*/), 64 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(Rsvd, 0xffff0000 /*fFixedInsn*/, 0 /*fClass*/, 63 65 kDisArmV8OpcDecodeNop, 0xffff0000, 16, 64 kDisArmv8OpParmImm) 65 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 0, 16, 0 /*idxParam*/), 66 DIS_ARMV8_INSN_PARAM_NONE, 67 DIS_ARMV8_INSN_PARAM_NONE, 68 DIS_ARMV8_INSN_PARAM_NONE, 69 DIS_ARMV8_INSN_PARAM_NONE 70 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 71 66 kDisArmv8OpParmImm); 72 67 73 68 /* ADR/ADRP */ 74 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64Adr)69 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Adr) 75 70 DIS_ARMV8_OP(0x10000000, "adr" , OP_ARMV8_A64_ADR, DISOPTYPE_HARMLESS), 76 71 DIS_ARMV8_OP(0x90000000, "adrp" , OP_ARMV8_A64_ADRP, DISOPTYPE_HARMLESS) 77 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_2(g_ArmV8A64Adr, 0x9f000000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT, 78 kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31, 79 kDisArmv8OpParmGpr, kDisArmv8OpParmImmRel) 72 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Adr) 80 73 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 81 74 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmAdr, 0, 0, 1 /*idxParam*/), 82 DIS_ARMV8_INSN_PARAM_NONE, 83 DIS_ARMV8_INSN_PARAM_NONE, 84 DIS_ARMV8_INSN_PARAM_NONE 85 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 75 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(Adr, 0x9f000000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT, 76 kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31, 77 kDisArmv8OpParmGpr, kDisArmv8OpParmImmRel); 86 78 87 79 88 80 /* ADD/ADDS/SUB/SUBS - shifted immediate variant */ 89 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64AddSubImm)81 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(AddSubImm) 90 82 DIS_ARMV8_OP(0x11000000, "add" , OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS), 91 83 DIS_ARMV8_OP(0x31000000, "adds" , OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS), 92 84 DIS_ARMV8_OP(0x51000000, "sub" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS), 93 85 DIS_ARMV8_OP(0x71000000, "subs" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS), 94 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_3(g_ArmV8A64AddSubImm, 0x7f800000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF, 95 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 96 kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmImm) 86 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubImm) 97 87 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 98 88 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5, 1 /*idxParam*/), 99 89 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 10, 12, 2 /*idxParam*/), 100 90 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseSh12, 22, 1, 2 /*idxParam*/), 101 DIS_ARMV8_INSN_PARAM_NONE 102 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 91 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(AddSubImm, 0x7f800000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF, 92 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 93 kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmImm); 103 94 104 95 105 96 /* ADD/ADDS/SUB/SUBS - shifted register variant */ 106 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_aArmV8A64InsnAddSubShiftReg)97 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(AddSubShiftReg) 107 98 DIS_ARMV8_OP(0x0b000000, "add" , OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS), 108 99 DIS_ARMV8_OP(0x2b000000, "adds" , OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS), 109 100 DIS_ARMV8_OP(0x4b000000, "sub" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS), 110 101 DIS_ARMV8_OP(0x6b000000, "subs" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS), 111 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_3(g_aArmV8A64InsnAddSubShiftReg, 0x7f200000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF, 112 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 113 kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmGpr) 102 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubShiftReg) 114 103 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 115 104 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5, 1 /*idxParam*/), 116 105 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 16, 5, 2 /*idxParam*/), 117 106 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseShift, 22, 2, 2 /*idxParam*/), 118 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseShiftAmount, 10, 6, 2 /*idxParam*/) 119 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 107 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseShiftAmount, 10, 6, 2 /*idxParam*/), 108 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(AddSubShiftReg, 0x7f200000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF, 109 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 110 kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmGpr); 120 111 121 112 122 113 /* AND/ORR/EOR/ANDS */ 123 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64LogicalImm)114 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogicalImm) 124 115 DIS_ARMV8_OP(0x12000000, "and" , OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS), 125 116 DIS_ARMV8_OP(0x32000000, "orr" , OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS), 126 117 DIS_ARMV8_OP(0x52000000, "eor" , OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS), 127 118 DIS_ARMV8_OP(0x72000000, "ands" , OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS), 128 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_3(g_ArmV8A64LogicalImm, 0x7f800000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF, 129 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 130 kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmImm) 119 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogicalImm) 131 120 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 132 121 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5, 1 /*idxParam*/), 133 122 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmsImmrN, 10, 13, 2 /*idxParam*/), 134 DIS_ARMV8_INSN_PARAM_NONE,135 DIS_ARMV8_INSN_PARAM_NONE136 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;123 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(LogicalImm, 0x7f800000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF, 124 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 125 kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmImm); 137 126 138 127 139 128 /* MOVN/MOVZ/MOVK */ 140 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64MoveWide)129 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(MoveWide) 141 130 DIS_ARMV8_OP(0x12800000, "movn", OP_ARMV8_A64_MOVN, DISOPTYPE_HARMLESS), 142 131 INVALID_OPCODE, 143 132 DIS_ARMV8_OP(0x52800000, "movz" , OP_ARMV8_A64_MOVZ, DISOPTYPE_HARMLESS), 144 133 DIS_ARMV8_OP(0x72800000, "movk" , OP_ARMV8_A64_MOVK, DISOPTYPE_HARMLESS), 145 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_2(g_ArmV8A64MoveWide, 0x7f800000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF, 146 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 147 kDisArmv8OpParmGpr, kDisArmv8OpParmImm) 134 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(MoveWide) 148 135 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 149 136 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 16, 1 /*idxParam*/), 150 137 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseHw, 21, 2, 1 /*idxParam*/), 151 DIS_ARMV8_INSN_PARAM_NONE,152 DIS_ARMV8_INSN_PARAM_NONE153 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;138 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(MoveWide, 0x7f800000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF, 139 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 140 kDisArmv8OpParmGpr, kDisArmv8OpParmImm); 154 141 155 142 156 143 /* SBFM/BFM/UBFM */ 157 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64Bitfield)144 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Bitfield) 158 145 DIS_ARMV8_OP(0x13000000, "sbfm", OP_ARMV8_A64_SBFM, DISOPTYPE_HARMLESS), 159 146 DIS_ARMV8_OP(0x33000000, "bfm", OP_ARMV8_A64_BFM, DISOPTYPE_HARMLESS), 160 147 DIS_ARMV8_OP(0x53000000, "ubfm", OP_ARMV8_A64_UBFM, DISOPTYPE_HARMLESS), 161 148 INVALID_OPCODE, 162 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_4(g_ArmV8A64Bitfield, 0x7f800000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF | DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT, 163 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 164 kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmImm, kDisArmv8OpParmImm) 149 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Bitfield) 165 150 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 166 151 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5, 1 /*idxParam*/), 167 152 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 16, 6, 2 /*idxParam*/), 168 153 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 10, 6, 3 /*idxParam*/), 169 DIS_ARMV8_INSN_PARAM_NONE 170 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 154 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(Bitfield, 0x7f800000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF | DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT, 155 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 156 kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmImm, kDisArmv8OpParmImm); 171 157 172 158 … … 185 171 * 1 1 1 Extract 186 172 */ 187 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN( g_aArmV8A64InsnDataProcessingImm)188 DIS_ARMV8_DECODE_MAP_ENTRY( g_ArmV8A64Adr),189 DIS_ARMV8_DECODE_MAP_ENTRY( g_ArmV8A64Adr),190 DIS_ARMV8_DECODE_MAP_ENTRY( g_ArmV8A64AddSubImm),173 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcessingImm) 174 DIS_ARMV8_DECODE_MAP_ENTRY(Adr), 175 DIS_ARMV8_DECODE_MAP_ENTRY(Adr), 176 DIS_ARMV8_DECODE_MAP_ENTRY(AddSubImm), 191 177 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Add/subtract immediate with tags. */ 192 DIS_ARMV8_DECODE_MAP_ENTRY( g_ArmV8A64LogicalImm),193 DIS_ARMV8_DECODE_MAP_ENTRY( g_ArmV8A64MoveWide),194 DIS_ARMV8_DECODE_MAP_ENTRY( g_ArmV8A64Bitfield),178 DIS_ARMV8_DECODE_MAP_ENTRY(LogicalImm), 179 DIS_ARMV8_DECODE_MAP_ENTRY(MoveWide), 180 DIS_ARMV8_DECODE_MAP_ENTRY(Bitfield), 195 181 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /** @todo Extract */ 196 DIS_ARMV8_DECODE_MAP_DEFINE_END( g_aArmV8A64InsnDataProcessingImm, RT_BIT_32(23) | RT_BIT_32(24) | RT_BIT_32(25), 23);182 DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcessingImm, RT_BIT_32(23) | RT_BIT_32(24) | RT_BIT_32(25), 23); 197 183 198 184 199 185 /* B.cond/BC.cond */ 200 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64CondBr)186 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CondBr) 201 187 DIS_ARMV8_OP(0x54000000, "b", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW | DISOPTYPE_RELATIVE_CONTROLFLOW | DISOPTYPE_COND_CONTROLFLOW), 202 188 DIS_ARMV8_OP(0x54000010, "bc" , OP_ARMV8_A64_BC, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW | DISOPTYPE_RELATIVE_CONTROLFLOW | DISOPTYPE_COND_CONTROLFLOW), 203 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(g_ArmV8A64CondBr, 0xff000010 /*fFixedInsn*/, 0 /*fClass*/, 204 kDisArmV8OpcDecodeNop, RT_BIT_32(4), 4, 205 kDisArmv8OpParmImmRel) 189 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CondBr) 206 190 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseCond, 0, 4, DIS_ARMV8_INSN_PARAM_UNSET), 207 191 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 5, 19, 0 /*idxParam*/), 208 DIS_ARMV8_INSN_PARAM_NONE, 209 DIS_ARMV8_INSN_PARAM_NONE, 210 DIS_ARMV8_INSN_PARAM_NONE 211 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 192 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(CondBr, 0xff000010 /*fFixedInsn*/, 0 /*fClass*/, 193 kDisArmV8OpcDecodeNop, RT_BIT_32(4), 4, 194 kDisArmv8OpParmImmRel); 212 195 213 196 214 197 /* SVC/HVC/SMC/BRK/HLT/TCANCEL/DCPS1/DCPS2/DCPS3 */ 215 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64Excp)198 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Excp) 216 199 DIS_ARMV8_OP(0xd4000001, "svc", OP_ARMV8_A64_SVC, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT), 217 200 DIS_ARMV8_OP(0xd4000002, "hvc", OP_ARMV8_A64_HVC, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT | DISOPTYPE_PRIVILEGED), … … 223 206 DIS_ARMV8_OP(0xd4a00002, "dcps2", OP_ARMV8_A64_DCPS2, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT), 224 207 DIS_ARMV8_OP(0xd4a00003, "dcps3", OP_ARMV8_A64_DCPS3, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT), 225 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(g_ArmV8A64Excp, 0xffe0001f /*fFixedInsn*/, 0 /*fClass*/, 226 kDisArmV8OpcDecodeLookup, 0xffe0001f, 0, 227 kDisArmv8OpParmImm) 208 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Excp) 228 209 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 16, 0 /*idxParam*/), 229 DIS_ARMV8_INSN_PARAM_NONE, 230 DIS_ARMV8_INSN_PARAM_NONE, 231 DIS_ARMV8_INSN_PARAM_NONE, 232 DIS_ARMV8_INSN_PARAM_NONE 233 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 210 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(Excp, 0xffe0001f /*fFixedInsn*/, 0 /*fClass*/, 211 kDisArmV8OpcDecodeLookup, 0xffe0001f, 0, 212 kDisArmv8OpParmImm); 234 213 235 214 236 215 /* WFET/WFIT */ 237 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64SysReg)216 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysReg) 238 217 DIS_ARMV8_OP(0xd5031000, "wfet", OP_ARMV8_A64_WFET, DISOPTYPE_HARMLESS), /* FEAT_WFxT */ 239 218 DIS_ARMV8_OP(0x54000010, "wfit" , OP_ARMV8_A64_WFIT, DISOPTYPE_HARMLESS), /* FEAT_WFxT */ 240 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(g_ArmV8A64SysReg, 0xffffffe0 /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT, 241 kDisArmV8OpcDecodeNop, 0xfe0, 5, 242 kDisArmv8OpParmGpr) 243 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 244 DIS_ARMV8_INSN_PARAM_NONE, 245 DIS_ARMV8_INSN_PARAM_NONE, 246 DIS_ARMV8_INSN_PARAM_NONE, 247 DIS_ARMV8_INSN_PARAM_NONE 248 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 219 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysReg) 220 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 221 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(SysReg, 0xffffffe0 /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT, 222 kDisArmV8OpcDecodeNop, 0xfe0, 5, 223 kDisArmv8OpParmGpr); 249 224 250 225 251 226 /* Various hint instructions */ 252 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64Hints)227 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Hints) 253 228 DIS_ARMV8_OP(0xd503201f, "nop", OP_ARMV8_A64_NOP, DISOPTYPE_HARMLESS), 254 229 DIS_ARMV8_OP(0xd503203f, "yield", OP_ARMV8_A64_YIELD, DISOPTYPE_HARMLESS), … … 260 235 DIS_ARMV8_OP(0xd50320ff, "xpaclri", OP_ARMV8_A64_XPACLRI, DISOPTYPE_HARMLESS), /* FEAT_PAuth */ 261 236 /** @todo */ 262 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_0(g_ArmV8A64Hints, 0xffffffff /*fFixedInsn*/, 0 /*fClass*/, 263 kDisArmV8OpcDecodeNop, 0xfe0, 5) 264 DIS_ARMV8_INSN_PARAM_NONE, 265 DIS_ARMV8_INSN_PARAM_NONE, 266 DIS_ARMV8_INSN_PARAM_NONE, 267 DIS_ARMV8_INSN_PARAM_NONE, 268 DIS_ARMV8_INSN_PARAM_NONE 269 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 237 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Hints) 238 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_0(Hints, 0xffffffff /*fFixedInsn*/, 0 /*fClass*/, 239 kDisArmV8OpcDecodeNop, 0xfe0, 5); 270 240 271 241 272 242 /* CLREX */ 273 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64DecBarriers)243 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DecBarriers) 274 244 DIS_ARMV8_OP(0xd503304f, "clrex", OP_ARMV8_A64_CLREX, DISOPTYPE_HARMLESS), 275 245 DIS_ARMV8_OP(0xd50330bf, "dmb", OP_ARMV8_A64_DMB, DISOPTYPE_HARMLESS), 276 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(g_ArmV8A64DecBarriers, 0xfffff0ff /*fFixedInsn*/, 0 /*fClass*/, 277 kDisArmV8OpcDecodeNop, RT_BIT_32(5), 5, 278 kDisArmv8OpParmImm) 246 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DecBarriers) 279 247 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 8, 4, 0 /*idxParam*/), 280 DIS_ARMV8_INSN_PARAM_NONE, 281 DIS_ARMV8_INSN_PARAM_NONE, 282 DIS_ARMV8_INSN_PARAM_NONE, 283 DIS_ARMV8_INSN_PARAM_NONE 284 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 248 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(DecBarriers, 0xfffff0ff /*fFixedInsn*/, 0 /*fClass*/, 249 kDisArmV8OpcDecodeNop, RT_BIT_32(5), 5, 250 kDisArmv8OpParmImm); 285 251 286 252 287 253 /* Barrier instructions, we divide these instructions further based on the op2 field. */ 288 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN( g_ArmV8A64DecodeBarriers)254 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DecodeBarriers) 289 255 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 290 256 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DSB - Encoding */ 291 DIS_ARMV8_DECODE_MAP_ENTRY( g_ArmV8A64DecBarriers),/* CLREX */257 DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* CLREX */ 292 258 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo TCOMMIT */ 293 259 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DSB - Encoding */ 294 DIS_ARMV8_DECODE_MAP_ENTRY( g_ArmV8A64DecBarriers),/* DMB */260 DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* DMB */ 295 261 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo ISB */ 296 262 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /** @todo SB */ 297 DIS_ARMV8_DECODE_MAP_DEFINE_END( g_ArmV8A64DecodeBarriers, RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7), 5);263 DIS_ARMV8_DECODE_MAP_DEFINE_END(DecodeBarriers, RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7), 5); 298 264 299 265 300 266 /* MSR (and potentially CFINV,XAFLAG,AXFLAG) */ 301 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64PState) 302 DIS_ARMV8_OP(0xd503305f, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_PRIVILEGED), 303 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_2(g_ArmV8A64PState, 0xfffff0ff /*fFixedInsn*/, 0 /*fClass*/, 304 kDisArmV8OpcDecodeNop, 0, 0, 305 kDisArmv8OpParmImm, kDisArmv8OpParmNone) /** @todo */ 267 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(PState) 268 DIS_ARMV8_OP(0xd503305f, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_HARMLESS), 269 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(PState) 306 270 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParsePState, 0, 0, 0 /*idxParam*/), /* This is special for the MSR instruction. */ 307 271 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 8, 4, 1 /*idxParam*/), /* CRm field encodes the immediate value */ 308 DIS_ARMV8_INSN_PARAM_NONE, 309 DIS_ARMV8_INSN_PARAM_NONE, 310 DIS_ARMV8_INSN_PARAM_NONE 311 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 272 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(PState, 0xfffff0ff /*fFixedInsn*/, 0 /*fClass*/, 273 kDisArmV8OpcDecodeNop, 0, 0, 274 kDisArmv8OpParmImm, kDisArmv8OpParmNone); /** @todo */ 312 275 313 276 314 277 /* TSTART/TTEST */ 315 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64SysResult)278 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysResult) 316 279 DIS_ARMV8_OP(0xd5233060, "tstart", OP_ARMV8_A64_TSTART, DISOPTYPE_HARMLESS | DISOPTYPE_PRIVILEGED), /* FEAT_TME */ 317 280 DIS_ARMV8_OP(0xd5233160, "ttest", OP_ARMV8_A64_TTEST, DISOPTYPE_HARMLESS), /* FEAT_TME */ 318 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(g_ArmV8A64SysResult, 0xfffffffe /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT, 319 kDisArmV8OpcDecodeNop, RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11), 8, 320 kDisArmv8OpParmGpr) 321 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 322 DIS_ARMV8_INSN_PARAM_NONE, 323 DIS_ARMV8_INSN_PARAM_NONE, 324 DIS_ARMV8_INSN_PARAM_NONE, 325 DIS_ARMV8_INSN_PARAM_NONE 326 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 281 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysResult) 282 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 283 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(SysResult, 0xfffffffe /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT, 284 kDisArmV8OpcDecodeNop, RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11), 8, 285 kDisArmv8OpParmGpr); 327 286 328 287 329 288 /* SYS */ 330 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64Sys)289 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Sys) 331 290 DIS_ARMV8_OP(0xd5080000, "sys", OP_ARMV8_A64_SYS, DISOPTYPE_HARMLESS), 332 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_0(g_ArmV8A64Sys, 0xfff80000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT, 333 kDisArmV8OpcDecodeNop, 0, 0) /** @todo */ 291 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Sys) 334 292 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 16, 3, 0 /*idxParam*/), 335 293 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseCRnCRm, 8, 8, 1 /*idxParam*/), 336 294 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 3, 2 /*idxParam*/), 337 295 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 3 /*idxParam*/), 338 DIS_ARMV8_INSN_PARAM_NONE 339 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 296 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_0(Sys, 0xfff80000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT, 297 kDisArmV8OpcDecodeNop, 0, 0); /** @todo */ 340 298 341 299 342 300 /* SYSL */ 343 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64SysL)301 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysL) 344 302 DIS_ARMV8_OP(0xd5280000, "sysl", OP_ARMV8_A64_SYSL, DISOPTYPE_HARMLESS), 345 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_0(g_ArmV8A64SysL, 0xfff80000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT, 346 kDisArmV8OpcDecodeNop, 0, 0) /** @todo */ 303 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysL) 347 304 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 348 305 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 16, 3, 1 /*idxParam*/), 349 306 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseCRnCRm, 8, 8, 2 /*idxParam*/), 350 307 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 3, 3 /*idxParam*/), 351 DIS_ARMV8_INSN_PARAM_NONE 352 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 308 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_0(SysL, 0xfff80000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT, 309 kDisArmV8OpcDecodeNop, 0, 0); /** @todo */ 353 310 354 311 355 312 /* MSR */ 356 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64Msr)313 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Msr) 357 314 DIS_ARMV8_OP(0xd5100000, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_HARMLESS | DISOPTYPE_PRIVILEGED), 358 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_2(g_ArmV8A64Msr, 0xfff00000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT, 359 kDisArmV8OpcDecodeNop, 0, 0, 360 kDisArmv8OpParmSysReg, kDisArmv8OpParmGpr) 315 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Msr) 361 316 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseSysReg, 5, 15, 0 /*idxParam*/), 362 317 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 1 /*idxParam*/), 363 DIS_ARMV8_INSN_PARAM_NONE, 364 DIS_ARMV8_INSN_PARAM_NONE, 365 DIS_ARMV8_INSN_PARAM_NONE 366 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 318 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(Msr, 0xfff00000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT, 319 kDisArmV8OpcDecodeNop, 0, 0, 320 kDisArmv8OpParmSysReg, kDisArmv8OpParmGpr); 367 321 368 322 369 323 /* MRS */ 370 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64Mrs)324 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Mrs) 371 325 DIS_ARMV8_OP(0xd5300000, "mrs", OP_ARMV8_A64_MRS, DISOPTYPE_HARMLESS | DISOPTYPE_PRIVILEGED), 372 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_2(g_ArmV8A64Mrs, 0xfff00000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT, 373 kDisArmV8OpcDecodeNop, 0, 0, 374 kDisArmv8OpParmGpr, kDisArmv8OpParmSysReg) 326 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Mrs) 375 327 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 376 328 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseSysReg, 5, 15, 1 /*idxParam*/), 377 DIS_ARMV8_INSN_PARAM_NONE, 378 DIS_ARMV8_INSN_PARAM_NONE, 379 DIS_ARMV8_INSN_PARAM_NONE 380 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 329 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(Mrs, 0xfff00000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT, 330 kDisArmV8OpcDecodeNop, 0, 0, 331 kDisArmv8OpParmGpr, kDisArmv8OpParmSysReg); 381 332 382 333 383 334 /* BR/BRAA/BRAAZ/BRAB/BRABZ/BLR/BLRAA/BLRAAZ/BLRAB/BLRABZ/RET/RETAA/RETAB */ 384 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64BrBlrRet)335 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(BrBlrRet) 385 336 DIS_ARMV8_OP(0xd61f0000, "br", OP_ARMV8_A64_BR, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 386 337 DIS_ARMV8_OP(0xd63f0000, "blr", OP_ARMV8_A64_BLR, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), … … 389 340 DIS_ARMV8_OP(0xd65f0800, "retaa", OP_ARMV8_A64_RETAA, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 390 341 DIS_ARMV8_OP(0xd65f0c00, "retab", OP_ARMV8_A64_RETAB, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 391 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(g_ArmV8A64BrBlrRet, 0xfffffc1f /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT, 392 kDisArmV8OpcDecodeLookup, 0xfffffc1f, 0, 393 kDisArmv8OpParmGpr) 342 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(BrBlrRet) 394 343 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5, 0 /*idxParam*/), 395 DIS_ARMV8_INSN_PARAM_NONE, 396 DIS_ARMV8_INSN_PARAM_NONE, 397 DIS_ARMV8_INSN_PARAM_NONE, 398 DIS_ARMV8_INSN_PARAM_NONE 399 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 344 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(BrBlrRet, 0xfffffc1f /*fFixedInsn*/, DISARMV8INSNCLASS_F_FORCED_64BIT, 345 kDisArmV8OpcDecodeLookup, 0xfffffc1f, 0, 346 kDisArmv8OpParmGpr); 400 347 401 348 402 349 /* Unconditional branch (register) instructions, we divide these instructions further based on the opc field. */ 403 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN( g_ArmV8A64UncondBrReg)404 DIS_ARMV8_DECODE_MAP_ENTRY( g_ArmV8A64BrBlrRet), /* BR/BRAA/BRAAZ/BRAB/BRABZ */405 DIS_ARMV8_DECODE_MAP_ENTRY( g_ArmV8A64BrBlrRet), /* BLR/BLRAA/BLRAAZ/BLRAB/BLRABZ */406 DIS_ARMV8_DECODE_MAP_ENTRY( g_ArmV8A64BrBlrRet), /* RET/RETAA/RETAB */350 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(UncondBrReg) 351 DIS_ARMV8_DECODE_MAP_ENTRY(BrBlrRet), /* BR/BRAA/BRAAZ/BRAB/BRABZ */ 352 DIS_ARMV8_DECODE_MAP_ENTRY(BrBlrRet), /* BLR/BLRAA/BLRAAZ/BLRAB/BLRABZ */ 353 DIS_ARMV8_DECODE_MAP_ENTRY(BrBlrRet), /* RET/RETAA/RETAB */ 407 354 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 408 355 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, … … 418 365 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 419 366 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY 420 DIS_ARMV8_DECODE_MAP_DEFINE_END( g_ArmV8A64UncondBrReg, RT_BIT_32(21) | RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24), 21);367 DIS_ARMV8_DECODE_MAP_DEFINE_END(UncondBrReg, RT_BIT_32(21) | RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24), 21); 421 368 422 369 423 370 /* B/BL */ 424 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64UncondBrImm)371 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(UncondBrImm) 425 372 DIS_ARMV8_OP(0x14000000, "b", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 426 373 DIS_ARMV8_OP(0x94000000, "bl", OP_ARMV8_A64_BL, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 427 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(g_ArmV8A64UncondBrImm, 0xfc000000 /*fFixedInsn*/, 0 /*fClass*/, 428 kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31, 429 kDisArmv8OpParmImmRel) 374 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(UncondBrImm) 430 375 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 0, 26, 0 /*idxParam*/), 431 DIS_ARMV8_INSN_PARAM_NONE, 432 DIS_ARMV8_INSN_PARAM_NONE, 433 DIS_ARMV8_INSN_PARAM_NONE, 434 DIS_ARMV8_INSN_PARAM_NONE 435 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 376 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_1(UncondBrImm, 0xfc000000 /*fFixedInsn*/, 0 /*fClass*/, 377 kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31, 378 kDisArmv8OpParmImmRel); 436 379 437 380 438 381 /* CBZ/CBNZ */ 439 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64CmpBrImm)382 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CmpBrImm) 440 383 DIS_ARMV8_OP(0x34000000, "cbz", OP_ARMV8_A64_CBZ, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 441 384 DIS_ARMV8_OP(0x35000000, "cbnz", OP_ARMV8_A64_CBNZ, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 442 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_2(g_ArmV8A64CmpBrImm, 0x7f000000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF, 443 kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24, 444 kDisArmv8OpParmGpr, kDisArmv8OpParmImmRel) 385 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CmpBrImm) 445 386 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 446 387 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 5, 19, 1 /*idxParam*/), 447 DIS_ARMV8_INSN_PARAM_NONE, 448 DIS_ARMV8_INSN_PARAM_NONE, 449 DIS_ARMV8_INSN_PARAM_NONE 450 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 388 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(CmpBrImm, 0x7f000000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF, 389 kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24, 390 kDisArmv8OpParmGpr, kDisArmv8OpParmImmRel); 451 391 452 392 453 393 /* TBZ/TBNZ */ 454 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_ArmV8A64TestBrImm)394 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(TestBrImm) 455 395 DIS_ARMV8_OP(0x36000000, "tbz", OP_ARMV8_A64_TBZ, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 456 396 DIS_ARMV8_OP(0x37000000, "tbnz", OP_ARMV8_A64_TBNZ, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 457 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_3(g_ArmV8A64TestBrImm, 0x7f000000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF, /* Not an SF bit but has the same meaning. */ 458 kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24, 459 kDisArmv8OpParmGpr, kDisArmv8OpParmImm, kDisArmv8OpParmImmRel) 397 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(TestBrImm) 460 398 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 461 399 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmTbz, 0, 0, 1 /*idxParam*/), /* Hardcoded bit offsets in parser. */ 462 400 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 5, 14, 2 /*idxParam*/), 463 DIS_ARMV8_INSN_PARAM_NONE, 464 DIS_ARMV8_INSN_PARAM_NONE465 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;466 467 468 DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN( g_ArmV8A64BrExcpSys)469 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe000000, RT_BIT_32(26) | RT_BIT_32(28) | RT_BIT_32(30), g_ArmV8A64CondBr), /* op0: 010, op1: 0xxxxxxxxxxxxx, op2: - (including o1 from the conditional branch (immediate) class to save us one layer). */470 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xff000000, RT_BIT_32(26) | RT_BIT_32(28) | RT_BIT_32(30) | RT_BIT_32(31), g_ArmV8A64Excp), /* op0: 110, op1: 00xxxxxxxxxxxx, op2: -. */471 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff000, 0xd5031000, g_ArmV8A64SysReg), /* op0: 110, op1: 01000000110001, op2: -. */472 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503201f, g_ArmV8A64Hints), /* op0: 110, op1: 01000000110010, op2: 11111. */473 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503301f, g_ArmV8A64DecodeBarriers), /* op0: 110, op1: 01000000110011, op2: - (we include Rt: 11111 from the next stage here). */474 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff8f01f, 0xd500401f, g_ArmV8A64PState), /* op0: 110, op1: 0100000xxx0100, op2: - (we include Rt: 11111 from the next stage here). */475 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff0e0, 0xd5233060, g_ArmV8A64SysResult), /* op0: 110, op1: 0100100xxxxxxx, op2: - (we include op1, CRn and op2 from the next stage here). */476 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5080000, g_ArmV8A64Sys), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */477 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5280000, g_ArmV8A64SysL), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */478 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5100000, g_ArmV8A64Msr), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */479 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5300000, g_ArmV8A64Mrs), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */480 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe1f0000, 0xd61f0000, g_ArmV8A64UncondBrReg), /* op0: 110, op1: 1xxxxxxxxxxxxx, op2: - (we include the op2 field from the next stage here as it should be always 11111). */481 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7c000000, 0x14000000, g_ArmV8A64UncondBrImm), /* op0: x00, op1: xxxxxxxxxxxxxx, op2: -. */482 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x34000000, g_ArmV8A64CmpBrImm), /* op0: x01, op1: 0xxxxxxxxxxxxx, op2: -. */483 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x36000000, g_ArmV8A64TestBrImm), /* op0: x01, op1: 1xxxxxxxxxxxxx, op2: -. */484 DIS_ARMV8_DECODE_TBL_DEFINE_END( g_ArmV8A64BrExcpSys);401 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(TestBrImm, 0x7f000000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF, /* Not an SF bit but has the same meaning. */ 402 kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24, 403 kDisArmv8OpParmGpr, kDisArmv8OpParmImm, kDisArmv8OpParmImmRel); 404 405 406 DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(BrExcpSys) 407 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe000000, RT_BIT_32(26) | RT_BIT_32(28) | RT_BIT_32(30), CondBr), /* op0: 010, op1: 0xxxxxxxxxxxxx, op2: - (including o1 from the conditional branch (immediate) class to save us one layer). */ 408 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xff000000, RT_BIT_32(26) | RT_BIT_32(28) | RT_BIT_32(30) | RT_BIT_32(31), Excp), /* op0: 110, op1: 00xxxxxxxxxxxx, op2: -. */ 409 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff000, 0xd5031000, SysReg), /* op0: 110, op1: 01000000110001, op2: -. */ 410 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503201f, Hints), /* op0: 110, op1: 01000000110010, op2: 11111. */ 411 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503301f, DecodeBarriers), /* op0: 110, op1: 01000000110011, op2: - (we include Rt: 11111 from the next stage here). */ 412 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff8f01f, 0xd500401f, PState), /* op0: 110, op1: 0100000xxx0100, op2: - (we include Rt: 11111 from the next stage here). */ 413 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff0e0, 0xd5233060, SysResult), /* op0: 110, op1: 0100100xxxxxxx, op2: - (we include op1, CRn and op2 from the next stage here). */ 414 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5080000, Sys), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */ 415 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5280000, SysL), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */ 416 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5100000, Msr), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */ 417 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5300000, Mrs), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */ 418 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe1f0000, 0xd61f0000, UncondBrReg), /* op0: 110, op1: 1xxxxxxxxxxxxx, op2: - (we include the op2 field from the next stage here as it should be always 11111). */ 419 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7c000000, 0x14000000, UncondBrImm), /* op0: x00, op1: xxxxxxxxxxxxxx, op2: -. */ 420 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x34000000, CmpBrImm), /* op0: x01, op1: 0xxxxxxxxxxxxx, op2: -. */ 421 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x36000000, TestBrImm), /* op0: x01, op1: 1xxxxxxxxxxxxx, op2: -. */ 422 DIS_ARMV8_DECODE_TBL_DEFINE_END(BrExcpSys); 485 423 486 424 487 425 /* AND/ORR/EOR/ANDS */ 488 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_aArmV8A64InsnLogShiftRegN0)426 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogShiftRegN0) 489 427 DIS_ARMV8_OP(0x0a000000, "and", OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS), 490 428 DIS_ARMV8_OP(0x2a000000, "orr", OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS), 491 429 DIS_ARMV8_OP(0x4a000000, "eor", OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS), 492 430 DIS_ARMV8_OP(0x6a000000, "ands", OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS) 493 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_3(g_aArmV8A64InsnLogShiftRegN0, 0x7f200000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF, 494 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 495 kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmGpr) 431 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogShiftRegN0) 496 432 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 497 433 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5, 1 /*idxParam*/), … … 499 435 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseShift, 22, 2, 2 /*idxParam*/), 500 436 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseShiftAmount, 10, 6, 2 /*idxParam*/), 501 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 437 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(LogShiftRegN0, 0x7f200000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF, 438 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 439 kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmGpr); 502 440 503 441 504 442 /* AND/ORR/EOR/ANDS */ 505 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN( g_aArmV8A64InsnLogShiftRegN1)443 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogShiftRegN1) 506 444 DIS_ARMV8_OP(0x0a200000, "bic", OP_ARMV8_A64_BIC, DISOPTYPE_HARMLESS), 507 445 DIS_ARMV8_OP(0x2a200000, "orn", OP_ARMV8_A64_ORN, DISOPTYPE_HARMLESS), 508 446 DIS_ARMV8_OP(0x4a200000, "eon", OP_ARMV8_A64_EON, DISOPTYPE_HARMLESS), 509 447 DIS_ARMV8_OP(0x6a200000, "bics", OP_ARMV8_A64_BICS, DISOPTYPE_HARMLESS) 510 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_3(g_aArmV8A64InsnLogShiftRegN1, 0x7f200000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF, 511 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 512 kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmGpr) 448 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogShiftRegN1) 513 449 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 514 450 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5, 1 /*idxParam*/), … … 516 452 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseShift, 22, 2, 2 /*idxParam*/), 517 453 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseShiftAmount, 10, 6, 2 /*idxParam*/), 518 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 519 520 521 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_aArmV8A64InsnLogShiftRegN) 522 DIS_ARMV8_DECODE_MAP_ENTRY(g_aArmV8A64InsnLogShiftRegN0), /* Logical (shifted register) - N = 0 */ 523 DIS_ARMV8_DECODE_MAP_ENTRY(g_aArmV8A64InsnLogShiftRegN1), /* Logical (shifted register) - N = 1 */ 524 DIS_ARMV8_DECODE_MAP_DEFINE_END(g_aArmV8A64InsnLogShiftRegN, RT_BIT_32(21), 21); 525 526 527 528 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_aArmV8A64InsnAddSubExtReg) 529 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 530 DIS_ARMV8_DECODE_MAP_DEFINE_END(g_aArmV8A64InsnAddSubExtReg, RT_BIT_32(24), 24); 531 532 533 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_aArmV8A64InsnAddSubShiftExtReg) 534 DIS_ARMV8_DECODE_MAP_ENTRY(g_aArmV8A64InsnAddSubShiftReg), /* Add/Subtract (shifted register) */ 535 DIS_ARMV8_DECODE_MAP_ENTRY(g_aArmV8A64InsnAddSubExtReg), /* Add/Subtract (extended register) */ 536 DIS_ARMV8_DECODE_MAP_DEFINE_END(g_aArmV8A64InsnAddSubShiftExtReg, RT_BIT_32(21), 21); 537 538 539 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_ArmV8A64LogicalAddSubReg) 540 DIS_ARMV8_DECODE_MAP_ENTRY(g_aArmV8A64InsnLogShiftRegN), /* Logical (shifted register) */ 541 DIS_ARMV8_DECODE_MAP_ENTRY(g_aArmV8A64InsnAddSubShiftExtReg), /* Add/subtract (shifted/extended register) */ 542 DIS_ARMV8_DECODE_MAP_DEFINE_END(g_ArmV8A64LogicalAddSubReg, RT_BIT_32(24), 24); 543 544 545 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_ArmV8A64DataProcReg) 546 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 547 DIS_ARMV8_DECODE_MAP_DEFINE_END(g_ArmV8A64DataProcReg, RT_BIT_32(24), 24); 548 549 550 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64LdSt) 454 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(LogShiftRegN1, 0x7f200000 /*fFixedInsn*/, DISARMV8INSNCLASS_F_SF, 455 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 456 kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmGpr); 457 458 459 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LogShiftRegN) 460 DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN0), /* Logical (shifted register) - N = 0 */ 461 DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN1), /* Logical (shifted register) - N = 1 */ 462 DIS_ARMV8_DECODE_MAP_DEFINE_END(LogShiftRegN, RT_BIT_32(21), 21); 463 464 465 466 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(AddSubExtReg) 467 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */ 468 DIS_ARMV8_DECODE_MAP_DEFINE_END(AddSubExtReg, RT_BIT_32(24), 24); 469 470 471 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(AddSubShiftExtReg) 472 DIS_ARMV8_DECODE_MAP_ENTRY(AddSubShiftReg), /* Add/Subtract (shifted register) */ 473 DIS_ARMV8_DECODE_MAP_ENTRY(AddSubExtReg), /* Add/Subtract (extended register) */ 474 DIS_ARMV8_DECODE_MAP_DEFINE_END(AddSubShiftExtReg, RT_BIT_32(21), 21); 475 476 477 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LogicalAddSubReg) 478 DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN), /* Logical (shifted register) */ 479 DIS_ARMV8_DECODE_MAP_ENTRY(AddSubShiftExtReg), /* Add/subtract (shifted/extended register) */ 480 DIS_ARMV8_DECODE_MAP_DEFINE_END(LogicalAddSubReg, RT_BIT_32(24), 24); 481 482 483 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcReg) 484 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 485 DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcReg, RT_BIT_32(24), 24); 486 487 488 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdSt) 551 489 DIS_ARMV8_OP(0xb9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS), 552 490 DIS_ARMV8_OP(0xb9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS), 553 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_2(g_ArmV8A64LdSt, 0xbfc00000 /*fFixedInsn*/, 0 /*fClass*/, 554 kDisArmV8OpcDecodeLookup, 0xbfc00000, 0, 555 kDisArmv8OpParmGpr, kDisArmv8OpParmAddrInGpr) 491 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdSt) 556 492 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseIs32Bit, 30, 1, DIS_ARMV8_INSN_PARAM_UNSET), 557 493 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 558 494 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5, 1 /*idxParam*/), 559 495 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmMemOff, 10, 12, 1 /*idxParam*/), 560 DIS_ARMV8_INSN_PARAM_NONE 561 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 562 496 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(LdSt, 0xbfc00000 /*fFixedInsn*/, 0 /*fClass*/, 497 kDisArmV8OpcDecodeLookup, 0xbfc00000, 0, 498 kDisArmv8OpParmGpr, kDisArmv8OpParmAddrInGpr); 563 499 564 500 /* … … 600 536 * 15 1 1 1 1 Data processing - SIMD and floating point 601 537 */ 602 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN( g_ArmV8A64DecodeL0)603 DIS_ARMV8_DECODE_MAP_ENTRY( g_aArmV8A64InsnRsvd),/* Reserved class or SME encoding (@todo). */538 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DecodeL0) 539 DIS_ARMV8_DECODE_MAP_ENTRY(Rsvd), /* Reserved class or SME encoding (@todo). */ 604 540 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */ 605 541 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo SVE */ 606 542 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */ 607 543 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Load/Stores */ 608 DIS_ARMV8_DECODE_MAP_ENTRY( g_ArmV8A64LogicalAddSubReg),/* Data processing (register) (see op1 in C4.1.68). */544 DIS_ARMV8_DECODE_MAP_ENTRY(LogicalAddSubReg), /* Data processing (register) (see op1 in C4.1.68). */ 609 545 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Load/Stores */ 610 546 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Data processing (SIMD & FP) */ 611 DIS_ARMV8_DECODE_MAP_ENTRY( g_aArmV8A64InsnDataProcessingImm),/* Data processing (immediate). */612 DIS_ARMV8_DECODE_MAP_ENTRY( g_aArmV8A64InsnDataProcessingImm),/* Data processing (immediate). */613 DIS_ARMV8_DECODE_MAP_ENTRY( g_ArmV8A64BrExcpSys),/* Branches / Exception generation and system instructions. */614 DIS_ARMV8_DECODE_MAP_ENTRY( g_ArmV8A64BrExcpSys),/* Branches / Exception generation and system instructions. */615 DIS_ARMV8_DECODE_MAP_ENTRY( g_ArmV8A64LdSt),/* Load/Stores. */616 DIS_ARMV8_DECODE_MAP_ENTRY( g_ArmV8A64DataProcReg),/* Data processing (register) (see op1 in C4.1.68). */547 DIS_ARMV8_DECODE_MAP_ENTRY(DataProcessingImm), /* Data processing (immediate). */ 548 DIS_ARMV8_DECODE_MAP_ENTRY(DataProcessingImm), /* Data processing (immediate). */ 549 DIS_ARMV8_DECODE_MAP_ENTRY(BrExcpSys), /* Branches / Exception generation and system instructions. */ 550 DIS_ARMV8_DECODE_MAP_ENTRY(BrExcpSys), /* Branches / Exception generation and system instructions. */ 551 DIS_ARMV8_DECODE_MAP_ENTRY(LdSt), /* Load/Stores. */ 552 DIS_ARMV8_DECODE_MAP_ENTRY(DataProcReg), /* Data processing (register) (see op1 in C4.1.68). */ 617 553 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Load/Stores. */ 618 554 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /* Data processing (SIMD & FP). */ 619 DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC( g_ArmV8A64DecodeL0, RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28), 25);555 DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(DecodeL0, RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28), 25);
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