Changeset 104173 in vbox
- Timestamp:
- Apr 5, 2024 9:38:49 AM (6 months ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 3 edited
-
VMMAll/IEMAllAImpl-arm64.S (modified) (2 diffs)
-
VMMAll/IEMAllAImplC.cpp (modified) (19 diffs)
-
testcase/tstIEMAImpl.cpp (modified) (6 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/VMM/VMMAll/IEMAllAImpl-arm64.S
r103003 r104173 44 44 #endif 45 45 46 .macro BEGINPROC, a_Name 47 .private_extern NAME(\a_Name) 48 .globl NAME(\a_Name) 49 NAME(\a_Name): 50 .endm 51 52 53 .macro CALC_EFLAGS_PARITY, regEfl, regResult, regTmp 54 /* 55 * Parity calculation for low byte of the result (sucks that there is no popcount for gprs). 56 */ 57 eor \regTmp, \regResult, \regResult, LSR #4 58 eor \regTmp, \regTmp, \regTmp, LSR #2 59 eor \regTmp, \regTmp, \regTmp, LSR #1 60 eor \regTmp, \regTmp, #1 61 bfi \regEfl, \regTmp, #X86_EFL_PF_BIT, #1 /* PF(2) = popcount(w9 & 0xff) & 1 ^ 1 */ 62 .endm 63 64 65 .macro CALC_EFLAGS_AUX_CARRY, regEfl, regResult, regLeft, regRight, regTmp 66 /* 67 * Auxilary carry / borrow flag. This is related to 8-bit BCD. 68 */ 69 eor \regTmp, \regLeft, \regRight 70 eor \regTmp, \regTmp, \regResult 71 lsr \regTmp, \regTmp, #X86_EFL_AF_BIT 72 bfi \regEfl, \regTmp, #X86_EFL_AF_BIT, #1 /* AF(4) = (w8 ^ w1 ^ w9 & X86_EFL_AF) >> X86_EFL_AF_BIT */ 73 .endm 46 74 47 75 .macro CALC_EFLAGS, regEfl, regResult, regLeft, regRight, regTmp, fSkipFlags=0 … … 311 339 ret 312 340 .cfi_endproc 341 342 343 344 /* 345 * Shift Left. 346 */ 347 348 /* void iemAImpl_shl_u8(uint8_t *pu8Dst, uint8_t cShift, uint32_t *pEFlags); */ 349 /* void iemAImpl_shl_u16(uint16_t *pu16Dst, uint8_t cShift, uint32_t *pEFlags); */ 350 /* void iemAImpl_shl_u32(uint16_t *pu32Dst, uint8_t cShift, uint32_t *pEFlags); */ 351 .macro SHL_8_16_32, a_Name, a_cBits, a_fIntelFlags, a_LdStSuff 352 .p2align 2 353 BEGINPROC \a_Name 354 .cfi_startproc 355 356 /* Do we need to shift anything at all? */ 357 and w1, w1, #0x1f 358 cbz w1, 99f 359 360 /* 361 * Do the shifting 362 */ 363 ldr\a_LdStSuff w8, [x0] 364 .ifne \a_cBits < 32 365 lslv w9, w8, w1 366 .else 367 lslv x9, x8, x1 /* use 64-bit registers here so we get CF for free. We know x1 != 0. */ 368 .endif 369 str\a_LdStSuff w9, [x0] 370 371 /* 372 * Calculate EFLAGS. 373 */ 374 ldr w10, [x2] /* w10 = eflags; CF=0 PF=2 AF=4 ZF=6 SF=7 OF=11 */ 375 376 CALC_EFLAGS_PARITY w10, w9, w12 377 378 .ifne \a_cBits < 32 379 setf\a_cBits w9 /* Sets NZ */ 380 .else 381 ands wzr, w9, w9 /* Sets NZ */ 382 .endif 383 #if 1 384 mrs x11, NZCV 385 lsr w11, w11, #30 /* N=1; Z=0 */ 386 bfi w10, w11, X86_EFL_ZF_BIT, 2 /* EFLAGS.ZF and EFLAGS.SF */ 387 #else 388 cset x11, eq 389 bfi w10, w11, X86_EFL_ZF_BIT, 1 390 cset x12, pl 391 bfi w10, w12, X86_EFL_SF_BIT, 1 392 #endif 393 394 .ifne \a_cBits < 32 395 bfxil w10, w9, #\a_cBits, #1 /* w9 bit 8/16 contains carry. (X86_EFL_CF_BIT == 0) */ 396 .else 397 bfxil x10, x9, #\a_cBits, #1 /* x9 bit 32 contains carry. (X86_EFL_CF_BIT == 0) */ 398 .endif 399 400 .ifne \a_fIntelFlags 401 /* Intel: OF = first bit shifted: fEfl |= X86_EFL_GET_OF_ ## cOpBits(uDst ^ (uDst << 1)); */ 402 eor w11, w8, w8, LSL #1 403 lsr w11, w11, #(\a_cBits - 1) 404 bfi w10, w11, #X86_EFL_OF_BIT, #1 405 406 and w10, w10, ~X86_EFL_AF /* AF is cleared */ 407 .else 408 /* AMD: OF = last bit shifted: fEfl |= ((uResult >> (cOpBits - 1)) ^ fCarry) << X86_EFL_OF_BIT; */ 409 .ifne \a_cBits < 32 410 eor w11, w9, w9, LSR #1 411 lsr w11, w11, #(\a_cBits - 1) 412 .else 413 eor x11, x9, x9, LSR #1 414 lsr x11, x11, #(\a_cBits - 1) 415 .endif 416 bfi w10, w11, #X86_EFL_OF_BIT, #1 417 418 orr w10, w10, X86_EFL_AF /* AF is set */ 419 .endif 420 421 str w10, [x2] 422 99: 423 ret 424 .cfi_endproc 425 .endm 426 427 SHL_8_16_32 iemAImpl_shl_u8, 8, 1, b 428 SHL_8_16_32 iemAImpl_shl_u8_intel, 8, 1, b 429 SHL_8_16_32 iemAImpl_shl_u8_amd, 8, 0, b 430 431 SHL_8_16_32 iemAImpl_shl_u16, 16, 1, h 432 SHL_8_16_32 iemAImpl_shl_u16_intel, 16, 1, h 433 SHL_8_16_32 iemAImpl_shl_u16_amd, 16, 0, h 434 435 SHL_8_16_32 iemAImpl_shl_u32, 32, 1, 436 SHL_8_16_32 iemAImpl_shl_u32_intel, 32, 1, 437 SHL_8_16_32 iemAImpl_shl_u32_amd, 32, 0, 438 439 ;; @todo this is slightly slower than the C version (release) on an M2. Investigate why. 440 /* void iemAImpl_shl_u64(uint16_t *pu64Dst, uint8_t cShift, uint32_t *pEFlags); */ 441 .macro SHL_64, a_Name, a_fIntelFlags 442 .p2align 2 443 BEGINPROC \a_Name 444 .cfi_startproc 445 446 /* Do we need to shift anything at all? */ 447 and w1, w1, #0x3f 448 cbz w1, 99f 449 450 /* 451 * Do the shifting 452 */ 453 ldr x8, [x0] 454 lslv x9, x8, x1 455 str x9, [x0] 456 457 /* 458 * Calculate EFLAGS. 459 */ 460 ldr w10, [x2] /* w10 = eflags; CF=0 PF=2 AF=4 ZF=6 SF=7 OF=11 */ 461 462 CALC_EFLAGS_PARITY w10, w9, w11 463 464 ands xzr, x9, x9 /* Sets NZ */ 465 mrs x11, NZCV 466 lsr w11, w11, #30 /* N=1; Z=0 */ 467 bfi w10, w11, X86_EFL_ZF_BIT, 2 /* EFLAGS.ZF and EFLAGS.SF */ 468 469 neg w11, w1 /* the shift count is MODed by the data size, so this is safe. */ 470 lsrv x11, x8, x11 471 bfi w10, w11, X86_EFL_CF_BIT, 1 472 473 .ifne \a_fIntelFlags 474 /* Intel: OF = first bit shifted: fEfl |= X86_EFL_GET_OF_ ## cOpBits(uDst ^ (uDst << 1)); */ 475 eor x11, x8, x8, LSL #1 476 lsr x11, x11, #63 477 bfi w10, w11, #X86_EFL_OF_BIT, #1 478 479 and w10, w10, ~X86_EFL_AF /* AF is cleared */ 480 .else 481 /* AMD: OF = last bit shifted: fEfl |= ((uResult >> (cOpBits - 1)) ^ fCarry) << X86_EFL_OF_BIT; */ 482 eor x11, x11, x9, LSR #63 /* w11[0]=CF from above */ 483 bfi w10, w11, #X86_EFL_OF_BIT, #1 484 485 orr w10, w10, X86_EFL_AF /* AF is set */ 486 .endif 487 str w10, [x2] 488 99: 489 ret 490 .cfi_endproc 491 .endm 492 493 SHL_64 iemAImpl_shl_u64, 1 494 SHL_64 iemAImpl_shl_u64_intel, 1 495 SHL_64 iemAImpl_shl_u64_amd, 0 496 497 498 /* 499 * Shift Right, Unsigned. 500 */ 501 502 /* void iemAImpl_shr_u8(uint8_t *pu8Dst, uint8_t cShift, uint32_t *pEFlags); */ 503 /* void iemAImpl_shr_u16(uint16_t *pu16Dst, uint8_t cShift, uint32_t *pEFlags); */ 504 /* void iemAImpl_shr_u32(uint16_t *pu32Dst, uint8_t cShift, uint32_t *pEFlags); */ 505 .macro shr_8_16_32, a_Name, a_cBits, a_fIntelFlags, a_LdStSuff 506 .p2align 2 507 BEGINPROC \a_Name 508 .cfi_startproc 509 510 /* Do we need to shift anything at all? */ 511 and w1, w1, #0x1f 512 cbz w1, 99f 513 514 /* Load EFLAGS before we start the calculation. */ 515 ldr w10, [x2] /* w10 = eflags; CF=0 PF=2 AF=4 ZF=6 SF=7 OF=11 */ 516 517 /* 518 * Do the shifting. 519 */ 520 ldr\a_LdStSuff w8, [x0] 521 lsrv w9, w8, w1 522 str\a_LdStSuff w9, [x0] 523 524 /* 525 * Calculate EFLAGS. 526 */ 527 sub w11, w1, #1 528 lsrv w11, w8, w11 529 bfxil w10, w11, #X86_EFL_CF_BIT, #1 530 531 .ifne \a_fIntelFlags 532 and w10, w10, ~X86_EFL_AF /* AF is cleared */ 533 /* Intel: OF = one bit shift: fEfl |= X86_EFL_GET_OF_ ## cOpBits(uDstIn); */ 534 lsr w11, w8, #(\a_cBits - 1) 535 bfi w10, w11, #X86_EFL_OF_BIT, #1 536 .else 537 orr w10, w10, X86_EFL_AF /* AF is set */ 538 /* AMD: OF = last bits shifted: fEfl |= (uResult >> (cOpBits - 2)) << X86_EFL_OF_BIT; */ 539 lsr w11, w9, #(\a_cBits - 2) 540 bfi w10, w11, #X86_EFL_OF_BIT, #1 541 .endif 542 543 CALC_EFLAGS_PARITY w10, w9, w11 544 545 .ifne \a_cBits < 32 546 setf\a_cBits w9 /* Sets NZ */ 547 .else 548 ands wzr, w9, w9 /* Sets NZ */ 549 .endif 550 mrs x11, NZCV 551 lsr w11, w11, #30 /* N=1; Z=0 */ 552 bfi w10, w11, X86_EFL_ZF_BIT, 2 /* EFLAGS.ZF and EFLAGS.SF */ 553 554 str w10, [x2] 555 99: 556 ret 557 .cfi_endproc 558 .endm 559 560 shr_8_16_32 iemAImpl_shr_u8, 8, 1, b 561 shr_8_16_32 iemAImpl_shr_u8_intel, 8, 1, b 562 shr_8_16_32 iemAImpl_shr_u8_amd, 8, 0, b 563 564 shr_8_16_32 iemAImpl_shr_u16, 16, 1, h 565 shr_8_16_32 iemAImpl_shr_u16_intel, 16, 1, h 566 shr_8_16_32 iemAImpl_shr_u16_amd, 16, 0, h 567 568 shr_8_16_32 iemAImpl_shr_u32, 32, 1, 569 shr_8_16_32 iemAImpl_shr_u32_intel, 32, 1, 570 shr_8_16_32 iemAImpl_shr_u32_amd, 32, 0, 571 572 ;; @todo this is slightly slower than the C version (release) on an M2. Investigate why. 573 /* void iemAImpl_shr_u64(uint16_t *pu64Dst, uint8_t cShift, uint32_t *pEFlags); */ 574 .macro shr_64, a_Name, a_fIntelFlags 575 .p2align 2 576 BEGINPROC \a_Name 577 .cfi_startproc 578 579 /* Do we need to shift anything at all? */ 580 ands w1, w1, #0x3f 581 b.eq 99f 582 583 /* Load EFLAGS before we start the calculation. */ 584 ldr w10, [x2] /* w10 = eflags; CF=0 PF=2 AF=4 ZF=6 SF=7 OF=11 */ 585 586 /* 587 * Do the shifting 588 */ 589 ldr x8, [x0] 590 lsrv x9, x8, x1 591 str x9, [x0] 592 593 /* 594 * Calculate EFLAGS. 595 */ 596 sub w11, w1, #1 597 lsrv x11, x8, x11 598 bfxil w10, w11, #X86_EFL_CF_BIT, #1 599 600 .ifne \a_fIntelFlags 601 and w10, w10, ~X86_EFL_AF /* AF is cleared */ 602 /* Intel: OF = one bit shift: fEfl |= X86_EFL_GET_OF_ ## cOpBits(uDstIn); */ 603 lsr x11, x8, #63 604 bfi w10, w11, #X86_EFL_OF_BIT, #1 605 .else 606 orr w10, w10, X86_EFL_AF /* AF is set */ 607 /* AMD: OF = last bits shifted: fEfl |= (uResult >> (cOpBits - 2)) << X86_EFL_OF_BIT; */ 608 lsr x11, x9, #62 609 bfi w10, w11, #X86_EFL_OF_BIT, #1 610 .endif 611 612 CALC_EFLAGS_PARITY w10, w9, w11 613 614 ands xzr, x9, x9 /* Sets NZ */ 615 mrs x11, NZCV 616 lsr w11, w11, #30 /* N=1; Z=0 */ 617 bfi w10, w11, X86_EFL_ZF_BIT, 2 /* EFLAGS.ZF and EFLAGS.SF */ 618 619 str w10, [x2] 620 99: 621 ret 622 .cfi_endproc 623 .endm 624 625 shr_64 iemAImpl_shr_u64, 1 626 shr_64 iemAImpl_shr_u64_intel, 1 627 shr_64 iemAImpl_shr_u64_amd, 0 628 629 630 /* 631 * Shift Right, Signed 632 */ 633 634 /* void iemAImpl_sar_u8(uint8_t *pu8Dst, uint8_t cShift, uint32_t *pEFlags); */ 635 /* void iemAImpl_sar_u16(uint16_t *pu16Dst, uint8_t cShift, uint32_t *pEFlags); */ 636 /* void iemAImpl_sar_u32(uint16_t *pu32Dst, uint8_t cShift, uint32_t *pEFlags); */ 637 .macro sar_8_16_32, a_Name, a_cBits, a_fIntelFlags, a_LdSuff, a_StSuff 638 .p2align 2 639 BEGINPROC \a_Name 640 .cfi_startproc 641 642 /* Do we need to shift anything at all? */ 643 and w1, w1, #0x1f 644 cbz w1, 99f 645 646 /* Load EFLAGS before we start the calculation. */ 647 ldr w10, [x2] /* w10 = eflags; CF=0 PF=2 AF=4 ZF=6 SF=7 OF=11 */ 648 649 /* 650 * Do the shifting. 651 */ 652 ldr\a_LdSuff w8, [x0] /* Sign-extending for 8 and 16 bits! */ 653 asrv w9, w8, w1 654 str\a_StSuff w9, [x0] 655 656 /* 657 * Calculate EFLAGS. 658 */ 659 sub w11, w1, #1 660 lsrv w11, w8, w11 661 bfxil w10, w11, #X86_EFL_CF_BIT, #1 662 663 .ifne \a_fIntelFlags 664 mov w11, ~(X86_EFL_AF | X86_EFL_OF) 665 and w10, w10, w11 /* AF and OF are cleared */ 666 .else 667 orr w10, w10, X86_EFL_AF /* AF is set */ 668 and w10, w10, ~X86_EFL_OF /* OF is cleared */ 669 .endif 670 671 CALC_EFLAGS_PARITY w10, w9, w11 672 673 .ifne \a_cBits < 32 674 setf\a_cBits w9 /* Sets NZ */ 675 .else 676 ands wzr, w9, w9 /* Sets NZ */ 677 .endif 678 mrs x11, NZCV 679 lsr w11, w11, #30 /* N=1; Z=0 */ 680 bfi w10, w11, X86_EFL_ZF_BIT, 2 /* EFLAGS.ZF and EFLAGS.SF */ 681 682 str w10, [x2] 683 99: 684 ret 685 .cfi_endproc 686 .endm 687 688 sar_8_16_32 iemAImpl_sar_u8, 8, 1, sb, b 689 sar_8_16_32 iemAImpl_sar_u8_intel, 8, 1, sb, b 690 sar_8_16_32 iemAImpl_sar_u8_amd, 8, 0, sb, b 691 692 sar_8_16_32 iemAImpl_sar_u16, 16, 1, sh, h 693 sar_8_16_32 iemAImpl_sar_u16_intel, 16, 1, sh, h 694 sar_8_16_32 iemAImpl_sar_u16_amd, 16, 0, sh, h 695 696 sar_8_16_32 iemAImpl_sar_u32, 32, 1, , 697 sar_8_16_32 iemAImpl_sar_u32_intel, 32, 1, , 698 sar_8_16_32 iemAImpl_sar_u32_amd, 32, 0, , 699 700 ;; @todo this is slightly slower than the C version (release) on an M2. Investigate why. 701 /* void iemAImpl_sar_u64(uint16_t *pu64Dst, uint8_t cShift, uint32_t *pEFlags); */ 702 .macro sar_64, a_Name, a_fIntelFlags 703 .p2align 2 704 BEGINPROC \a_Name 705 .cfi_startproc 706 707 /* Do we need to shift anything at all? */ 708 ands w1, w1, #0x3f 709 b.eq 99f 710 711 /* Load EFLAGS before we start the calculation. */ 712 ldr w10, [x2] /* w10 = eflags; CF=0 PF=2 AF=4 ZF=6 SF=7 OF=11 */ 713 714 /* 715 * Do the shifting 716 */ 717 ldr x8, [x0] 718 asrv x9, x8, x1 719 str x9, [x0] 720 721 /* 722 * Calculate EFLAGS. 723 */ 724 sub w11, w1, #1 725 lsrv x11, x8, x11 726 bfxil w10, w11, #X86_EFL_CF_BIT, #1 727 728 .ifne \a_fIntelFlags 729 mov w11, ~(X86_EFL_AF | X86_EFL_OF) 730 and w10, w10, w11 /* AF and OF are cleared */ 731 .else 732 orr w10, w10, X86_EFL_AF /* AF is set */ 733 and w10, w10, ~X86_EFL_OF /* OF is cleared */ 734 .endif 735 736 CALC_EFLAGS_PARITY w10, w9, w11 737 738 ands xzr, x9, x9 /* Sets NZ */ 739 mrs x11, NZCV 740 lsr w11, w11, #30 /* N=1; Z=0 */ 741 bfi w10, w11, X86_EFL_ZF_BIT, 2 /* EFLAGS.ZF and EFLAGS.SF */ 742 743 str w10, [x2] 744 99: 745 ret 746 .cfi_endproc 747 .endm 748 749 sar_64 iemAImpl_sar_u64, 1 750 sar_64 iemAImpl_sar_u64_intel, 1 751 sar_64 iemAImpl_sar_u64_amd, 0 752 -
trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp
r104156 r104173 84 84 85 85 /** 86 * Calculates the parity flag. 87 * 88 * @returns X86_EFL_PF or 0. 89 * @param a_uResult Unsigned result value. 90 */ 91 #if !defined(RT_ARCH_ARM64) || 1 /** @todo profile this... micro benching in tstIEMAImpl indicates no gain, but it may be skewed. */ 92 # define IEM_EFL_CALC_PARITY(a_uResult) (g_afParity[(a_uResult) & 0xff]) 93 #else 94 # define IEM_EFL_CALC_PARITY(a_uResult) iemAImplCalcParity(a_uResult) 95 DECL_FORCE_INLINE(uint32_t) iemAImplCalcParity(uint32_t uResult) 96 { 97 /* Emulate 8-bit pop count. This translates to 4 EOR instructions on 98 ARM64 as they can shift the 2nd source operand. */ 99 uint8_t bPf = uResult ^ (uResult >> 4); 100 bPf ^= bPf >> 2; 101 bPf ^= bPf >> 1; 102 bPf ^= 1; 103 return (bPf & 1) << X86_EFL_PF_BIT; 104 } 105 #endif 106 107 /** 86 108 * Extracts the OF flag from a OF calculation result. 87 109 * … … 111 133 fEflTmp &= ~X86_EFL_STATUS_BITS; \ 112 134 fEflTmp |= (a_CfExpr) << X86_EFL_CF_BIT; \ 113 fEflTmp |= g_afParity[(a_uResult) & 0xff]; \135 fEflTmp |= IEM_EFL_CALC_PARITY(a_uResult); \ 114 136 fEflTmp |= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uSrc) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \ 115 137 fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \ … … 148 170 uint32_t fEflTmp = *(a_pfEFlags); \ 149 171 fEflTmp &= ~X86_EFL_STATUS_BITS; \ 150 fEflTmp |= g_afParity[(a_uResult) & 0xff]; \172 fEflTmp |= IEM_EFL_CALC_PARITY(a_uResult); \ 151 173 fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \ 152 174 fEflTmp |= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \ … … 1414 1436 { \ 1415 1437 *puDst = --iBit; \ 1416 fEfl |= g_afParity[iBit]; \1438 fEfl |= IEM_EFL_CALC_PARITY(iBit); \ 1417 1439 } \ 1418 1440 else \ … … 1553 1575 uint32_t fEfl = *(a_pfEFlags) & ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF); \ 1554 1576 if (uResult) \ 1555 fEfl |= g_afParity[uResult]; \1577 fEfl |= IEM_EFL_CALC_PARITY(uResult); \ 1556 1578 else \ 1557 1579 fEfl |= X86_EFL_ZF | X86_EFL_PF; \ … … 2402 2424 if (Result.s.Lo & RT_BIT_64(a_cBitsWidth - 1)) \ 2403 2425 fEfl |= X86_EFL_SF; \ 2404 fEfl |= g_afParity[Result.s.Lo & 0xff]; \2426 fEfl |= IEM_EFL_CALC_PARITY(Result.s.Lo); \ 2405 2427 if (Result.s.Hi != 0) \ 2406 2428 fEfl |= X86_EFL_CF | X86_EFL_OF; \ … … 2516 2538 if (Result.s.Lo & RT_BIT_64(a_cBitsWidth - 1)) \ 2517 2539 fEfl |= X86_EFL_SF; \ 2518 fEfl |= g_afParity[Result.s.Lo & 0xff]; \2540 fEfl |= IEM_EFL_CALC_PARITY(Result.s.Lo & 0xff); \ 2519 2541 } \ 2520 2542 *pfEFlags = fEfl; \ … … 2747 2769 uint32_t fEflTmp = *(a_pfEFlags); \ 2748 2770 fEflTmp &= ~X86_EFL_STATUS_BITS | X86_EFL_CF; \ 2749 fEflTmp |= g_afParity[(a_uResult) & 0xff]; \2771 fEflTmp |= IEM_EFL_CALC_PARITY(a_uResult); \ 2750 2772 fEflTmp |= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \ 2751 2773 fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \ … … 2904 2926 fEflTmp &= ~X86_EFL_STATUS_BITS & ~X86_EFL_CF; \ 2905 2927 fEflTmp |= ((a_uDst) != 0) << X86_EFL_CF_BIT; \ 2906 fEflTmp |= g_afParity[(a_uResult) & 0xff]; \2928 fEflTmp |= IEM_EFL_CALC_PARITY(a_uResult); \ 2907 2929 fEflTmp |= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \ 2908 2930 fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \ … … 3274 3296 fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \ 3275 3297 fEfl |= X86_EFL_CALC_ZF(uResult); \ 3276 fEfl |= g_afParity[uResult & 0xff]; \3298 fEfl |= IEM_EFL_CALC_PARITY(uResult); \ 3277 3299 if (!a_fIntelFlags) \ 3278 3300 fEfl |= X86_EFL_AF; /* AMD 3990x sets it unconditionally, Intel 10980XE does the oposite */ \ … … 3281 3303 } 3282 3304 3283 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY) 3305 #if !defined(RT_ARCH_ARM64) 3306 3307 # if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY) 3284 3308 EMIT_SHL(64, uint64_t, RT_NOTHING, 1) 3285 # endif3309 # endif 3286 3310 EMIT_SHL(64, uint64_t, _intel, 1) 3287 3311 EMIT_SHL(64, uint64_t, _amd, 0) 3288 3312 3289 # if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)3313 # if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY) 3290 3314 EMIT_SHL(32, uint32_t, RT_NOTHING, 1) 3291 # endif3315 # endif 3292 3316 EMIT_SHL(32, uint32_t, _intel, 1) 3293 3317 EMIT_SHL(32, uint32_t, _amd, 0) 3294 3318 3295 # if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)3319 # if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY) 3296 3320 EMIT_SHL(16, uint16_t, RT_NOTHING, 1) 3297 # endif3321 # endif 3298 3322 EMIT_SHL(16, uint16_t, _intel, 1) 3299 3323 EMIT_SHL(16, uint16_t, _amd, 0) 3300 3324 3301 # if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)3325 # if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY) 3302 3326 EMIT_SHL(8, uint8_t, RT_NOTHING, 1) 3303 # endif3327 # endif 3304 3328 EMIT_SHL(8, uint8_t, _intel, 1) 3305 3329 EMIT_SHL(8, uint8_t, _amd, 0) 3330 3331 #endif /* !RT_ARCH_ARM64 */ 3306 3332 3307 3333 … … 3327 3353 fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \ 3328 3354 fEfl |= X86_EFL_CALC_ZF(uResult); \ 3329 fEfl |= g_afParity[uResult & 0xff]; \3355 fEfl |= IEM_EFL_CALC_PARITY(uResult); \ 3330 3356 if (!a_fIntelFlags) \ 3331 3357 fEfl |= X86_EFL_AF; /* AMD 3990x sets it unconditionally, Intel 10980XE does the oposite */ \ … … 3334 3360 } 3335 3361 3336 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY) 3362 #if !defined(RT_ARCH_ARM64) 3363 3364 # if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY) 3337 3365 EMIT_SHR(64, uint64_t, RT_NOTHING, 1) 3338 # endif3366 # endif 3339 3367 EMIT_SHR(64, uint64_t, _intel, 1) 3340 3368 EMIT_SHR(64, uint64_t, _amd, 0) 3341 3369 3342 # if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)3370 # if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY) 3343 3371 EMIT_SHR(32, uint32_t, RT_NOTHING, 1) 3344 # endif3372 # endif 3345 3373 EMIT_SHR(32, uint32_t, _intel, 1) 3346 3374 EMIT_SHR(32, uint32_t, _amd, 0) 3347 3375 3348 # if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)3376 # if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY) 3349 3377 EMIT_SHR(16, uint16_t, RT_NOTHING, 1) 3350 # endif3378 # endif 3351 3379 EMIT_SHR(16, uint16_t, _intel, 1) 3352 3380 EMIT_SHR(16, uint16_t, _amd, 0) 3353 3381 3354 # if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)3382 # if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY) 3355 3383 EMIT_SHR(8, uint8_t, RT_NOTHING, 1) 3356 # endif3384 # endif 3357 3385 EMIT_SHR(8, uint8_t, _intel, 1) 3358 3386 EMIT_SHR(8, uint8_t, _amd, 0) 3387 3388 #endif /* !RT_ARCH_ARM64 */ 3359 3389 3360 3390 … … 3379 3409 fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \ 3380 3410 fEfl |= X86_EFL_CALC_ZF(uResult); \ 3381 fEfl |= g_afParity[uResult & 0xff]; \3411 fEfl |= IEM_EFL_CALC_PARITY(uResult); \ 3382 3412 if (!a_fIntelFlags) \ 3383 3413 fEfl |= X86_EFL_AF; /* AMD 3990x sets it unconditionally, Intel 10980XE does the oposite */ \ … … 3386 3416 } 3387 3417 3388 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY) 3418 #if !defined(RT_ARCH_ARM64) 3419 3420 # if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY) 3389 3421 EMIT_SAR(64, uint64_t, int64_t, RT_NOTHING, 1) 3390 # endif3422 # endif 3391 3423 EMIT_SAR(64, uint64_t, int64_t, _intel, 1) 3392 3424 EMIT_SAR(64, uint64_t, int64_t, _amd, 0) 3393 3425 3394 # if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)3426 # if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY) 3395 3427 EMIT_SAR(32, uint32_t, int32_t, RT_NOTHING, 1) 3396 # endif3428 # endif 3397 3429 EMIT_SAR(32, uint32_t, int32_t, _intel, 1) 3398 3430 EMIT_SAR(32, uint32_t, int32_t, _amd, 0) 3399 3431 3400 # if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)3432 # if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY) 3401 3433 EMIT_SAR(16, uint16_t, int16_t, RT_NOTHING, 1) 3402 # endif3434 # endif 3403 3435 EMIT_SAR(16, uint16_t, int16_t, _intel, 1) 3404 3436 EMIT_SAR(16, uint16_t, int16_t, _amd, 0) 3405 3437 3406 # if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)3438 # if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY) 3407 3439 EMIT_SAR(8, uint8_t, int8_t, RT_NOTHING, 1) 3408 # endif3440 # endif 3409 3441 EMIT_SAR(8, uint8_t, int8_t, _intel, 1) 3410 3442 EMIT_SAR(8, uint8_t, int8_t, _amd, 0) 3443 3444 #endif /* !RT_ARCH_ARM64 */ 3411 3445 3412 3446 … … 3451 3485 AssertCompile(X86_EFL_CF_BIT == 0); \ 3452 3486 fEfl |= (uDst >> (a_cBitsWidth - cShift)) & X86_EFL_CF; /* CF = last bit shifted out */ \ 3453 fEfl |= g_afParity[uResult & 0xff]; \3487 fEfl |= IEM_EFL_CALC_PARITY(uResult); \ 3454 3488 fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \ 3455 3489 fEfl |= X86_EFL_CALC_ZF(uResult); \ … … 3508 3542 fEfl |= X86_EFL_AF; \ 3509 3543 } \ 3510 fEfl |= g_afParity[uResult & 0xff]; \3544 fEfl |= IEM_EFL_CALC_PARITY(uResult); \ 3511 3545 fEfl |= X86_EFL_CALC_SF(uResult, 16); \ 3512 3546 fEfl |= X86_EFL_CALC_ZF(uResult); \ … … 3566 3600 fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \ 3567 3601 fEfl |= X86_EFL_CALC_ZF(uResult); \ 3568 fEfl |= g_afParity[uResult & 0xff]; \3602 fEfl |= IEM_EFL_CALC_PARITY(uResult); \ 3569 3603 *pfEFlags = fEfl; \ 3570 3604 } \ … … 3618 3652 fEfl |= X86_EFL_CALC_SF(uResult, 16); \ 3619 3653 fEfl |= X86_EFL_CALC_ZF(uResult); \ 3620 fEfl |= g_afParity[uResult & 0xff]; \3654 fEfl |= IEM_EFL_CALC_PARITY(uResult); \ 3621 3655 *pfEFlags = fEfl; \ 3622 3656 } \ -
trunk/src/VBox/VMM/testcase/tstIEMAImpl.cpp
r104156 r104173 256 256 257 257 static unsigned g_cVerbosity = 0; 258 static bool g_fVerboseSkipping = true; 258 259 259 260 … … 1246 1247 static bool SubTestAndCheckIfEnabled(const char *pszName) 1247 1248 { 1248 RTTestSub(g_hTest, pszName); 1249 if (IsTestEnabled(pszName)) 1250 return true; 1251 RTTestSkipped(g_hTest, g_cVerbosity > 0 ? "excluded" : NULL); 1249 bool const fEnabled = IsTestEnabled(pszName); 1250 if (g_fVerboseSkipping || fEnabled) 1251 { 1252 RTTestSub(g_hTest, pszName); 1253 if (fEnabled) 1254 return true; 1255 RTTestSkipped(g_hTest, g_cVerbosity > 0 ? "excluded" : NULL); 1256 } 1252 1257 return false; 1253 1258 } … … 10009 10014 uint32_t const cDefaultTests = 96; 10010 10015 uint32_t cTests = cDefaultTests; 10016 10011 10017 RTGETOPTDEF const s_aOptions[] = 10012 10018 { … … 10037 10043 { "--verbose", 'v', RTGETOPT_REQ_NOTHING }, 10038 10044 { "--quiet", 'q', RTGETOPT_REQ_NOTHING }, 10045 { "--quiet-skipping", 'Q', RTGETOPT_REQ_NOTHING }, 10039 10046 }; 10040 10047 … … 10130 10137 g_cVerbosity++; 10131 10138 break; 10139 case 'Q': 10140 g_fVerboseSkipping = false; 10141 break; 10132 10142 10133 10143 case 'h': 10134 RTPrintf("usage: % s<-g|-t> [options]\n"10144 RTPrintf("usage: %Rbn <-g|-t> [options]\n" 10135 10145 "\n" 10136 10146 "Mode:\n" … … 10181 10191 " -q, --quiet\n" 10182 10192 " Noise level. Default: --quiet\n" 10183 , argv[0], cDefaultTests); 10193 " -Q, --quiet-skipping\n" 10194 " Don't display skipped tests.\n" 10195 "\n" 10196 "Tip! When working on a single instruction, use the the -I and -Q options to\n" 10197 " restrict the testing: %Rbn -tiQI \"shr_*\"\n" 10198 , argv[0], cDefaultTests, argv[0]); 10184 10199 return RTEXITCODE_SUCCESS; 10185 10200 default:
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