Changeset 104140 in vbox
- Timestamp:
- Apr 3, 2024 2:56:11 PM (6 months ago)
- Location:
- trunk/src/VBox/VMM/VMMAll
- Files:
-
- 2 edited
-
IEMAllInstPython.py (modified) (4 diffs)
-
IEMAllN8veRecompFuncs.h (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py
r104135 r104140 2995 2995 'IEM_MC_CALL_AVX_AIMPL_2': (McBlock.parseMcCallAvxAImpl, True, True, g_fNativeSimd), 2996 2996 'IEM_MC_CALL_AVX_AIMPL_3': (McBlock.parseMcCallAvxAImpl, True, True, g_fNativeSimd), 2997 'IEM_MC_CALL_AVX_AIMPL_NEW_3': (McBlock.parseMcCallAvxAImpl, True, True, False, ), 2997 2998 'IEM_MC_CALL_CIMPL_0': (McBlock.parseMcCallCImpl, True, True, False, ), 2998 2999 'IEM_MC_CALL_CIMPL_1': (McBlock.parseMcCallCImpl, True, True, False, ), … … 3052 3053 'IEM_MC_FETCH_GREG_U8_ZX_U64': (McBlock.parseMcGeneric, False, False, True, ), # thrd var 3053 3054 'IEM_MC_FETCH_GREG_PAIR_U32': (McBlock.parseMcGeneric, False, False, False, ), 3054 'IEM_MC_FETCH_GREG_PAIR_U64': (McBlock.parseMcGeneric, False, False, False,),3055 'IEM_MC_FETCH_GREG_PAIR_U64': (McBlock.parseMcGeneric, False, False, g_fNativeSimd), 3055 3056 'IEM_MC_FETCH_MEM_D80': (McBlock.parseMcGeneric, True, True, False, ), 3056 3057 'IEM_MC_FETCH_MEM_I16': (McBlock.parseMcGeneric, True, True, False, ), … … 3260 3261 'IEM_MC_RAISE_DIVIDE_ERROR': (McBlock.parseMcGeneric, True, True, True, ), 3261 3262 'IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO': (McBlock.parseMcGeneric, True, True, False, ), 3262 'IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED': (McBlock.parseMcGeneric, True, True, False,),3263 'IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED': (McBlock.parseMcGeneric, True, True, True, ), 3263 3264 'IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT': (McBlock.parseMcGeneric, True, True, True, ), 3264 3265 'IEM_MC_REF_EFLAGS': (McBlock.parseMcGeneric, False, False, True, ), … … 3322 3323 'IEM_MC_STORE_GREG_U8_CONST': (McBlock.parseMcGeneric, True, True, True, ), # thrd var 3323 3324 'IEM_MC_STORE_GREG_PAIR_U32': (McBlock.parseMcGeneric, True, True, False, ), 3324 'IEM_MC_STORE_GREG_PAIR_U64': (McBlock.parseMcGeneric, True, True, False,),3325 'IEM_MC_STORE_GREG_PAIR_U64': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), 3325 3326 'IEM_MC_STORE_MEM_I16_CONST_BY_REF': (McBlock.parseMcGeneric, True, True, False, ), 3326 3327 'IEM_MC_STORE_MEM_I32_CONST_BY_REF': (McBlock.parseMcGeneric, True, True, False, ), -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h
r104135 r104140 1275 1275 1276 1276 1277 #define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \ 1278 off = iemNativeEmitRaiseGp0IfEffAddrUnaligned(pReNative, off, pCallEntry->idxInstr, a_EffAddr, a_cbAlign) 1279 1280 /** 1281 * Emits code to raise a \#GP(0) if the given variable contains an unaligned address. 1282 * 1283 * @returns New code buffer offset, UINT32_MAX on failure. 1284 * @param pReNative The native recompile state. 1285 * @param off The code buffer offset. 1286 * @param idxInstr The current instruction. 1287 */ 1288 DECL_INLINE_THROW(uint32_t) 1289 iemNativeEmitRaiseGp0IfEffAddrUnaligned(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr, uint8_t idxVarEffAddr, uint8_t cbAlign) 1290 { 1291 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarEffAddr); 1292 IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxVarEffAddr, sizeof(RTGCPTR)); 1293 1294 /* 1295 * Make sure we don't have any outstanding guest register writes as we may throw an exception. 1296 */ 1297 off = iemNativeRegFlushPendingWrites(pReNative, off); 1298 1299 #ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING 1300 off = iemNativeEmitStoreImmToVCpuU8(pReNative, off, idxInstr, RT_UOFFSETOF(VMCPUCC, iem.s.idxTbCurInstr)); 1301 #else 1302 RT_NOREF(idxInstr); 1303 #endif 1304 1305 uint8_t const idxLabelRaiseGp0 = iemNativeLabelCreate(pReNative, kIemNativeLabelType_RaiseGp0); 1306 uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxVarEffAddr, &off); 1307 1308 off = iemNativeEmitTestAnyBitsInGprAndJmpToLabelIfAnySet(pReNative, off, idxVarReg, cbAlign - 1, idxLabelRaiseGp0); 1309 1310 iemNativeVarRegisterRelease(pReNative, idxVarEffAddr); 1311 return off; 1312 } 1313 1314 1277 1315 /********************************************************************************************************************************* 1278 1316 * Emitters for conditionals (IEM_MC_IF_XXX, IEM_MC_ELSE, IEM_MC_ENDIF) * … … 2844 2882 2845 2883 2884 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR 2885 #define IEM_MC_FETCH_GREG_PAIR_U64(a_u128Dst, a_iGRegLo, a_iGRegHi) \ 2886 off = iemNativeEmitFetchGregPairU64(pReNative, off, a_u128Dst, a_iGRegLo, a_iGRegHi) 2887 2888 /** Emits code for IEM_MC_FETCH_GREG_PAIR_U64. */ 2889 DECL_INLINE_THROW(uint32_t) 2890 iemNativeEmitFetchGregPairU64(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxDstVar, uint8_t iGRegLo, uint8_t iGRegHi) 2891 { 2892 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxDstVar); 2893 IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxDstVar, sizeof(RTUINT128U)); 2894 Assert(iGRegLo < 16 && iGRegHi < 16); 2895 2896 uint8_t const idxGstFullRegLo = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGRegLo), 2897 kIemNativeGstRegUse_ReadOnly); 2898 uint8_t const idxGstFullRegHi = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGRegHi), 2899 kIemNativeGstRegUse_ReadOnly); 2900 2901 iemNativeVarSetKindToStack(pReNative, idxDstVar); 2902 uint8_t const idxVarReg = iemNativeVarSimdRegisterAcquire(pReNative, idxDstVar, &off); 2903 off = iemNativeEmitSimdStoreGprToVecRegU64(pReNative, off, idxVarReg, idxGstFullRegLo, 0); 2904 off = iemNativeEmitSimdStoreGprToVecRegU64(pReNative, off, idxVarReg, idxGstFullRegHi, 1); 2905 2906 iemNativeVarSimdRegisterRelease(pReNative, idxDstVar); 2907 iemNativeRegFreeTmp(pReNative, idxGstFullRegLo); 2908 iemNativeRegFreeTmp(pReNative, idxGstFullRegHi); 2909 return off; 2910 } 2911 #endif 2912 2846 2913 2847 2914 /********************************************************************************************************************************* … … 3273 3340 return off; 3274 3341 } 3342 3343 3344 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR 3345 #define IEM_MC_STORE_GREG_PAIR_U64(a_iGRegLo, a_iGRegHi, a_u128Value) \ 3346 off = iemNativeEmitStoreGregPairU64(pReNative, off, a_iGRegLo, a_iGRegHi, a_u128Value) 3347 3348 /** Emits code for IEM_MC_FETCH_GREG_PAIR_U64. */ 3349 DECL_INLINE_THROW(uint32_t) 3350 iemNativeEmitStoreGregPairU64(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGRegLo, uint8_t iGRegHi, uint8_t idxDstVar) 3351 { 3352 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxDstVar); 3353 IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxDstVar, sizeof(RTUINT128U)); 3354 Assert(iGRegLo < 16 && iGRegHi < 16); 3355 3356 uint8_t const idxGstFullRegLo = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGRegLo), 3357 kIemNativeGstRegUse_ForFullWrite); 3358 uint8_t const idxGstFullRegHi = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGRegHi), 3359 kIemNativeGstRegUse_ForFullWrite); 3360 3361 iemNativeVarSetKindToStack(pReNative, idxDstVar); 3362 uint8_t const idxVarReg = iemNativeVarSimdRegisterAcquire(pReNative, idxDstVar, &off, true /*fInitialized*/); 3363 off = iemNativeEmitSimdLoadGprFromVecRegU64(pReNative, off, idxGstFullRegLo, idxVarReg, 0); 3364 off = iemNativeEmitSimdLoadGprFromVecRegU64(pReNative, off, idxGstFullRegHi, idxVarReg, 1); 3365 3366 iemNativeVarSimdRegisterRelease(pReNative, idxDstVar); 3367 iemNativeRegFreeTmp(pReNative, idxGstFullRegLo); 3368 iemNativeRegFreeTmp(pReNative, idxGstFullRegHi); 3369 return off; 3370 } 3371 #endif 3275 3372 3276 3373
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