- Timestamp:
- Apr 3, 2024 12:03:22 PM (6 months ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 9 edited
-
VMMAll/IEMAllAImplC.cpp (modified) (1 diff)
-
VMMAll/IEMAllInstPython.py (modified) (2 diffs)
-
VMMAll/IEMAllInstVexMap1.cpp.h (modified) (6 diffs)
-
VMMAll/IEMAllN8veLiveness.cpp (modified) (2 diffs)
-
VMMAll/IEMAllN8veRecompFuncs.h (modified) (1 diff)
-
include/IEMInternal.h (modified) (1 diff)
-
include/IEMMc.h (modified) (2 diffs)
-
include/IEMN8veRecompilerEmit.h (modified) (8 diffs)
-
testcase/tstIEMCheckMc.cpp (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp
r104132 r104133 7744 7744 *********************************************************************************************************************************/ 7745 7745 7746 #ifdef IEM_WITH_VEX7747 7748 /*7749 * VMOVSLDUP7750 */7751 IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc))7752 {7753 pXState->x87.aXMM[iYRegDst].au32[0] = pXState->x87.aXMM[iYRegSrc].au32[0];7754 pXState->x87.aXMM[iYRegDst].au32[1] = pXState->x87.aXMM[iYRegSrc].au32[0];7755 pXState->x87.aXMM[iYRegDst].au32[2] = pXState->x87.aXMM[iYRegSrc].au32[2];7756 pXState->x87.aXMM[iYRegDst].au32[3] = pXState->x87.aXMM[iYRegSrc].au32[2];7757 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[0] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[0];7758 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[1] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[0];7759 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[2] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[2];7760 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[3] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[2];7761 }7762 7763 7764 IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc))7765 {7766 pXState->x87.aXMM[iYRegDst].au32[0] = pSrc->au32[0];7767 pXState->x87.aXMM[iYRegDst].au32[1] = pSrc->au32[0];7768 pXState->x87.aXMM[iYRegDst].au32[2] = pSrc->au32[2];7769 pXState->x87.aXMM[iYRegDst].au32[3] = pSrc->au32[2];7770 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[0] = pSrc->au32[4];7771 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[1] = pSrc->au32[4];7772 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[2] = pSrc->au32[6];7773 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[3] = pSrc->au32[6];7774 }7775 7776 #endif /* IEM_WITH_VEX */7777 7778 7779 #ifdef IEM_WITH_VEX7780 7781 /*7782 * VMOVSHDUP7783 */7784 IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc))7785 {7786 pXState->x87.aXMM[iYRegDst].au32[0] = pXState->x87.aXMM[iYRegSrc].au32[1];7787 pXState->x87.aXMM[iYRegDst].au32[1] = pXState->x87.aXMM[iYRegSrc].au32[1];7788 pXState->x87.aXMM[iYRegDst].au32[2] = pXState->x87.aXMM[iYRegSrc].au32[3];7789 pXState->x87.aXMM[iYRegDst].au32[3] = pXState->x87.aXMM[iYRegSrc].au32[3];7790 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[0] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[1];7791 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[1] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[1];7792 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[2] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[3];7793 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[3] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[3];7794 }7795 7796 7797 IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc))7798 {7799 pXState->x87.aXMM[iYRegDst].au32[0] = pSrc->au32[1];7800 pXState->x87.aXMM[iYRegDst].au32[1] = pSrc->au32[1];7801 pXState->x87.aXMM[iYRegDst].au32[2] = pSrc->au32[3];7802 pXState->x87.aXMM[iYRegDst].au32[3] = pSrc->au32[3];7803 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[0] = pSrc->au32[5];7804 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[1] = pSrc->au32[5];7805 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[2] = pSrc->au32[7];7806 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[3] = pSrc->au32[7];7807 }7808 7809 #endif /* IEM_WITH_VEX */7810 7811 7812 #ifdef IEM_WITH_VEX7813 7814 /*7815 * VMOVDDUP7816 */7817 IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc))7818 {7819 pXState->x87.aXMM[iYRegDst].au64[0] = pXState->x87.aXMM[iYRegSrc].au64[0];7820 pXState->x87.aXMM[iYRegDst].au64[1] = pXState->x87.aXMM[iYRegSrc].au64[0];7821 pXState->u.YmmHi.aYmmHi[iYRegDst].au64[0] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au64[0];7822 pXState->u.YmmHi.aYmmHi[iYRegDst].au64[1] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au64[0];7823 }7824 7825 IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc))7826 {7827 pXState->x87.aXMM[iYRegDst].au64[0] = pSrc->au64[0];7828 pXState->x87.aXMM[iYRegDst].au64[1] = pSrc->au64[0];7829 pXState->u.YmmHi.aYmmHi[iYRegDst].au64[0] = pSrc->au64[2];7830 pXState->u.YmmHi.aYmmHi[iYRegDst].au64[1] = pSrc->au64[2];7831 }7832 7833 #endif /* IEM_WITH_VEX */7834 7835 7836 7746 /* 7837 7747 * PAND / VPAND / PANDPS / VPANDPS / PANDPD / VPANDPD -
trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py
r104129 r104133 3019 3019 'IEM_MC_CLEAR_XREG_U32_MASK': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), 3020 3020 'IEM_MC_CLEAR_YREG_128_UP': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), 3021 'IEM_MC_CLEAR_ZREG_256_UP': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), 3021 3022 'IEM_MC_COMMIT_EFLAGS': (McBlock.parseMcGeneric, True, True, True, ), 3022 3023 'IEM_MC_COMMIT_EFLAGS_OPT': (McBlock.parseMcGeneric, True, True, True, ), … … 3369 3370 'IEM_MC_STORE_YREG_U128_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), 3370 3371 'IEM_MC_STORE_YREG_U256_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), 3372 'IEM_MC_STORE_YREG_U32_U256': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), 3371 3373 'IEM_MC_STORE_YREG_U32_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), 3374 'IEM_MC_STORE_YREG_U64': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), 3375 'IEM_MC_STORE_YREG_U64_U256': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), 3372 3376 'IEM_MC_STORE_YREG_U64_ZX_VLMAX': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), 3373 3377 'IEM_MC_SUB_GREG_U16': (McBlock.parseMcGeneric, True, True, True, ), -
trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h
r104132 r104133 1142 1142 IEM_MC_PREPARE_AVX_USAGE(); 1143 1143 1144 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 0); 1145 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 1); 1146 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovsldup_256_rr, iYRegDst, iYRegSrc); 1144 IEM_MC_LOCAL(RTUINT256U, uSrc); 1145 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 1146 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 0); 1147 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 0); 1148 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 2); 1149 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2); 1150 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 4, uSrc, 4); 1151 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 5, uSrc, 4); 1152 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 6, uSrc, 6); 1153 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 7, uSrc, 6); 1154 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 1147 1155 1148 1156 IEM_MC_ADVANCE_RIP_AND_FINISH(); … … 1186 1194 1187 1195 IEM_MC_LOCAL(RTUINT256U, uSrc); 1188 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);1189 1196 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 1190 1197 1191 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 0); 1192 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovsldup_256_rm, iYRegDst, puSrc); 1198 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 0); 1199 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 0); 1200 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 2); 1201 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2); 1202 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 4, uSrc, 4); 1203 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 5, uSrc, 4); 1204 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 6, uSrc, 6); 1205 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 7, uSrc, 6); 1206 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 1193 1207 1194 1208 IEM_MC_ADVANCE_RIP_AND_FINISH(); … … 1243 1257 IEM_MC_PREPARE_AVX_USAGE(); 1244 1258 1245 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 0); 1246 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 1); 1247 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovddup_256_rr, iYRegDst, iYRegSrc); 1259 IEM_MC_LOCAL(uint64_t, uSrc1); 1260 IEM_MC_LOCAL(uint64_t, uSrc2); 1261 IEM_MC_FETCH_YREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /* a_iQword*/); 1262 IEM_MC_FETCH_YREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm), 2 /* a_iQword*/); 1263 1264 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /* a_iQword*/, uSrc1); 1265 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /* a_iQword*/, uSrc1); 1266 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 2 /* a_iQword*/, uSrc2); 1267 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 3 /* a_iQword*/, uSrc2); 1268 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 1248 1269 1249 1270 IEM_MC_ADVANCE_RIP_AND_FINISH(); … … 1286 1307 1287 1308 IEM_MC_LOCAL(RTUINT256U, uSrc); 1288 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);1289 1309 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 1290 1310 1291 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 0); 1292 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovddup_256_rm, iYRegDst, puSrc); 1311 IEM_MC_STORE_YREG_U64_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQwDst*/, uSrc, 0 /*a_iQwSrc*/); 1312 IEM_MC_STORE_YREG_U64_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /*a_iQwDst*/, uSrc, 0 /*a_iQwSrc*/); 1313 IEM_MC_STORE_YREG_U64_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2 /*a_iQwDst*/, uSrc, 2 /*a_iQwSrc*/); 1314 IEM_MC_STORE_YREG_U64_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3 /*a_iQwDst*/, uSrc, 2 /*a_iQwSrc*/); 1315 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 1293 1316 1294 1317 IEM_MC_ADVANCE_RIP_AND_FINISH(); … … 1592 1615 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 1593 1616 IEM_MC_PREPARE_AVX_USAGE(); 1594 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 0); 1595 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 1); 1596 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovshdup_256_rr, iYRegDst, iYRegSrc); 1617 1618 IEM_MC_LOCAL(RTUINT256U, uSrc); 1619 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 1620 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 1); 1621 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 1); 1622 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 3); 1623 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3); 1624 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 4, uSrc, 5); 1625 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 5, uSrc, 5); 1626 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 6, uSrc, 7); 1627 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 7, uSrc, 7); 1628 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 1597 1629 1598 1630 IEM_MC_ADVANCE_RIP_AND_FINISH(); … … 1636 1668 1637 1669 IEM_MC_LOCAL(RTUINT256U, uSrc); 1638 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);1639 1670 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 1640 1671 1641 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 0); 1642 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovshdup_256_rm, iYRegDst, puSrc); 1672 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 1); 1673 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 1); 1674 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 3); 1675 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3); 1676 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 4, uSrc, 5); 1677 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 5, uSrc, 5); 1678 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 6, uSrc, 7); 1679 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 7, uSrc, 7); 1680 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 1643 1681 1644 1682 IEM_MC_ADVANCE_RIP_AND_FINISH(); -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veLiveness.cpp
r104129 r104133 731 731 #define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) NOP() 732 732 733 #define IEM_MC_STORE_YREG_U32_U256(a_iYRegDst, a_iDwDst, a_u256Value, a_iDwSrc) NOP() 734 #define IEM_MC_STORE_YREG_U64_U256(a_iYRegDst, a_iQwDst, a_u256Value, a_iQwSrc) NOP() 735 #define IEM_MC_STORE_YREG_U64(a_iYRegDst, a_iQword, a_u64Value) NOP() 736 733 737 #define IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX(a_iYRegDst, a_u8Src) NOP() 734 738 #define IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX(a_iYRegDst, a_u16Src) NOP() … … 752 756 #define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) NOP() 753 757 #define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) NOP() 758 759 #define IEM_MC_CLEAR_ZREG_256_UP(a_iYReg) NOP() 754 760 755 761 #define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) IEM_LIVENESS_MEM(a_iSeg) -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h
r104129 r104133 8562 8562 8563 8563 8564 #define IEM_MC_STORE_YREG_U32_U256(a_iYRegDst, a_iDwDst, a_u256Value, a_iDwSrc) \ 8565 off = iemNativeEmitSimdStoreYregU32FromU256(pReNative, off, a_iYRegDst, a_iDwDst, a_u256Value, a_iDwSrc) 8566 8567 8568 /** Emits code for IEM_MC_STORE_YREG_U32_U256. */ 8569 DECL_INLINE_THROW(uint32_t) 8570 iemNativeEmitSimdStoreYregU32FromU256(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iYRegDst, uint8_t iDwDst, 8571 uint8_t idxSrcVar, uint8_t iDwSrc) 8572 { 8573 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxSrcVar); 8574 IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxSrcVar, sizeof(RTUINT256U)); 8575 8576 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYRegDst), 8577 iDwDst < 4 8578 ? kIemNativeGstSimdRegLdStSz_Low128 8579 : kIemNativeGstSimdRegLdStSz_High128, 8580 kIemNativeGstRegUse_ForUpdate); 8581 uint8_t const idxVarRegSrc = iemNativeVarSimdRegisterAcquire(pReNative, idxSrcVar, &off, true /*fInitalized*/); 8582 uint8_t const idxRegTmp = iemNativeRegAllocTmp(pReNative, &off); 8583 8584 off = iemNativeEmitSimdLoadGprFromVecRegU32(pReNative, off, idxRegTmp, idxVarRegSrc, iDwSrc); 8585 off = iemNativeEmitSimdStoreGprToVecRegU32(pReNative, off, idxSimdRegDst, idxRegTmp, iDwDst); 8586 8587 /* Free but don't flush the source register. */ 8588 iemNativeSimdRegFreeTmp(pReNative, idxSimdRegDst); 8589 iemNativeRegFreeTmp(pReNative, idxRegTmp); 8590 iemNativeVarSimdRegisterRelease(pReNative, idxSrcVar); 8591 8592 return off; 8593 } 8594 8595 8596 #define IEM_MC_STORE_YREG_U64_U256(a_iYRegDst, a_iQwDst, a_u256Value, a_iQwSrc) \ 8597 off = iemNativeEmitSimdStoreYregU64FromU256(pReNative, off, a_iYRegDst, a_iQwDst, a_u256Value, a_iQwSrc) 8598 8599 8600 /** Emits code for IEM_MC_STORE_YREG_U64_U256. */ 8601 DECL_INLINE_THROW(uint32_t) 8602 iemNativeEmitSimdStoreYregU64FromU256(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iYRegDst, uint8_t iQwDst, 8603 uint8_t idxSrcVar, uint8_t iQwSrc) 8604 { 8605 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxSrcVar); 8606 IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxSrcVar, sizeof(RTUINT256U)); 8607 8608 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYRegDst), 8609 iQwDst < 2 8610 ? kIemNativeGstSimdRegLdStSz_Low128 8611 : kIemNativeGstSimdRegLdStSz_High128, 8612 kIemNativeGstRegUse_ForUpdate); 8613 uint8_t const idxVarRegSrc = iemNativeVarSimdRegisterAcquire(pReNative, idxSrcVar, &off, true /*fInitalized*/); 8614 uint8_t const idxRegTmp = iemNativeRegAllocTmp(pReNative, &off); 8615 8616 off = iemNativeEmitSimdLoadGprFromVecRegU64(pReNative, off, idxRegTmp, idxVarRegSrc, iQwSrc); 8617 off = iemNativeEmitSimdStoreGprToVecRegU64(pReNative, off, idxSimdRegDst, idxRegTmp, iQwDst); 8618 8619 /* Free but don't flush the source register. */ 8620 iemNativeSimdRegFreeTmp(pReNative, idxSimdRegDst); 8621 iemNativeRegFreeTmp(pReNative, idxRegTmp); 8622 iemNativeVarSimdRegisterRelease(pReNative, idxSrcVar); 8623 8624 return off; 8625 } 8626 8627 8628 #define IEM_MC_STORE_YREG_U64(a_iYRegDst, a_iQword, a_u64Value) \ 8629 off = iemNativeEmitSimdStoreYregU64(pReNative, off, a_iYRegDst, a_iQword, a_u64Value) 8630 8631 8632 /** Emits code for IEM_MC_STORE_YREG_U64. */ 8633 DECL_INLINE_THROW(uint32_t) 8634 iemNativeEmitSimdStoreYregU64(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iYRegDst, uint8_t iQwDst, uint8_t idxSrcVar) 8635 { 8636 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxSrcVar); 8637 IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxSrcVar, sizeof(uint64_t)); 8638 8639 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYRegDst), 8640 iQwDst < 2 8641 ? kIemNativeGstSimdRegLdStSz_Low128 8642 : kIemNativeGstSimdRegLdStSz_High128, 8643 kIemNativeGstRegUse_ForUpdate); 8644 8645 uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxSrcVar, &off); 8646 8647 off = iemNativeEmitSimdStoreGprToVecRegU64(pReNative, off, idxSimdRegDst, idxVarReg, iQwDst); 8648 8649 /* Free but don't flush the source register. */ 8650 iemNativeSimdRegFreeTmp(pReNative, idxSimdRegDst); 8651 iemNativeVarRegisterRelease(pReNative, idxSrcVar); 8652 8653 return off; 8654 } 8655 8656 8657 #define IEM_MC_CLEAR_ZREG_256_UP(a_iYReg) \ 8658 off = iemNativeEmitSimdClearZregU256Vlmax(pReNative, off, a_iYReg) 8659 8660 /** Emits code for IEM_MC_CLEAR_ZREG_256_UP. */ 8661 DECL_INLINE_THROW(uint32_t) 8662 iemNativeEmitSimdClearZregU256Vlmax(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iYReg) 8663 { 8664 RT_NOREF(pReNative, iYReg); 8665 /** @todo Needs to be implemented when support for AVX-512 is added. */ 8666 return off; 8667 } 8668 8669 8564 8670 #define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \ 8565 8671 off = iemNativeEmitSimdSseStoreResult(pReNative, off, a_SseData, a_iXmmReg) -
trunk/src/VBox/VMM/include/IEMInternal.h
r104132 r104133 3591 3591 /** @name Media (SSE/MMX/AVX) operation: Sort this later 3592 3592 * @{ */ 3593 IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));3594 IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));3595 IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));3596 IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));3597 IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));3598 IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));3599 3600 3593 IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc)); 3601 3594 IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc)); -
trunk/src/VBox/VMM/include/IEMMc.h
r104129 r104133 702 702 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \ 703 703 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \ 704 } while (0) 705 #define IEM_MC_STORE_YREG_U32_U256(a_iYRegDst, a_iDwDst, a_u256Value, a_iDwSrc) \ 706 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \ 707 if ((a_iDwDst) < 4) \ 708 pVCpu->cpum.GstCtx.XState.x87.aXMM[(iYRegDstTmp)].au32[(a_iDwDst)] = (a_u256Value).au32[(a_iDwSrc)]; \ 709 else \ 710 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[(iYRegDstTmp)].au32[(a_iDwDst) - 4] = (a_u256Value).au32[(a_iDwSrc)]; \ 711 } while (0) 712 #define IEM_MC_STORE_YREG_U64_U256(a_iYRegDst, a_iQwDst, a_u256Value, a_iQwSrc) \ 713 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \ 714 if ((a_iQwDst) < 2) \ 715 pVCpu->cpum.GstCtx.XState.x87.aXMM[(iYRegDstTmp)].au64[(a_iQwDst)] = (a_u256Value).au64[(a_iQwDst)]; \ 716 else \ 717 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[(iYRegDstTmp)].au64[(a_iQwDst) - 4] = (a_u256Value).au64[(a_iQwDst)]; \ 718 } while (0) 719 #define IEM_MC_STORE_YREG_U64(a_iYRegDst, a_iQword, a_u64Value) \ 720 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \ 721 if ((a_iQword) < 2) \ 722 pVCpu->cpum.GstCtx.XState.x87.aXMM[(iYRegDstTmp)].au64[(a_iQword)] = (a_u64Value); \ 723 else \ 724 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[(iYRegDstTmp)].au64[(a_iQword) - 2] = (a_u64Value); \ 704 725 } while (0) 705 726 … … 889 910 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \ 890 911 } while (0) 912 913 #define IEM_MC_CLEAR_ZREG_256_UP(a_iYReg) \ 914 do { IEM_MC_INT_CLEAR_ZMM_256_UP(a_iYReg); } while (0) 891 915 892 916 #ifndef IEM_WITH_SETJMP -
trunk/src/VBox/VMM/include/IEMN8veRecompilerEmit.h
r104099 r104133 8286 8286 if (iQWord >= 2) 8287 8287 { 8288 /** @todo Currently not used. */ 8289 AssertReleaseFailed(); 8288 /* 8289 * vpextrq doesn't work on the upper 128-bits. 8290 * So we use the following sequence: 8291 * vextracti128 vectmp0, vecsrc, 1 8292 * pextrd gpr, vectmp0, #(iQWord - 2) 8293 */ 8294 /* vextracti128 */ 8295 pCodeBuf[off++] = X86_OP_VEX3; 8296 pCodeBuf[off++] = X86_OP_VEX3_BYTE1_MAKE(0x3, IEMNATIVE_SIMD_REG_FIXED_TMP0 >= 8, false, iVecRegSrc >= 8); 8297 pCodeBuf[off++] = X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(false, true, X86_OP_VEX3_BYTE2_P_066H); 8298 pCodeBuf[off++] = 0x39; 8299 pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegSrc & 7, IEMNATIVE_SIMD_REG_FIXED_TMP0 & 7); 8300 pCodeBuf[off++] = 0x1; 8301 8302 /* pextrd gpr, vecsrc, #iDWord (ASSUMES SSE4.1). */ 8303 pCodeBuf[off++] = X86_OP_PRF_SIZE_OP; 8304 pCodeBuf[off++] = X86_OP_REX_W 8305 | (IEMNATIVE_SIMD_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_R) 8306 | (iGprDst < 8 ? 0 : X86_OP_REX_B); 8307 pCodeBuf[off++] = 0x0f; 8308 pCodeBuf[off++] = 0x3a; 8309 pCodeBuf[off++] = 0x16; 8310 pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, IEMNATIVE_SIMD_REG_FIXED_TMP0 & 7, iGprDst & 7); 8311 pCodeBuf[off++] = iQWord - 2; 8290 8312 } 8291 8313 else … … 8347 8369 if (iDWord >= 4) 8348 8370 { 8349 /** @todo Currently not used. */ 8350 AssertReleaseFailed(); 8371 /* 8372 * vpextrd doesn't work on the upper 128-bits. 8373 * So we use the following sequence: 8374 * vextracti128 vectmp0, vecsrc, 1 8375 * pextrd gpr, vectmp0, #(iDWord - 4) 8376 */ 8377 /* vextracti128 */ 8378 pCodeBuf[off++] = X86_OP_VEX3; 8379 pCodeBuf[off++] = X86_OP_VEX3_BYTE1_MAKE(0x3, IEMNATIVE_SIMD_REG_FIXED_TMP0 >= 8, false, iVecRegSrc >= 8); 8380 pCodeBuf[off++] = X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(false, true, X86_OP_VEX3_BYTE2_P_066H); 8381 pCodeBuf[off++] = 0x39; 8382 pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegSrc & 7, IEMNATIVE_SIMD_REG_FIXED_TMP0 & 7); 8383 pCodeBuf[off++] = 0x1; 8384 8385 /* pextrd gpr, vecsrc, #iDWord (ASSUMES SSE4.1). */ 8386 pCodeBuf[off++] = X86_OP_PRF_SIZE_OP; 8387 if (iGprDst >= 8 || IEMNATIVE_SIMD_REG_FIXED_TMP0 >= 8) 8388 pCodeBuf[off++] = (IEMNATIVE_SIMD_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_R) 8389 | (iGprDst < 8 ? 0 : X86_OP_REX_B); 8390 pCodeBuf[off++] = 0x0f; 8391 pCodeBuf[off++] = 0x3a; 8392 pCodeBuf[off++] = 0x16; 8393 pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, IEMNATIVE_SIMD_REG_FIXED_TMP0 & 7, iGprDst & 7); 8394 pCodeBuf[off++] = iDWord - 4; 8351 8395 } 8352 8396 else … … 8364 8408 } 8365 8409 #elif defined(RT_ARCH_ARM64) 8410 Assert(iDWord < 4); 8411 8366 8412 /* umov gprdst, vecsrc[iDWord] */ 8367 8413 pCodeBuf[off++] = Armv8A64MkVecInstrUmov(iGprDst, iVecRegSrc, iDWord, kArmv8InstrUmovInsSz_U32, false /*fDst64Bit*/); … … 8382 8428 8383 8429 #ifdef RT_ARCH_AMD64 8384 off = iemNativeEmitSimdLoadGprFromVecRegU32Ex(iemNativeInstrBufEnsure(pReNative, off, 7), off, iGprDst, iVecRegSrc, iDWord);8430 off = iemNativeEmitSimdLoadGprFromVecRegU32Ex(iemNativeInstrBufEnsure(pReNative, off, 15), off, iGprDst, iVecRegSrc, iDWord); 8385 8431 #elif defined(RT_ARCH_ARM64) 8386 8432 /* ASSUMES that there are two adjacent 128-bit registers available for the 256-bit value. */ … … 8527 8573 { 8528 8574 #ifdef RT_ARCH_AMD64 8529 /* pinsrq vecsrc, gpr, #iQWord (ASSUMES SSE4.1). */ 8530 pCodeBuf[off++] = X86_OP_PRF_SIZE_OP; 8531 pCodeBuf[off++] = X86_OP_REX_W 8532 | (iVecRegDst < 8 ? 0 : X86_OP_REX_R) 8533 | (iGprSrc < 8 ? 0 : X86_OP_REX_B); 8534 pCodeBuf[off++] = 0x0f; 8535 pCodeBuf[off++] = 0x3a; 8536 pCodeBuf[off++] = 0x22; 8537 pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, iGprSrc & 7); 8538 pCodeBuf[off++] = iQWord; 8575 if (iQWord >= 2) 8576 { 8577 /* 8578 * vpinsrq doesn't work on the upper 128-bits. 8579 * So we use the following sequence: 8580 * vextracti128 vectmp0, vecdst, 1 8581 * pinsrq vectmp0, gpr, #(iQWord - 2) 8582 * vinserti128 vecdst, vectmp0, 1 8583 */ 8584 /* vextracti128 */ 8585 pCodeBuf[off++] = X86_OP_VEX3; 8586 pCodeBuf[off++] = X86_OP_VEX3_BYTE1_MAKE(0x3, IEMNATIVE_SIMD_REG_FIXED_TMP0 >= 8, false, iVecRegDst >= 8); 8587 pCodeBuf[off++] = X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(false, true, X86_OP_VEX3_BYTE2_P_066H); 8588 pCodeBuf[off++] = 0x39; 8589 pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, IEMNATIVE_SIMD_REG_FIXED_TMP0 & 7); 8590 pCodeBuf[off++] = 0x1; 8591 8592 /* pinsrq */ 8593 pCodeBuf[off++] = X86_OP_PRF_SIZE_OP; 8594 pCodeBuf[off++] = X86_OP_REX_W 8595 | (IEMNATIVE_SIMD_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_R) 8596 | (iGprSrc < 8 ? 0 : X86_OP_REX_B); 8597 pCodeBuf[off++] = 0x0f; 8598 pCodeBuf[off++] = 0x3a; 8599 pCodeBuf[off++] = 0x22; 8600 pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, IEMNATIVE_SIMD_REG_FIXED_TMP0 & 7, iGprSrc & 7); 8601 pCodeBuf[off++] = iQWord - 2; 8602 8603 /* vinserti128 */ 8604 pCodeBuf[off++] = X86_OP_VEX3; 8605 pCodeBuf[off++] = X86_OP_VEX3_BYTE1_MAKE(0x3, IEMNATIVE_SIMD_REG_FIXED_TMP0 >= 8, false, iVecRegDst >= 8); 8606 pCodeBuf[off++] = X86_OP_VEX3_BYTE2_MAKE(false, iVecRegDst, true, X86_OP_VEX3_BYTE2_P_066H); 8607 pCodeBuf[off++] = 0x38; 8608 pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, IEMNATIVE_SIMD_REG_FIXED_TMP0 & 7); 8609 pCodeBuf[off++] = 0x01; /* Immediate */ 8610 } 8611 else 8612 { 8613 /* pinsrq vecsrc, gpr, #iQWord (ASSUMES SSE4.1). */ 8614 pCodeBuf[off++] = X86_OP_PRF_SIZE_OP; 8615 pCodeBuf[off++] = X86_OP_REX_W 8616 | (iVecRegDst < 8 ? 0 : X86_OP_REX_R) 8617 | (iGprSrc < 8 ? 0 : X86_OP_REX_B); 8618 pCodeBuf[off++] = 0x0f; 8619 pCodeBuf[off++] = 0x3a; 8620 pCodeBuf[off++] = 0x22; 8621 pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, iGprSrc & 7); 8622 pCodeBuf[off++] = iQWord; 8623 } 8539 8624 #elif defined(RT_ARCH_ARM64) 8540 8625 /* ins vecsrc[iQWord], gpr */ … … 8553 8638 iemNativeEmitSimdStoreGprToVecRegU64(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iVecRegDst, uint8_t iGprSrc, uint8_t iQWord) 8554 8639 { 8555 Assert(iQWord <= 1); 8556 8557 #ifdef RT_ARCH_AMD64 8558 off = iemNativeEmitSimdStoreGprToVecRegU64Ex(iemNativeInstrBufEnsure(pReNative, off, 7), off, iVecRegDst, iGprSrc, iQWord); 8559 #elif defined(RT_ARCH_ARM64) 8560 off = iemNativeEmitSimdStoreGprToVecRegU64Ex(iemNativeInstrBufEnsure(pReNative, off, 1), off, iVecRegDst, iGprSrc, iQWord); 8640 Assert(iQWord <= 3); 8641 8642 #ifdef RT_ARCH_AMD64 8643 off = iemNativeEmitSimdStoreGprToVecRegU64Ex(iemNativeInstrBufEnsure(pReNative, off, 19), off, iVecRegDst, iGprSrc, iQWord); 8644 #elif defined(RT_ARCH_ARM64) 8645 Assert(!(iVecRegDst & 0x1)); 8646 if (iQWord >= 2) 8647 off = iemNativeEmitSimdStoreGprToVecRegU64Ex(iemNativeInstrBufEnsure(pReNative, off, 1), off, iVecRegDst + 1, iGprSrc, iQWord - 2); 8648 else 8649 off = iemNativeEmitSimdStoreGprToVecRegU64Ex(iemNativeInstrBufEnsure(pReNative, off, 1), off, iVecRegDst, iGprSrc, iQWord); 8561 8650 #else 8562 8651 # error "port me" … … 8574 8663 { 8575 8664 #ifdef RT_ARCH_AMD64 8576 /* pinsrd vecsrc, gpr, #iDWord (ASSUMES SSE4.1). */ 8577 pCodeBuf[off++] = X86_OP_PRF_SIZE_OP; 8578 if (iVecRegDst >= 8 || iGprSrc >= 8) 8579 pCodeBuf[off++] = (iVecRegDst < 8 ? 0 : X86_OP_REX_R) 8580 | (iGprSrc < 8 ? 0 : X86_OP_REX_B); 8581 pCodeBuf[off++] = 0x0f; 8582 pCodeBuf[off++] = 0x3a; 8583 pCodeBuf[off++] = 0x22; 8584 pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, iGprSrc & 7); 8585 pCodeBuf[off++] = iDWord; 8665 if (iDWord >= 4) 8666 { 8667 /* 8668 * vpinsrq doesn't work on the upper 128-bits. 8669 * So we use the following sequence: 8670 * vextracti128 vectmp0, vecdst, 1 8671 * pinsrd vectmp0, gpr, #(iDword - 4) 8672 * vinserti128 vecdst, vectmp0, 1 8673 */ 8674 /* vextracti128 */ 8675 pCodeBuf[off++] = X86_OP_VEX3; 8676 pCodeBuf[off++] = X86_OP_VEX3_BYTE1_MAKE(0x3, IEMNATIVE_SIMD_REG_FIXED_TMP0 >= 8, false, iVecRegDst >= 8); 8677 pCodeBuf[off++] = X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(false, true, X86_OP_VEX3_BYTE2_P_066H); 8678 pCodeBuf[off++] = 0x39; 8679 pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, IEMNATIVE_SIMD_REG_FIXED_TMP0 & 7); 8680 pCodeBuf[off++] = 0x1; 8681 8682 /* pinsrd */ 8683 pCodeBuf[off++] = X86_OP_PRF_SIZE_OP; 8684 if (IEMNATIVE_SIMD_REG_FIXED_TMP0 >= 8 || iGprSrc >= 8) 8685 pCodeBuf[off++] = (IEMNATIVE_SIMD_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_R) 8686 | (iGprSrc < 8 ? 0 : X86_OP_REX_B); 8687 pCodeBuf[off++] = 0x0f; 8688 pCodeBuf[off++] = 0x3a; 8689 pCodeBuf[off++] = 0x22; 8690 pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, IEMNATIVE_SIMD_REG_FIXED_TMP0 & 7, iGprSrc & 7); 8691 pCodeBuf[off++] = iDWord - 4; 8692 8693 /* vinserti128 */ 8694 pCodeBuf[off++] = X86_OP_VEX3; 8695 pCodeBuf[off++] = X86_OP_VEX3_BYTE1_MAKE(0x3, IEMNATIVE_SIMD_REG_FIXED_TMP0 >= 8, false, iVecRegDst >= 8); 8696 pCodeBuf[off++] = X86_OP_VEX3_BYTE2_MAKE(false, iVecRegDst, true, X86_OP_VEX3_BYTE2_P_066H); 8697 pCodeBuf[off++] = 0x38; 8698 pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, IEMNATIVE_SIMD_REG_FIXED_TMP0 & 7); 8699 pCodeBuf[off++] = 0x01; /* Immediate */ 8700 } 8701 else 8702 { 8703 /* pinsrd vecsrc, gpr, #iDWord (ASSUMES SSE4.1). */ 8704 pCodeBuf[off++] = X86_OP_PRF_SIZE_OP; 8705 if (iVecRegDst >= 8 || iGprSrc >= 8) 8706 pCodeBuf[off++] = (iVecRegDst < 8 ? 0 : X86_OP_REX_R) 8707 | (iGprSrc < 8 ? 0 : X86_OP_REX_B); 8708 pCodeBuf[off++] = 0x0f; 8709 pCodeBuf[off++] = 0x3a; 8710 pCodeBuf[off++] = 0x22; 8711 pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, iGprSrc & 7); 8712 pCodeBuf[off++] = iDWord; 8713 } 8586 8714 #elif defined(RT_ARCH_ARM64) 8587 8715 /* ins vecsrc[iDWord], gpr */ … … 8600 8728 iemNativeEmitSimdStoreGprToVecRegU32(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iVecRegDst, uint8_t iGprSrc, uint8_t iDWord) 8601 8729 { 8602 Assert(iDWord <= 3); 8603 8604 #ifdef RT_ARCH_AMD64 8605 off = iemNativeEmitSimdStoreGprToVecRegU32Ex(iemNativeInstrBufEnsure(pReNative, off, 7), off, iVecRegDst, iGprSrc, iDWord); 8606 #elif defined(RT_ARCH_ARM64) 8607 off = iemNativeEmitSimdStoreGprToVecRegU32Ex(iemNativeInstrBufEnsure(pReNative, off, 1), off, iVecRegDst, iGprSrc, iDWord); 8730 Assert(iDWord <= 7); 8731 8732 #ifdef RT_ARCH_AMD64 8733 off = iemNativeEmitSimdStoreGprToVecRegU32Ex(iemNativeInstrBufEnsure(pReNative, off, 19), off, iVecRegDst, iGprSrc, iDWord); 8734 #elif defined(RT_ARCH_ARM64) 8735 Assert(!(iVecRegDst & 0x1)); 8736 if (iDWord >= 4) 8737 off = iemNativeEmitSimdStoreGprToVecRegU32Ex(iemNativeInstrBufEnsure(pReNative, off, 1), off, iVecRegDst + 1, iGprSrc, iDWord - 4); 8738 else 8739 off = iemNativeEmitSimdStoreGprToVecRegU32Ex(iemNativeInstrBufEnsure(pReNative, off, 1), off, iVecRegDst, iGprSrc, iDWord); 8608 8740 #else 8609 8741 # error "port me" -
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r104129 r104133 843 843 #define IEM_MC_FETCH_YREG_U64(a_u64Value, a_iYRegSrc, a_iQWord) do { CHK_YREG_IDX(a_iYRegSrc); CHK_VAR(a_u64Value); (a_u64Value) = UINT64_MAX; CHK_TYPE(uint64_t, a_u64Value); (void)fAvxRead; (void)fMcBegin; } while (0) 844 844 #define IEM_MC_FETCH_YREG_U32(a_u32Value, a_iYRegSrc) do { CHK_YREG_IDX(a_iYRegSrc); CHK_VAR(a_u32Value); (a_u32Value) = UINT32_MAX; CHK_TYPE(uint32_t, a_u32Value); (void)fAvxRead; (void)fMcBegin; } while (0) 845 #define IEM_MC_STORE_YREG_U64(a_iYRegDst, a_iQword, a_u64Value) do { CHK_XREG_IDX(a_iYRegDst); CHK_VAR(a_u64Value); CHK_TYPE(uint64_t, a_u64Value); AssertCompile((a_iQword) < 4); (void)fAvxWrite; (void)fMcBegin; } while (0) 845 846 #define IEM_MC_STORE_YREG_U128(a_iYRegDst, a_iDQword, a_u128Value) do { CHK_YREG_IDX(a_iYRegDst); CHK_VAR(a_u128Value); CHK_TYPE(RTUINT128U, a_u128Value); (void)fAvxWrite; (void)fMcBegin; } while (0) 846 847 #define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Value) do { CHK_YREG_IDX(a_iYRegDst); CHK_VAR(a_u32Value); CHK_TYPE(uint32_t, a_u32Value); (void)fAvxWrite; (void)fMcBegin; } while (0) … … 848 849 #define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Value) do { CHK_YREG_IDX(a_iYRegDst); CHK_VAR(a_u128Value); CHK_TYPE(RTUINT128U, a_u128Value); (void)fAvxWrite; (void)fMcBegin; } while (0) 849 850 #define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Value) do { CHK_YREG_IDX(a_iYRegDst); CHK_VAR(a_u256Value); CHK_TYPE(RTUINT256U, a_u256Value); (void)fAvxWrite; (void)fMcBegin; } while (0) 851 #define IEM_MC_STORE_YREG_U32_U256(a_iYRegDst, a_iDwDst, a_u256Value, a_iDwSrc) do { CHK_XREG_IDX(a_iYRegDst); CHK_VAR(a_u256Value); CHK_TYPE(RTUINT256U, a_u256Value); AssertCompile((a_iDwDst) < RT_ELEMENTS((a_u256Value).au32)); AssertCompile((a_iDwSrc) < RT_ELEMENTS((a_u256Value).au32)); (void)fAvxWrite; (void)fMcBegin; } while (0) 852 #define IEM_MC_STORE_YREG_U64_U256(a_iYRegDst, a_iQwDst, a_u256Value, a_iQwSrc) do { CHK_XREG_IDX(a_iYRegDst); CHK_VAR(a_u256Value); CHK_TYPE(RTUINT256U, a_u256Value); AssertCompile((a_iQwDst) < RT_ELEMENTS((a_u256Value).au64)); AssertCompile((a_iQwSrc) < RT_ELEMENTS((a_u256Value).au64)); (void)fAvxWrite; (void)fMcBegin; } while (0) 850 853 #define IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX(a_iYRegDst, a_u8Value) do { CHK_YREG_IDX(a_iYRegDst); CHK_VAR(a_u8Value); CHK_TYPE(uint8_t, a_u8Value); (void)fAvxWrite; (void)fMcBegin; } while (0) 851 854 #define IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX(a_iYRegDst, a_u16Value) do { CHK_YREG_IDX(a_iYRegDst); CHK_VAR(a_u16Value); CHK_TYPE(uint16_t, a_u16Value); (void)fAvxWrite; (void)fMcBegin; } while (0) … … 866 869 #define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) do { CHK_YREG_IDX(a_iYRegDst); CHK_YREG_IDX(a_iYRegSrcHx); (void)fAvxWrite; (void)fAvxRead; (void)fMcBegin; } while (0) 867 870 #define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) do { CHK_YREG_IDX(a_iYRegDst); CHK_YREG_IDX(a_iYRegSrcHx); (void)fAvxWrite; (void)fAvxRead; (void)fMcBegin; } while (0) 871 #define IEM_MC_CLEAR_ZREG_256_UP(a_iZReg) do { CHK_YREG_IDX(a_iZReg); (void)fAvxWrite; (void)fMcBegin; } while (0) 868 872 869 873 #define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_VAR(a_GCPtrMem); CHK_VAR(a_u8Dst); AssertCompile(sizeof(a_u8Dst) == (sizeof(uint8_t))); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
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