- Timestamp:
- Mar 3, 2024 2:20:46 AM (7 months ago)
- Location:
- trunk/src/VBox/VMM/VMMAll
- Files:
-
- 2 edited
-
IEMAllInstOneByte.cpp.h (modified) (18 diffs)
-
target-x86/IEMAllN8veEmit-x86.h (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h
r103647 r103648 148 148 * operands. 149 149 */ 150 #define IEMOP_BODY_BINARY_rm_r8_RO(a_fnNormalU8, a_EmitterBasename, a_f RegRegNativeArchs, a_fMemRegNativeArchs) \150 #define IEMOP_BODY_BINARY_rm_r8_RO(a_fnNormalU8, a_EmitterBasename, a_fNativeArchs) \ 151 151 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \ 152 152 \ … … 160 160 IEM_MC_ARG(uint8_t, u8Src, 1); \ 161 161 IEM_MC_FETCH_GREG_U8(u8Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 162 IEM_MC_NATIVE_IF(a_f RegRegNativeArchs) { \162 IEM_MC_NATIVE_IF(a_fNativeArchs) { \ 163 163 IEM_MC_LOCAL(uint8_t, u8Dst); \ 164 164 IEM_MC_FETCH_GREG_U8(u8Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \ … … 167 167 IEM_MC_FETCH_EFLAGS(uEFlags); \ 168 168 IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u8Dst, u8Src, uEFlags, 8); \ 169 IEM_MC_STORE_GREG_U8(IEM_GET_MODRM_RM(pVCpu, bRm), u8Dst); \170 169 IEM_MC_COMMIT_EFLAGS(uEFlags); \ 171 170 } IEM_MC_NATIVE_ELSE() { \ … … 192 191 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ 193 192 IEMOP_HLP_DONE_DECODING(); \ 194 \ 195 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 196 IEM_MC_ARG(uint8_t const *, pu8Dst, 0); \ 197 IEM_MC_MEM_MAP_U8_RO(pu8Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 198 IEM_MC_ARG(uint8_t, u8Src, 1); \ 199 IEM_MC_FETCH_GREG_U8(u8Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 200 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2); \ 201 IEM_MC_FETCH_EFLAGS(EFlags); \ 202 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU8, pu8Dst, u8Src, pEFlags); \ 203 \ 204 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \ 205 IEM_MC_COMMIT_EFLAGS(EFlags); \ 193 IEM_MC_NATIVE_IF(0) { \ 194 IEM_MC_LOCAL(uint8_t, u8Dst); \ 195 IEM_MC_FETCH_MEM_U8(u8Dst, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 196 IEM_MC_LOCAL(uint8_t, u8SrcEmit); \ 197 IEM_MC_FETCH_GREG_U8(u8SrcEmit, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 198 /** @todo IEM_MC_LOCAL_EFLAGS(uEFlags); */ \ 199 IEM_MC_LOCAL(uint32_t, uEFlags); \ 200 IEM_MC_FETCH_EFLAGS(uEFlags); \ 201 IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u8Dst, u8SrcEmit, uEFlags, 8); \ 202 IEM_MC_COMMIT_EFLAGS(uEFlags); \ 203 } IEM_MC_NATIVE_ELSE() { \ 204 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 205 IEM_MC_ARG(uint8_t const *, pu8Dst, 0); \ 206 IEM_MC_MEM_MAP_U8_RO(pu8Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 207 IEM_MC_ARG(uint8_t, u8Src, 1); \ 208 IEM_MC_FETCH_GREG_U8(u8Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 209 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2); \ 210 IEM_MC_FETCH_EFLAGS(EFlags); \ 211 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU8, pu8Dst, u8Src, pEFlags); \ 212 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \ 213 IEM_MC_COMMIT_EFLAGS(EFlags); \ 214 } IEM_MC_NATIVE_ENDIF(); \ 206 215 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 207 216 IEM_MC_END(); \ … … 534 543 * memory/register as the destination. 535 544 */ 536 #define IEMOP_BODY_BINARY_rm_rv_RO(a_fnNormalU16, a_fnNormalU32, a_fnNormalU64, a_EmitterBasename, a_f RegRegNativeArchs, a_fMemRegNativeArchs) \545 #define IEMOP_BODY_BINARY_rm_rv_RO(a_fnNormalU16, a_fnNormalU32, a_fnNormalU64, a_EmitterBasename, a_fNativeArchs) \ 537 546 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \ 538 547 \ … … 549 558 IEM_MC_ARG(uint16_t, u16Src, 1); \ 550 559 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 551 IEM_MC_NATIVE_IF(a_f RegRegNativeArchs) { \560 IEM_MC_NATIVE_IF(a_fNativeArchs) { \ 552 561 IEM_MC_LOCAL(uint16_t, u16Dst); \ 553 562 IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \ … … 556 565 IEM_MC_FETCH_EFLAGS(uEFlags); \ 557 566 IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \ 558 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_RM(pVCpu, bRm), u16Dst); \559 567 IEM_MC_COMMIT_EFLAGS(uEFlags); \ 560 568 } IEM_MC_NATIVE_ELSE() { \ … … 574 582 IEM_MC_ARG(uint32_t, u32Src, 1); \ 575 583 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 576 IEM_MC_NATIVE_IF(a_f RegRegNativeArchs) { \584 IEM_MC_NATIVE_IF(a_fNativeArchs) { \ 577 585 IEM_MC_LOCAL(uint32_t, u32Dst); \ 578 586 IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \ … … 581 589 IEM_MC_FETCH_EFLAGS(uEFlags); \ 582 590 IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \ 583 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Dst); \584 591 IEM_MC_COMMIT_EFLAGS(uEFlags); \ 585 592 } IEM_MC_NATIVE_ELSE() { \ … … 599 606 IEM_MC_ARG(uint64_t, u64Src, 1); \ 600 607 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 601 IEM_MC_NATIVE_IF(a_f RegRegNativeArchs) { \608 IEM_MC_NATIVE_IF(a_fNativeArchs) { \ 602 609 IEM_MC_LOCAL(uint64_t, u64Dst); \ 603 610 IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \ … … 606 613 IEM_MC_FETCH_EFLAGS(uEFlags); \ 607 614 IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \ 608 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Dst); \609 615 IEM_MC_COMMIT_EFLAGS(uEFlags); \ 610 616 } IEM_MC_NATIVE_ELSE() { \ … … 635 641 case IEMMODE_16BIT: \ 636 642 IEM_MC_BEGIN(3, 3, 0, 0); \ 637 IEM_MC_ARG(uint16_t const *, pu16Dst, 0); \638 IEM_MC_ARG(uint16_t, u16Src, 1); \639 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2); \640 643 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 641 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \642 \643 644 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ 644 645 IEMOP_HLP_DONE_DECODING(); \ 645 IEM_MC_MEM_MAP_U16_RO(pu16Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 646 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 647 IEM_MC_FETCH_EFLAGS(EFlags); \ 648 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \ 649 \ 650 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \ 651 IEM_MC_COMMIT_EFLAGS(EFlags); \ 646 IEM_MC_NATIVE_IF(a_fNativeArchs) { \ 647 IEM_MC_LOCAL(uint16_t, u16Dst); \ 648 IEM_MC_FETCH_MEM_U16(u16Dst, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 649 IEM_MC_LOCAL(uint16_t, u16SrcEmit); \ 650 IEM_MC_FETCH_GREG_U16(u16SrcEmit, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 651 /** @todo IEM_MC_LOCAL_EFLAGS(uEFlags); */ \ 652 IEM_MC_LOCAL(uint32_t, uEFlags); \ 653 IEM_MC_FETCH_EFLAGS(uEFlags); \ 654 IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u16Dst, u16SrcEmit, uEFlags, 16); \ 655 IEM_MC_COMMIT_EFLAGS(uEFlags); \ 656 } IEM_MC_NATIVE_ELSE() { \ 657 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 658 IEM_MC_ARG(uint16_t const *, pu16Dst, 0); \ 659 IEM_MC_MEM_MAP_U16_RO(pu16Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 660 IEM_MC_ARG(uint16_t, u16Src, 1); \ 661 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 662 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2); \ 663 IEM_MC_FETCH_EFLAGS(EFlags); \ 664 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \ 665 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \ 666 IEM_MC_COMMIT_EFLAGS(EFlags); \ 667 } IEM_MC_NATIVE_ENDIF(); \ 652 668 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 653 669 IEM_MC_END(); \ … … 656 672 case IEMMODE_32BIT: \ 657 673 IEM_MC_BEGIN(3, 3, IEM_MC_F_MIN_386, 0); \ 658 IEM_MC_ARG(uint32_t const *, pu32Dst, 0); \659 IEM_MC_ARG(uint32_t, u32Src, 1); \660 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2); \661 674 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 662 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \663 \664 675 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ 665 676 IEMOP_HLP_DONE_DECODING(); \ 666 IEM_MC_MEM_MAP_U32_RO(pu32Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 667 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 668 IEM_MC_FETCH_EFLAGS(EFlags); \ 669 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU32, pu32Dst, u32Src, pEFlags); \ 670 \ 671 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \ 672 IEM_MC_COMMIT_EFLAGS(EFlags); \ 677 IEM_MC_NATIVE_IF(a_fNativeArchs) { \ 678 IEM_MC_LOCAL(uint32_t, u32Dst); \ 679 IEM_MC_FETCH_MEM_U32(u32Dst, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 680 IEM_MC_LOCAL(uint32_t, u32SrcEmit); \ 681 IEM_MC_FETCH_GREG_U32(u32SrcEmit, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 682 /** @todo IEM_MC_LOCAL_EFLAGS(uEFlags); */ \ 683 IEM_MC_LOCAL(uint32_t, uEFlags); \ 684 IEM_MC_FETCH_EFLAGS(uEFlags); \ 685 IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u32Dst, u32SrcEmit, uEFlags, 32); \ 686 IEM_MC_COMMIT_EFLAGS(uEFlags); \ 687 } IEM_MC_NATIVE_ELSE() { \ 688 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 689 IEM_MC_ARG(uint32_t const *, pu32Dst, 0); \ 690 IEM_MC_MEM_MAP_U32_RO(pu32Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 691 IEM_MC_ARG(uint32_t, u32Src, 1); \ 692 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 693 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2); \ 694 IEM_MC_FETCH_EFLAGS(EFlags); \ 695 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU32, pu32Dst, u32Src, pEFlags); \ 696 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \ 697 IEM_MC_COMMIT_EFLAGS(EFlags); \ 698 } IEM_MC_NATIVE_ENDIF(); \ 673 699 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 674 700 IEM_MC_END(); \ … … 677 703 case IEMMODE_64BIT: \ 678 704 IEM_MC_BEGIN(3, 3, IEM_MC_F_64BIT, 0); \ 679 IEM_MC_ARG(uint64_t const *, pu64Dst, 0); \680 IEM_MC_ARG(uint64_t, u64Src, 1); \681 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2); \682 705 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 683 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \684 \685 706 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ 686 707 IEMOP_HLP_DONE_DECODING(); \ 687 IEM_MC_MEM_MAP_U64_RO(pu64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 688 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 689 IEM_MC_FETCH_EFLAGS(EFlags); \ 690 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \ 691 \ 692 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \ 693 IEM_MC_COMMIT_EFLAGS(EFlags); \ 708 IEM_MC_NATIVE_IF(a_fNativeArchs) { \ 709 IEM_MC_LOCAL(uint64_t, u64Dst); \ 710 IEM_MC_FETCH_MEM_U64(u64Dst, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 711 IEM_MC_LOCAL(uint64_t, u64SrcEmit); \ 712 IEM_MC_FETCH_GREG_U64(u64SrcEmit, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 713 /** @todo IEM_MC_LOCAL_EFLAGS(uEFlags); */ \ 714 IEM_MC_LOCAL(uint32_t, uEFlags); \ 715 IEM_MC_FETCH_EFLAGS(uEFlags); \ 716 IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u64Dst, u64SrcEmit, uEFlags, 64); \ 717 IEM_MC_COMMIT_EFLAGS(uEFlags); \ 718 } IEM_MC_NATIVE_ELSE() { \ 719 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 720 IEM_MC_ARG(uint64_t const *, pu64Dst, 0); \ 721 IEM_MC_MEM_MAP_U64_RO(pu64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 722 IEM_MC_ARG(uint64_t, u64Src, 1); \ 723 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 724 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2); \ 725 IEM_MC_FETCH_EFLAGS(EFlags); \ 726 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \ 727 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \ 728 IEM_MC_COMMIT_EFLAGS(EFlags); \ 729 } IEM_MC_NATIVE_ENDIF(); \ 694 730 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 695 731 IEM_MC_END(); \ … … 1743 1779 { 1744 1780 IEMOP_MNEMONIC(cmp_Eb_Gb, "cmp Eb,Gb"); 1745 IEMOP_BODY_BINARY_rm_r8_RO(iemAImpl_cmp_u8, cmp, 0 , 0);1781 IEMOP_BODY_BINARY_rm_r8_RO(iemAImpl_cmp_u8, cmp, 0); 1746 1782 } 1747 1783 … … 1754 1790 { 1755 1791 IEMOP_MNEMONIC(cmp_Ev_Gv, "cmp Ev,Gv"); 1756 IEMOP_BODY_BINARY_rm_rv_RO(iemAImpl_cmp_u16, iemAImpl_cmp_u32, iemAImpl_cmp_u64, cmp, 0 , 0);1792 IEMOP_BODY_BINARY_rm_rv_RO(iemAImpl_cmp_u16, iemAImpl_cmp_u32, iemAImpl_cmp_u64, cmp, 0); 1757 1793 } 1758 1794 … … 5325 5361 IEMOP_MNEMONIC(test_Eb_Gb, "test Eb,Gb"); 5326 5362 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF); 5327 IEMOP_BODY_BINARY_rm_r8_RO(iemAImpl_test_u8, test, 0, 0);5363 IEMOP_BODY_BINARY_rm_r8_RO(iemAImpl_test_u8, test, RT_ARCH_VAL_AMD64); 5328 5364 } 5329 5365 … … 5337 5373 IEMOP_MNEMONIC(test_Ev_Gv, "test Ev,Gv"); 5338 5374 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF); 5339 IEMOP_BODY_BINARY_rm_rv_RO(iemAImpl_test_u16, iemAImpl_test_u32, iemAImpl_test_u64, test, 0, 0);5375 IEMOP_BODY_BINARY_rm_rv_RO(iemAImpl_test_u16, iemAImpl_test_u32, iemAImpl_test_u64, test, RT_ARCH_VAL_AMD64); 5340 5376 } 5341 5377 -
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h
r103646 r103648 129 129 { 130 130 /* 131 * The AND instruction will clear OF, CF and AF (latter is offundefined),131 * The AND instruction will clear OF, CF and AF (latter is undefined), 132 132 * so we don't need the initial destination value. 133 133 * … … 191 191 uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits) 192 192 { 193 RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits); 194 AssertFailed(); 195 return iemNativeEmitBrk(pReNative, off, 0x666); 193 /* 194 * The TESTS instruction will clear OF, CF and AF (latter is undefined), 195 * so we don't need the initial destination value. 196 * 197 * On AMD64 we use the matching native instruction. 198 * 199 * On ARM64 we need a real register for the AND result so we can calculate 200 * PF correctly for it. This means that we have to use a three operand 201 * AND variant, which makes the code widely different from AMD64. 202 */ 203 /** @todo we could use ANDS on ARM64 and get the ZF for free for all 204 * variants, and SF for 32-bit and 64-bit. */ 205 uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/); 206 uint8_t const idxRegSrc = iemNativeVarRegisterAcquire(pReNative, idxVarSrc, &off, true /*fInitialized*/); 207 #ifndef RT_ARCH_AMD64 208 uint8_t const idxRegResult = iemNativeRegAllocTmp(pReNative, &off); 209 #endif 210 // off = iemNativeEmitBrk(pReNative, off, 0x2222); 211 PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, RT_ARCH_VAL == RT_ARCH_VAL_AMD64 ? 4 : 1); 212 #ifdef RT_ARCH_ARM64 213 pCodeBuf[off++] = Armv8A64MkInstrAnd(idxRegResult, idxRegDst, idxRegSrc, cOpBits > 32 /*f64Bit*/); 214 215 #elif defined(RT_ARCH_AMD64) 216 switch (cOpBits) 217 { 218 case 16: 219 pCodeBuf[off++] = X86_OP_PRF_SIZE_OP; 220 RT_FALL_THRU(); 221 case 32: 222 if (idxRegDst >= 8 || idxRegSrc >= 8) 223 pCodeBuf[off++] = (idxRegDst >= 8 ? X86_OP_REX_B : 0) | (idxRegSrc >= 8 ? X86_OP_REX_R : 0); 224 pCodeBuf[off++] = 0x85; 225 break; 226 227 default: AssertFailed(); RT_FALL_THRU(); 228 case 64: 229 pCodeBuf[off++] = X86_OP_REX_W | (idxRegDst >= 8 ? X86_OP_REX_B : 0) | (idxRegSrc >= 8 ? X86_OP_REX_R : 0); 230 pCodeBuf[off++] = 0x85; 231 break; 232 233 case 8: 234 if (idxRegDst >= 8 || idxRegSrc >= 8) 235 pCodeBuf[off++] = (idxRegDst >= 8 ? X86_OP_REX_B : 0) | (idxRegSrc >= 8 ? X86_OP_REX_R : 0); 236 else if (idxRegDst >= 4 || idxRegSrc >= 4) 237 pCodeBuf[off++] = X86_OP_REX; 238 pCodeBuf[off++] = 0x84; 239 break; 240 } 241 pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, idxRegSrc & 7, idxRegDst & 7); 242 #else 243 # error "port me" 244 #endif 245 IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off); 246 iemNativeVarRegisterRelease(pReNative, idxVarSrc); 247 iemNativeVarRegisterRelease(pReNative, idxVarDst); 248 249 #ifdef RT_ARCH_AMD64 250 off = iemNativeEmitEFlagsForLogical(pReNative, off, idxVarEfl, cOpBits, UINT8_MAX); 251 #else 252 off = iemNativeEmitEFlagsForLogical(pReNative, off, idxVarEfl, cOpBits, idxRegResult); 253 iemNativeRegFreeTmp(pReNative, idxRegResult); 254 #endif 255 return off; 196 256 } 197 257 … … 202 262 { 203 263 /* 204 * The OR instruction will clear OF, CF and AF (latter is offundefined),264 * The OR instruction will clear OF, CF and AF (latter is undefined), 205 265 * so we don't need the initial destination value. 206 266 * … … 263 323 { 264 324 /* 265 * The XOR instruction will clear OF, CF and AF (latter is offundefined),325 * The XOR instruction will clear OF, CF and AF (latter is undefined), 266 326 * so we don't need the initial destination value. 267 327 *
Note:
See TracChangeset
for help on using the changeset viewer.

