- Timestamp:
- Mar 1, 2024 10:06:51 PM (7 months ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 5 edited
-
Makefile.kmk (modified) (1 diff)
-
VMMAll/IEMAllInstCommonBodyMacros.h (modified) (4 diffs)
-
VMMAll/IEMAllInstOneByte.cpp.h (modified) (8 diffs)
-
VMMAll/IEMAllInstTwoByte0f.cpp.h (modified) (4 diffs)
-
VMMAll/target-x86/IEMAllN8veEmit-x86.h (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/Makefile.kmk
r103377 r103640 625 625 $(PATH_SUB_CURRENT)/VMMAll/IEMAllN8vePython.py \ 626 626 $(PATH_SUB_CURRENT)/VMMAll/IEMAllInstCommon.cpp.h \ 627 $(PATH_SUB_CURRENT)/VMMAll/IEMAllInstCommonBodyMacros.h \ 627 628 $(if-expr !defined(IEM_WITHOUT_3DNOW) ,$(PATH_SUB_CURRENT)/VMMAll/IEMAllInst3DNow.cpp.h,) \ 628 629 $(if-expr !defined(IEM_WITHOUT_THREE_0F_38),$(PATH_SUB_CURRENT)/VMMAll/IEMAllInstThree0f38.cpp.h,) \ -
trunk/src/VBox/VMM/VMMAll/IEMAllInstCommonBodyMacros.h
r103548 r103640 39 39 * @note Used both in OneByte and TwoByte0f. 40 40 */ 41 #define IEMOP_BODY_BINARY_rv_rm(a_bRm, a_fnNormalU16, a_fnNormalU32, a_fnNormalU64, a_fModifiesDstReg, a_f16BitMcFlag ) \41 #define IEMOP_BODY_BINARY_rv_rm(a_bRm, a_fnNormalU16, a_fnNormalU32, a_fnNormalU64, a_fModifiesDstReg, a_f16BitMcFlag, a_EmitterBasename, a_fNativeArchs) \ 42 42 /* \ 43 43 * If rm is denoting a register, no more instruction bytes. \ … … 50 50 IEM_MC_BEGIN(3, 0, a_f16BitMcFlag, 0); \ 51 51 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 52 IEM_MC_ARG(uint16_t *, pu16Dst, 0); \ 53 IEM_MC_ARG(uint16_t, u16Src, 1); \ 54 IEM_MC_ARG(uint32_t *, pEFlags, 2); \ 55 \ 52 IEM_MC_ARG(uint16_t, u16Src, 1); \ 56 53 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \ 57 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \ 58 IEM_MC_REF_EFLAGS(pEFlags); \ 59 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \ 60 \ 54 IEM_MC_NATIVE_IF(a_fNativeArchs) { \ 55 IEM_MC_LOCAL(uint16_t, u16Dst); \ 56 IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 57 /** @todo IEM_MC_LOCAL_EFLAGS(uEFlags); */ \ 58 IEM_MC_LOCAL(uint32_t, uEFlags); \ 59 IEM_MC_FETCH_EFLAGS(uEFlags); \ 60 IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \ 61 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Dst); \ 62 IEM_MC_COMMIT_EFLAGS(uEFlags); \ 63 } IEM_MC_NATIVE_ELSE() { \ 64 IEM_MC_ARG(uint16_t *, pu16Dst, 0); \ 65 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 66 IEM_MC_ARG(uint32_t *, pEFlags, 2); \ 67 IEM_MC_REF_EFLAGS(pEFlags); \ 68 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \ 69 } IEM_MC_NATIVE_ENDIF(); \ 61 70 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 62 71 IEM_MC_END(); \ … … 66 75 IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); \ 67 76 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 68 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \ 69 IEM_MC_ARG(uint32_t, u32Src, 1); \ 70 IEM_MC_ARG(uint32_t *, pEFlags, 2); \ 71 \ 77 IEM_MC_ARG(uint32_t, u32Src, 1); \ 72 78 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \ 73 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \ 74 IEM_MC_REF_EFLAGS(pEFlags); \ 75 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU32, pu32Dst, u32Src, pEFlags); \ 76 \ 77 if (a_fModifiesDstReg) \ 78 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, a_bRm)); \ 79 IEM_MC_NATIVE_IF(a_fNativeArchs) { \ 80 IEM_MC_LOCAL(uint32_t, u32Dst); \ 81 IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 82 /** @todo IEM_MC_LOCAL_EFLAGS(uEFlags); */ \ 83 IEM_MC_LOCAL(uint32_t, uEFlags); \ 84 IEM_MC_FETCH_EFLAGS(uEFlags); \ 85 IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \ 86 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Dst); \ 87 IEM_MC_COMMIT_EFLAGS(uEFlags); \ 88 } IEM_MC_NATIVE_ELSE() { \ 89 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \ 90 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 91 IEM_MC_ARG(uint32_t *, pEFlags, 2); \ 92 IEM_MC_REF_EFLAGS(pEFlags); \ 93 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU32, pu32Dst, u32Src, pEFlags); \ 94 if (a_fModifiesDstReg) \ 95 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, a_bRm)); \ 96 } IEM_MC_NATIVE_ENDIF(); \ 79 97 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 80 98 IEM_MC_END(); \ … … 84 102 IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \ 85 103 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 86 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \ 87 IEM_MC_ARG(uint64_t, u64Src, 1); \ 88 IEM_MC_ARG(uint32_t *, pEFlags, 2); \ 89 \ 104 IEM_MC_ARG(uint64_t, u64Src, 1); \ 90 105 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \ 91 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \ 92 IEM_MC_REF_EFLAGS(pEFlags); \ 93 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \ 94 \ 106 IEM_MC_NATIVE_IF(a_fNativeArchs) { \ 107 IEM_MC_LOCAL(uint64_t, u64Dst); \ 108 IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 109 /** @todo IEM_MC_LOCAL_EFLAGS(uEFlags); */ \ 110 IEM_MC_LOCAL(uint32_t, uEFlags); \ 111 IEM_MC_FETCH_EFLAGS(uEFlags); \ 112 IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \ 113 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Dst); \ 114 IEM_MC_COMMIT_EFLAGS(uEFlags); \ 115 } IEM_MC_NATIVE_ELSE() { \ 116 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \ 117 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 118 IEM_MC_ARG(uint32_t *, pEFlags, 2); \ 119 IEM_MC_REF_EFLAGS(pEFlags); \ 120 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \ 121 } IEM_MC_NATIVE_ENDIF(); \ 95 122 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 96 123 IEM_MC_END(); \ -
trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h
r103635 r103640 771 771 IEMOP_MNEMONIC2(RM, ADD, add, Gv, Ev, DISOPTYPE_HARMLESS, 0); 772 772 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 773 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_add_u16, iemAImpl_add_u32, iemAImpl_add_u64, 1, 0 );773 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_add_u16, iemAImpl_add_u32, iemAImpl_add_u64, 1, 0, add, 0); 774 774 } 775 775 … … 898 898 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF); 899 899 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 900 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_or_u16, iemAImpl_or_u32, iemAImpl_or_u64, 1, 0 );900 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_or_u16, iemAImpl_or_u32, iemAImpl_or_u64, 1, 0, or, 0); 901 901 } 902 902 … … 1052 1052 IEMOP_MNEMONIC2(RM, ADC, adc, Gv, Ev, DISOPTYPE_HARMLESS, 0); 1053 1053 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 1054 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_adc_u16, iemAImpl_adc_u32, iemAImpl_adc_u64, 1, 0 );1054 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_adc_u16, iemAImpl_adc_u32, iemAImpl_adc_u64, 1, 0, adc, 0); 1055 1055 } 1056 1056 … … 1157 1157 IEMOP_MNEMONIC2(RM, SBB, sbb, Gv, Ev, DISOPTYPE_HARMLESS, 0); 1158 1158 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 1159 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_sbb_u16, iemAImpl_sbb_u32, iemAImpl_sbb_u64, 1, 0 );1159 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_sbb_u16, iemAImpl_sbb_u32, iemAImpl_sbb_u64, 1, 0, sbb, 0); 1160 1160 } 1161 1161 … … 1266 1266 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF); 1267 1267 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 1268 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_and_u16, iemAImpl_and_u32, iemAImpl_and_u64, 1, 0 );1268 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_and_u16, iemAImpl_and_u32, iemAImpl_and_u64, 1, 0, and, 0); 1269 1269 } 1270 1270 … … 1378 1378 IEMOP_MNEMONIC2(RM, SUB, sub, Gv, Ev, DISOPTYPE_HARMLESS, 0); 1379 1379 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 1380 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_sub_u16, iemAImpl_sub_u32, iemAImpl_sub_u64, 1, 0 );1380 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_sub_u16, iemAImpl_sub_u32, iemAImpl_sub_u64, 1, 0, sub, 0); 1381 1381 } 1382 1382 … … 1545 1545 } 1546 1546 1547 //I E M OP_BODY_BINARY_rv_rm(bRm, iemAImpl_xor_u16, iemAImpl_xor_u32, iemAImpl_xor_u64, 1, 0); - restore later. 1548 /* 1549 * START TEMP EXPERIMENTAL CODE 1550 */ 1551 if (IEM_IS_MODRM_REG_MODE(bRm)) 1552 { 1553 switch (pVCpu->iem.s.enmEffOpSize) 1554 { 1555 case IEMMODE_16BIT: 1556 IEM_MC_BEGIN(3, 0, 0, 0); 1557 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1558 IEM_MC_ARG(uint16_t, u16Src, 1); 1559 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 1560 IEM_MC_NATIVE_IF(RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64) { 1561 IEM_MC_LOCAL(uint16_t, u16Dst); 1562 IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1563 /// @todo IEM_MC_LOCAL_EFLAGS(uEFlags); 1564 IEM_MC_LOCAL(uint32_t, uEFlags); 1565 IEM_MC_FETCH_EFLAGS(uEFlags); 1566 IEM_MC_NATIVE_EMIT_4(iemNativeEmit_xor_r_r_efl, u16Dst, u16Src, uEFlags, 16); 1567 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Dst); 1568 IEM_MC_COMMIT_EFLAGS(uEFlags); 1569 } IEM_MC_NATIVE_ELSE() { 1570 IEM_MC_ARG(uint16_t *, pu16Dst, 0); 1571 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1572 IEM_MC_ARG(uint32_t *, pEFlags, 2); 1573 IEM_MC_REF_EFLAGS(pEFlags); 1574 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xor_u16, pu16Dst, u16Src, pEFlags); 1575 } IEM_MC_NATIVE_ENDIF(); 1576 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1577 IEM_MC_END(); 1578 break; 1579 1580 case IEMMODE_32BIT: 1581 IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); 1582 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1583 IEM_MC_ARG(uint32_t, u32Src, 1); 1584 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 1585 IEM_MC_NATIVE_IF(RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64) { 1586 IEM_MC_LOCAL(uint32_t, u32Dst); 1587 IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1588 /// @todo IEM_MC_LOCAL_EFLAGS(uEFlags); 1589 IEM_MC_LOCAL(uint32_t, uEFlags); 1590 IEM_MC_FETCH_EFLAGS(uEFlags); 1591 IEM_MC_NATIVE_EMIT_4(iemNativeEmit_xor_r_r_efl, u32Dst, u32Src, uEFlags, 32); 1592 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Dst); 1593 IEM_MC_COMMIT_EFLAGS(uEFlags); 1594 } IEM_MC_NATIVE_ELSE() { 1595 IEM_MC_ARG(uint32_t *, pu32Dst, 0); 1596 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1597 IEM_MC_ARG(uint32_t *, pEFlags, 2); 1598 IEM_MC_REF_EFLAGS(pEFlags); 1599 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xor_u32, pu32Dst, u32Src, pEFlags); 1600 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 1601 } IEM_MC_NATIVE_ENDIF(); 1602 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1603 IEM_MC_END(); 1604 break; 1605 1606 case IEMMODE_64BIT: 1607 IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); 1608 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1609 IEM_MC_ARG(uint64_t, u64Src, 1); 1610 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 1611 IEM_MC_NATIVE_IF(RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64) { 1612 IEM_MC_LOCAL(uint64_t, u64Dst); 1613 IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1614 /// @todo IEM_MC_LOCAL_EFLAGS(uEFlags); 1615 IEM_MC_LOCAL(uint32_t, uEFlags); 1616 IEM_MC_FETCH_EFLAGS(uEFlags); 1617 IEM_MC_NATIVE_EMIT_4(iemNativeEmit_xor_r_r_efl, u64Dst, u64Src, uEFlags, 64); 1618 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Dst); 1619 IEM_MC_COMMIT_EFLAGS(uEFlags); 1620 } IEM_MC_NATIVE_ELSE() { 1621 IEM_MC_ARG(uint64_t *, pu64Dst, 0); 1622 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1623 IEM_MC_ARG(uint32_t *, pEFlags, 2); 1624 IEM_MC_REF_EFLAGS(pEFlags); 1625 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xor_u64, pu64Dst, u64Src, pEFlags); 1626 } IEM_MC_NATIVE_ENDIF(); 1627 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1628 IEM_MC_END(); 1629 break; 1630 1631 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 1632 } 1633 } 1634 else 1635 { 1636 /* 1637 * We're accessing memory. 1638 */ 1639 switch (pVCpu->iem.s.enmEffOpSize) 1640 { 1641 case IEMMODE_16BIT: 1642 IEM_MC_BEGIN(3, 1, 0, 0); 1643 IEM_MC_ARG(uint16_t *, pu16Dst, 0); 1644 IEM_MC_ARG(uint16_t, u16Src, 1); 1645 IEM_MC_ARG(uint32_t *, pEFlags, 2); 1646 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); 1647 1648 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 1649 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1650 IEM_MC_FETCH_MEM_U16(u16Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 1651 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1652 IEM_MC_REF_EFLAGS(pEFlags); 1653 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xor_u16, pu16Dst, u16Src, pEFlags); 1654 1655 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1656 IEM_MC_END(); 1657 break; 1658 1659 case IEMMODE_32BIT: 1660 IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386, 0); 1661 IEM_MC_ARG(uint32_t *, pu32Dst, 0); 1662 IEM_MC_ARG(uint32_t, u32Src, 1); 1663 IEM_MC_ARG(uint32_t *, pEFlags, 2); 1664 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); 1665 1666 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 1667 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1668 IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 1669 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1670 IEM_MC_REF_EFLAGS(pEFlags); 1671 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xor_u32, pu32Dst, u32Src, pEFlags); 1672 1673 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 1674 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1675 IEM_MC_END(); 1676 break; 1677 1678 case IEMMODE_64BIT: 1679 IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT, 0); 1680 IEM_MC_ARG(uint64_t *, pu64Dst, 0); 1681 IEM_MC_ARG(uint64_t, u64Src, 1); 1682 IEM_MC_ARG(uint32_t *, pEFlags, 2); 1683 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); 1684 1685 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 1686 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1687 IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 1688 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1689 IEM_MC_REF_EFLAGS(pEFlags); 1690 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xor_u64, pu64Dst, u64Src, pEFlags); 1691 1692 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1693 IEM_MC_END(); 1694 break; 1695 1696 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 1697 } 1698 } 1699 /* END TEMP EXPERIMENTAL CODE */ 1547 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_xor_u16, iemAImpl_xor_u32, iemAImpl_xor_u64, 1, 0, xor, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64); 1700 1548 } 1701 1549 … … 1837 1685 IEMOP_MNEMONIC(cmp_Gv_Ev, "cmp Gv,Ev"); 1838 1686 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 1839 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_cmp_u16, iemAImpl_cmp_u32, iemAImpl_cmp_u64, 0, 0 );1687 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_cmp_u16, iemAImpl_cmp_u32, iemAImpl_cmp_u64, 0, 0, cmp, 0); 1840 1688 } 1841 1689 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h
r103592 r103640 10446 10446 const IEMOPBINSIZES * const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_eflags); 10447 10447 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 10448 IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, 1, IEM_MC_F_MIN_386 );10448 IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, 1, IEM_MC_F_MIN_386, imul, 0); 10449 10449 } 10450 10450 … … 10953 10953 const IEMOPBINSIZES * const pImpl = IEM_SELECT_HOST_OR_FALLBACK(fPopCnt, &s_Native, &s_Fallback); 10954 10954 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 10955 IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, 1, IEM_MC_F_NOT_286_OR_OLDER );10955 IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, 1, IEM_MC_F_NOT_286_OR_OLDER, popcnt, 0); 10956 10956 } 10957 10957 … … 11628 11628 IEM_GET_HOST_CPU_FEATURES(pVCpu)->fBmi1); 11629 11629 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 11630 IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, 1, IEM_MC_F_NOT_286_OR_OLDER );11630 IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, 1, IEM_MC_F_NOT_286_OR_OLDER, tzcnt, 0); 11631 11631 } 11632 11632 … … 11683 11683 IEM_GET_HOST_CPU_FEATURES(pVCpu)->fBmi1); 11684 11684 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 11685 IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, 1, IEM_MC_F_NOT_286_OR_OLDER );11685 IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, 1, IEM_MC_F_NOT_286_OR_OLDER, lzcnt, 0); 11686 11686 } 11687 11687 -
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h
r103637 r103640 123 123 } 124 124 125 /** @todo move this somewhere else ... */ 125 126 DECL_INLINE_THROW(uint32_t) 127 iemNativeEmit_and_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, 128 uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits) 129 { 130 RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits); 131 AssertFailed(); 132 return iemNativeEmitBrk(pReNative, off, 0x666); 133 } 134 135 136 DECL_INLINE_THROW(uint32_t) 137 iemNativeEmit_test_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, 138 uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits) 139 { 140 RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits); 141 AssertFailed(); 142 return iemNativeEmitBrk(pReNative, off, 0x666); 143 } 144 145 146 DECL_INLINE_THROW(uint32_t) 147 iemNativeEmit_or_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, 148 uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits) 149 { 150 RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits); 151 AssertFailed(); 152 return iemNativeEmitBrk(pReNative, off, 0x666); 153 } 154 155 126 156 DECL_INLINE_THROW(uint32_t) 127 157 iemNativeEmit_xor_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, … … 184 214 } 185 215 216 217 DECL_INLINE_THROW(uint32_t) 218 iemNativeEmit_add_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, 219 uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits) 220 { 221 RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits); 222 AssertFailed(); 223 return iemNativeEmitBrk(pReNative, off, 0x666); 224 } 225 226 227 DECL_INLINE_THROW(uint32_t) 228 iemNativeEmit_adc_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, 229 uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits) 230 { 231 RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits); 232 AssertFailed(); 233 return iemNativeEmitBrk(pReNative, off, 0x666); 234 } 235 236 237 DECL_INLINE_THROW(uint32_t) 238 iemNativeEmit_sub_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, 239 uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits) 240 { 241 RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits); 242 AssertFailed(); 243 return iemNativeEmitBrk(pReNative, off, 0x666); 244 } 245 246 247 DECL_INLINE_THROW(uint32_t) 248 iemNativeEmit_cmp_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, 249 uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits) 250 { 251 RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits); 252 AssertFailed(); 253 return iemNativeEmitBrk(pReNative, off, 0x666); 254 } 255 256 257 DECL_INLINE_THROW(uint32_t) 258 iemNativeEmit_sbb_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, 259 uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits) 260 { 261 RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits); 262 AssertFailed(); 263 return iemNativeEmitBrk(pReNative, off, 0x666); 264 } 265 266 267 DECL_INLINE_THROW(uint32_t) 268 iemNativeEmit_imul_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, 269 uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits) 270 { 271 RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits); 272 AssertFailed(); 273 return iemNativeEmitBrk(pReNative, off, 0x666); 274 } 275 276 277 DECL_INLINE_THROW(uint32_t) 278 iemNativeEmit_popcnt_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, 279 uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits) 280 { 281 RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits); 282 AssertFailed(); 283 return iemNativeEmitBrk(pReNative, off, 0x666); 284 } 285 286 287 DECL_INLINE_THROW(uint32_t) 288 iemNativeEmit_tzcnt_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, 289 uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits) 290 { 291 RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits); 292 AssertFailed(); 293 return iemNativeEmitBrk(pReNative, off, 0x666); 294 } 295 296 297 DECL_INLINE_THROW(uint32_t) 298 iemNativeEmit_lzcnt_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, 299 uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits) 300 { 301 RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits); 302 AssertFailed(); 303 return iemNativeEmitBrk(pReNative, off, 0x666); 304 } 305 306 186 307 #endif /* !VMM_INCLUDED_SRC_VMMAll_target_x86_IEMAllN8veEmit_x86_h */
Note:
See TracChangeset
for help on using the changeset viewer.

