- Timestamp:
- Feb 29, 2024 1:01:56 PM (7 months ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 9 edited
-
VMMAll/IEMAllInstOneByte.cpp.h (modified) (1 diff)
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VMMAll/IEMAllInstPython.py (modified) (11 diffs)
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VMMAll/IEMAllN8veLiveness.cpp (modified) (1 diff)
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VMMAll/IEMAllN8vePython.py (modified) (2 diffs)
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VMMAll/IEMAllN8veRecompiler.cpp (modified) (1 diff)
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VMMAll/IEMAllThrdPython.py (modified) (5 diffs)
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include/IEMMc.h (modified) (2 diffs)
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include/IEMN8veRecompilerEmit.h (modified) (2 diffs)
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testcase/tstIEMCheckMc.cpp (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h
r103590 r103613 1544 1544 } 1545 1545 } 1546 IEMOP_BODY_BINARY_rv_rm(bRm, iemAImpl_xor_u16, iemAImpl_xor_u32, iemAImpl_xor_u64, 1, 0); 1546 1547 //I E M OP_BODY_BINARY_rv_rm(bRm, iemAImpl_xor_u16, iemAImpl_xor_u32, iemAImpl_xor_u64, 1, 0); - restore later. 1548 /* 1549 * START TEMP EXPERIMENTAL CODE 1550 */ 1551 if (IEM_IS_MODRM_REG_MODE(bRm)) 1552 { 1553 switch (pVCpu->iem.s.enmEffOpSize) 1554 { 1555 case IEMMODE_16BIT: 1556 IEM_MC_BEGIN(3, 0, 0, 0); 1557 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1558 IEM_MC_ARG(uint16_t *, pu16Dst, 0); 1559 IEM_MC_ARG(uint16_t, u16Src, 1); 1560 IEM_MC_ARG(uint32_t *, pEFlags, 2); 1561 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 1562 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1563 IEM_MC_REF_EFLAGS(pEFlags); 1564 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xor_u16, pu16Dst, u16Src, pEFlags); 1565 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1566 IEM_MC_END(); 1567 break; 1568 1569 case IEMMODE_32BIT: 1570 IEM_MC_BEGIN(3, 0, IEM_MC_F_MIN_386, 0); 1571 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1572 IEM_MC_ARG(uint32_t, u32Src, 1); 1573 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 1574 IEM_MC_NATIVE_IF(RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64) { 1575 IEM_MC_LOCAL(uint32_t, u32Dst); 1576 IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1577 /// @todo IEM_MC_LOCAL_EFLAGS(uEFlags); 1578 IEM_MC_LOCAL(uint32_t, uEFlags); 1579 IEM_MC_FETCH_EFLAGS(uEFlags); 1580 IEM_MC_NATIVE_EMIT_4(iemNativeEmit_xor_r_r_efl, u32Dst, u32Src, uEFlags, 32); 1581 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Dst); 1582 IEM_MC_COMMIT_EFLAGS(uEFlags); 1583 } IEM_MC_NATIVE_ELSE() { 1584 IEM_MC_ARG(uint32_t *, pu32Dst, 0); 1585 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1586 IEM_MC_ARG(uint32_t *, pEFlags, 2); 1587 IEM_MC_REF_EFLAGS(pEFlags); 1588 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xor_u32, pu32Dst, u32Src, pEFlags); 1589 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 1590 } IEM_MC_NATIVE_ENDIF(); 1591 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1592 IEM_MC_END(); 1593 break; 1594 1595 case IEMMODE_64BIT: 1596 IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); 1597 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1598 IEM_MC_ARG(uint64_t *, pu64Dst, 0); 1599 IEM_MC_ARG(uint64_t, u64Src, 1); 1600 IEM_MC_ARG(uint32_t *, pEFlags, 2); 1601 1602 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 1603 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1604 IEM_MC_REF_EFLAGS(pEFlags); 1605 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xor_u64, pu64Dst, u64Src, pEFlags); 1606 1607 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1608 IEM_MC_END(); 1609 break; 1610 1611 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 1612 } 1613 } 1614 else 1615 { 1616 /* 1617 * We're accessing memory. 1618 */ 1619 switch (pVCpu->iem.s.enmEffOpSize) 1620 { 1621 case IEMMODE_16BIT: 1622 IEM_MC_BEGIN(3, 1, 0, 0); 1623 IEM_MC_ARG(uint16_t *, pu16Dst, 0); 1624 IEM_MC_ARG(uint16_t, u16Src, 1); 1625 IEM_MC_ARG(uint32_t *, pEFlags, 2); 1626 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); 1627 1628 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 1629 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1630 IEM_MC_FETCH_MEM_U16(u16Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 1631 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1632 IEM_MC_REF_EFLAGS(pEFlags); 1633 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xor_u16, pu16Dst, u16Src, pEFlags); 1634 1635 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1636 IEM_MC_END(); 1637 break; 1638 1639 case IEMMODE_32BIT: 1640 IEM_MC_BEGIN(3, 1, IEM_MC_F_MIN_386, 0); 1641 IEM_MC_ARG(uint32_t *, pu32Dst, 0); 1642 IEM_MC_ARG(uint32_t, u32Src, 1); 1643 IEM_MC_ARG(uint32_t *, pEFlags, 2); 1644 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); 1645 1646 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 1647 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1648 IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 1649 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1650 IEM_MC_REF_EFLAGS(pEFlags); 1651 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xor_u32, pu32Dst, u32Src, pEFlags); 1652 1653 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 1654 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1655 IEM_MC_END(); 1656 break; 1657 1658 case IEMMODE_64BIT: 1659 IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT, 0); 1660 IEM_MC_ARG(uint64_t *, pu64Dst, 0); 1661 IEM_MC_ARG(uint64_t, u64Src, 1); 1662 IEM_MC_ARG(uint32_t *, pEFlags, 2); 1663 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); 1664 1665 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 1666 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1667 IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 1668 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); 1669 IEM_MC_REF_EFLAGS(pEFlags); 1670 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xor_u64, pu64Dst, u64Src, pEFlags); 1671 1672 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1673 IEM_MC_END(); 1674 break; 1675 1676 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 1677 } 1678 } 1679 /* END TEMP EXPERIMENTAL CODE */ 1547 1680 } 1548 1681 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py
r103592 r103613 1895 1895 class McStmtCond(McStmt): 1896 1896 """ 1897 Base class for conditional statements (IEM_MC_IF_XXX ).1897 Base class for conditional statements (IEM_MC_IF_XXX, IEM_MC_NATIVE_IF). 1898 1898 """ 1899 1899 def __init__(self, sName, asParams, aoIfBranch = None, aoElseBranch = None): … … 1903 1903 self.oIfBranchAnnotation = None; ##< User specific IF-branch annotation. 1904 1904 self.oElseBranchAnnotation = None; ##< User specific IF-branch annotation. 1905 self.sNativeInfix = '' if sName != 'IEM_MC_NATIVE_IF' else '_NATIVE'; 1905 1906 1906 1907 def renderCode(self, cchIndent = 0): … … 1908 1909 sRet += self.renderCodeForList(self.aoIfBranch, cchIndent + 4); 1909 1910 if self.aoElseBranch: 1910 sRet += ' ' * cchIndent + '} IEM_MC _ELSE() {\n';1911 sRet += ' ' * cchIndent + '} IEM_MC%s_ELSE() {\n' % (self.sNativeInfix,); 1911 1912 sRet += self.renderCodeForList(self.aoElseBranch, cchIndent + 4); 1912 sRet += ' ' * cchIndent + '} IEM_MC _ENDIF();\n';1913 sRet += ' ' * cchIndent + '} IEM_MC%s_ENDIF();\n' % (self.sNativeInfix,); 1913 1914 return sRet; 1914 1915 … … 2255 2256 2256 2257 @staticmethod 2258 def parseMcLocalEFlags(oSelf, sName, asParams): 2259 """ IEM_MC_LOCAL_EFLAGS""" 2260 oSelf.checkStmtParamCount(sName, asParams, 1); 2261 oStmt = McStmtVar(sName, asParams, 'uint32_t', asParams[0]); 2262 oSelf.aoLocals.append(oStmt); 2263 return oStmt; 2264 2265 @staticmethod 2257 2266 def parseMcCallAImpl(oSelf, sName, asParams): 2258 2267 """ IEM_MC_CALL_AIMPL_3|4 """ … … 2460 2469 + r')'); 2461 2470 2471 kaasConditions = ( 2472 ( 'IEM_MC_IF_', 'IEM_MC_ELSE', 'IEM_MC_ENDIF' ), 2473 ( 'IEM_MC_NATIVE_IF', 'IEM_MC_NATIVE_ELSE', 'IEM_MC_NATIVE_ENDIF' ), 2474 ); 2462 2475 def decodeCode(self, sRawCode, off = 0, offStop = -1, iLevel = 0): # pylint: disable=too-many-statements,too-many-branches 2463 2476 """ … … 2500 2513 # All MC statements ends with a semicolon, except for conditionals which ends with a '{'. 2501 2514 # Extract it and strip comments from it. 2502 if not self.isSubstrAt(sRawCode, off, 'IEM_MC_IF_'): 2515 if self.isSubstrAt(sRawCode, off, self.kaasConditions[0][0]): iCond = 0; 2516 elif self.isSubstrAt(sRawCode, off, self.kaasConditions[1][0]): iCond = 1; 2517 else: iCond = -1; 2518 if iCond < 0: 2503 2519 offEnd = sRawCode.find(';', off + len('IEM_MC_')); 2504 2520 if offEnd <= off: 2505 2521 self.raiseDecodeError(sRawCode, off, 'MC statement without a ";"'); 2506 2522 else: 2507 offEnd = sRawCode.find('{', off + len( 'IEM_MC_IF_'));2523 offEnd = sRawCode.find('{', off + len(self.kaasConditions[iCond][0])); 2508 2524 if offEnd <= off: 2509 2525 self.raiseDecodeError(sRawCode, off, 'MC conditional statement without a "{"'); 2510 if sRawCode.find(';', off + len( 'IEM_MC_IF_'), offEnd) > off:2526 if sRawCode.find(';', off + len(self.kaasConditions[iCond][0]), offEnd) > off: 2511 2527 self.raiseDecodeError(sRawCode, off, 'MC conditional statement without an immediate "{"'); 2512 2528 offEnd -= 1; … … 2552 2568 # } IEM_MC_ENDIF(); 2553 2569 # 2554 if sName.startswith('IEM_MC_IF_'):2555 if iLevel > 1: 2570 if iCond >= 0: 2571 if iLevel > 1: ## @todo discount IEM_MC_NATIVE_IF. 2556 2572 self.raiseDecodeError(sRawCode, off, 'Too deep nesting of conditionals.'); 2557 2573 … … 2570 2586 # Is there an else section? 2571 2587 off = self.skipSpacesAt(sRawCode, offBlock1End + 1, offStop); 2572 if self.isSubstrAt(sRawCode, off, 'IEM_MC_ELSE'): 2573 off = self.skipSpacesAt(sRawCode, off + len('IEM_MC_ELSE'), offStop); 2588 sElseNm = self.kaasConditions[iCond][1]; 2589 if self.isSubstrAt(sRawCode, off, sElseNm): 2590 off = self.skipSpacesAt(sRawCode, off + len(sElseNm), offStop); 2574 2591 if sRawCode[off] != '(': 2575 self.raiseDecodeError(sRawCode, off, 'Expected "(" following IEM_MC_ELSE"');2592 self.raiseDecodeError(sRawCode, off, 'Expected "(" following %s"' % (sElseNm,)); 2576 2593 off = self.skipSpacesAt(sRawCode, off + 1, offStop); 2577 2594 if sRawCode[off] != ')': 2578 self.raiseDecodeError(sRawCode, off, 'Expected ")" following IEM_MC_ELSE("');2595 self.raiseDecodeError(sRawCode, off, 'Expected ")" following %s("' % (sElseNm,)); 2579 2596 2580 2597 # Find start of the ELSE block. 2581 2598 offBlock2 = self.skipSpacesAt(sRawCode, off + 1, offStop); 2582 2599 if sRawCode[offBlock2] != '{': 2583 self.raiseDecodeError(sRawCode, offBlock2, 'Expected "{" following IEM_MC_ELSE()"');2600 self.raiseDecodeError(sRawCode, offBlock2, 'Expected "{" following %s()"' % (sElseNm,)); 2584 2601 2585 2602 # Find the end of it. … … 2592 2609 2593 2610 # Parse past the endif statement. 2594 if not self.isSubstrAt(sRawCode, off, 'IEM_MC_ENDIF'): 2595 self.raiseDecodeError(sRawCode, off, 'Expected IEM_MC_ENDIF for closing %s' % (sName,)); 2596 off = self.skipSpacesAt(sRawCode, off + len('IEM_MC_ENDIF'), offStop); 2611 sEndIfNm = self.kaasConditions[iCond][2]; 2612 if not self.isSubstrAt(sRawCode, off, sEndIfNm): 2613 self.raiseDecodeError(sRawCode, off, 'Expected %s for closing %s' % (sEndIfNm, sName,)); 2614 off = self.skipSpacesAt(sRawCode, off + len(sEndIfNm), offStop); 2597 2615 if sRawCode[off] != '(': 2598 self.raiseDecodeError(sRawCode, off, 'Expected "(" following IEM_MC_ENDIF"');2616 self.raiseDecodeError(sRawCode, off, 'Expected "(" following %s"' % (sEndIfNm,)); 2599 2617 off = self.skipSpacesAt(sRawCode, off + 1, offStop); 2600 2618 if sRawCode[off] != ')': 2601 self.raiseDecodeError(sRawCode, off, 'Expected ")" following IEM_MC_ENDIF("');2619 self.raiseDecodeError(sRawCode, off, 'Expected ")" following %s("' % (sEndIfNm,)); 2602 2620 off = self.skipSpacesAt(sRawCode, off + 1, offStop); 2603 2621 if sRawCode[off] != ';': 2604 self.raiseDecodeError(sRawCode, off, 'Expected ";" following IEM_MC_ENDIF()"');2622 self.raiseDecodeError(sRawCode, off, 'Expected ";" following %s()"' % (sEndIfNm,)); 2605 2623 off += 1; 2606 2624 … … 3103 3121 'IEM_MC_LOCAL_ASSIGN': (McBlock.parseMcLocalAssign, False, False, True, ), 3104 3122 'IEM_MC_LOCAL_CONST': (McBlock.parseMcLocalConst, False, False, True, ), 3123 'IEM_MC_LOCAL_EFLAGS': (McBlock.parseMcLocalEFlags, True, True, True, ), 3105 3124 'IEM_MC_NOREF': (McBlock.parseMcGeneric, False, False, True, ), 3106 3125 'IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT': (McBlock.parseMcGeneric, True, True, False, ), … … 3154 3173 'IEM_MC_MODIFIED_MREG': (McBlock.parseMcGeneric, True, True, False, ), 3155 3174 'IEM_MC_MODIFIED_MREG_BY_REF': (McBlock.parseMcGeneric, True, True, False, ), 3175 'IEM_MC_NATIVE_EMIT_0': (McBlock.parseMcGeneric, True, True, True, ), 3176 'IEM_MC_NATIVE_EMIT_1': (McBlock.parseMcGeneric, True, True, True, ), 3177 'IEM_MC_NATIVE_EMIT_2': (McBlock.parseMcGeneric, True, True, True, ), 3178 'IEM_MC_NATIVE_EMIT_3': (McBlock.parseMcGeneric, True, True, True, ), 3179 'IEM_MC_NATIVE_EMIT_4': (McBlock.parseMcGeneric, True, True, True, ), 3180 'IEM_MC_NATIVE_EMIT_5': (McBlock.parseMcGeneric, True, True, True, ), 3181 'IEM_MC_NATIVE_EMIT_6': (McBlock.parseMcGeneric, True, True, True, ), 3182 'IEM_MC_NATIVE_EMIT_7': (McBlock.parseMcGeneric, True, True, True, ), 3183 'IEM_MC_NATIVE_IF': (McBlock.parseMcGenericCond, False, False, True, ), 3184 'IEM_MC_NATIVE_ELSE': (McBlock.parseMcGenericCond, False, False, True, ), 3185 'IEM_MC_NATIVE_ENDIF': (McBlock.parseMcGenericCond, False, False, True, ), 3156 3186 'IEM_MC_OR_2LOCS_U32': (McBlock.parseMcGeneric, False, False, False, ), 3157 3187 'IEM_MC_OR_GREG_U16': (McBlock.parseMcGeneric, True, True, False, ), -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veLiveness.cpp
r103393 r103613 981 981 #define IEM_MC_MEM_ROLLBACK_AND_UNMAP_WO(a_bMapInfo) NOP() 982 982 983 #define IEM_MC_NATIVE_IF(a_fSupportedHosts) { 984 #define IEM_MC_NATIVE_ELSE() } { 985 #define IEM_MC_NATIVE_ENDIF() } ((void)0) 986 987 #define IEM_MC_NATIVE_EMIT_0(a_fnEmitter) 988 #define IEM_MC_NATIVE_EMIT_1(a_fnEmitter, a0) NOP() 989 #define IEM_MC_NATIVE_EMIT_2(a_fnEmitter, a0, a1) NOP() 990 #define IEM_MC_NATIVE_EMIT_3(a_fnEmitter, a0, a1, a2) NOP() 991 #define IEM_MC_NATIVE_EMIT_4(a_fnEmitter, a0, a1, a2, a3) NOP() 992 #define IEM_MC_NATIVE_EMIT_5(a_fnEmitter, a0, a1, a2, a3, a4) NOP() 993 #define IEM_MC_NATIVE_EMIT_6(a_fnEmitter, a0, a1, a2, a3, a4, a5) NOP() 994 #define IEM_MC_NATIVE_EMIT_7(a_fnEmitter, a0, a1, a2, a3, a4, a5, a6) NOP() 995 #define IEM_MC_NATIVE_EMIT_8(a_fnEmitter, a0, a1, a2, a3, a4, a5, a6, a7) NOP() 983 996 984 997 #define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) NOP() -
trunk/src/VBox/VMM/VMMAll/IEMAllN8vePython.py
r103259 r103613 306 306 else: 307 307 aoStmts.insert(iStmt + 1, iai.McStmt('IEM_MC_FREE_ARG', [sVarName,])); 308 if fIncludeReferences and oVarInfo. sReference:308 if fIncludeReferences and oVarInfo.oReferences: 309 309 sRefVarName = oVarInfo.oReferences.oStmt.sVarName; 310 310 if sRefVarName in dVars: … … 441 441 if sVarName in dVars: 442 442 freeVariable(aoStmts, len(aoStmts) - 1, dVars[sVarName], dFreedVars, dVars); 443 if sVarName in dFreedVars: 444 del dFreedVars[sVarName]; ## @todo Try eliminate this one... 443 445 return dFreedVars; 444 446 -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp
r103596 r103613 6147 6147 } return off 6148 6148 6149 6150 6151 /********************************************************************************************************************************* 6152 * Native Emitter Support. * 6153 *********************************************************************************************************************************/ 6154 6155 6156 #define IEM_MC_NATIVE_IF(a_fSupportedHosts) if (RT_ARCH_VAL & (a_fSupportedHosts)) { 6157 6158 #define IEM_MC_NATIVE_ELSE() } else { 6159 6160 #define IEM_MC_NATIVE_ENDIF() } ((void)0) 6161 6162 6163 #define IEM_MC_NATIVE_EMIT_0(a_fnEmitter) \ 6164 off = a_fnEmitter(pReNative, off) 6165 6166 #define IEM_MC_NATIVE_EMIT_1(a_fnEmitter, a0) \ 6167 off = a_fnEmitter(pReNative, off, (a0)) 6168 6169 #define IEM_MC_NATIVE_EMIT_2(a_fnEmitter, a0, a1) \ 6170 off = a_fnEmitter(pReNative, off, (a0), (a1)) 6171 6172 #define IEM_MC_NATIVE_EMIT_3(a_fnEmitter, a0, a1, a2) \ 6173 off = a_fnEmitter(pReNative, off, (a0), (a1), (a2)) 6174 6175 #define IEM_MC_NATIVE_EMIT_4(a_fnEmitter, a0, a1, a2, a3) \ 6176 off = a_fnEmitter(pReNative, off, (a0), (a1), (a2), (a3)) 6177 6178 #define IEM_MC_NATIVE_EMIT_5(a_fnEmitter, a0, a1, a2, a3, a4) \ 6179 off = a_fnEmitter(pReNative, off, (a0), (a1), (a2), (a3), (a4)) 6180 6181 #define IEM_MC_NATIVE_EMIT_6(a_fnEmitter, a0, a1, a2, a3, a4, a5) \ 6182 off = a_fnEmitter(pReNative, off, (a0), (a1), (a2), (a3), (a4), (a5)) 6183 6184 #define IEM_MC_NATIVE_EMIT_7(a_fnEmitter, a0, a1, a2, a3, a4, a5, a6) \ 6185 off = a_fnEmitter(pReNative, off, (a0), (a1), (a2), (a3), (a4), (a5), (a6)) 6186 6187 #define IEM_MC_NATIVE_EMIT_8(a_fnEmitter, a0, a1, a2, a3, a4, a5, a6, a7) \ 6188 off = a_fnEmitter(pReNative, off, (a0), (a1), (a2), (a3), (a4), (a5), (a6), (a7)) 6189 6190 6191 /** 6192 * This is an implementation of IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL 6193 * and friends. 6194 * 6195 * It takes liveness stuff into account. 6196 */ 6197 DECL_INLINE_THROW(uint32_t) 6198 iemNativeEmitEFlagsForLogical(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarEfl, 6199 uint8_t cOpBits, uint8_t idxRegResult) 6200 { 6201 #ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS 6202 if (1) /** @todo check if all bits are clobbered. */ 6203 #endif 6204 { 6205 #ifdef RT_ARCH_AMD64 6206 /* 6207 * Collect flags and merge them with eflags. 6208 */ 6209 /** @todo we could alternatively use SAHF here when host rax is free since, 6210 * OF is cleared. */ 6211 PIEMNATIVEINSTR pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1); 6212 /* pushf - do this before any reg allocations as they may emit instructions too. */ 6213 pCodeBuf[off++] = 0x9c; 6214 6215 uint8_t const idxRegEfl = iemNativeVarRegisterAcquire(pReNative, idxVarEfl, &off, true /*fInitialized*/); 6216 uint8_t const idxTmpReg = iemNativeRegAllocTmp(pReNative, &off); 6217 pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2 + 6 + 6 + 3); 6218 /* pop tmp */ 6219 if (idxTmpReg >= 8) 6220 pCodeBuf[off++] = X86_OP_REX_B; 6221 pCodeBuf[off++] = 0x58 + (idxTmpReg & 7); 6222 /* and tmp, X86_EFL_PF | X86_EFL_ZF | X86_EFL_SF */ 6223 off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, idxTmpReg, X86_EFL_PF | X86_EFL_ZF | X86_EFL_SF); 6224 /* Clear the status bits in EFLs. */ 6225 off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, idxRegEfl, ~X86_EFL_STATUS_BITS); 6226 /* OR in the flags we collected. */ 6227 off = iemNativeEmitOrGpr32ByGprEx(pCodeBuf, off, idxRegEfl, idxTmpReg); 6228 iemNativeVarRegisterRelease(pReNative, idxVarEfl); 6229 iemNativeRegFreeTmp(pReNative, idxTmpReg); 6230 RT_NOREF(cOpBits, idxRegResult); 6231 6232 #elif defined(RT_ARCH_ARM64) 6233 /* 6234 * Calculate flags. 6235 */ 6236 uint8_t const idxRegEfl = iemNativeVarRegisterAcquire(pReNative, idxVarEfl, &off, true /*fInitialized*/); 6237 uint8_t const idxTmpReg = iemNativeRegAllocTmp(pReNative, &off); 6238 PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 15); 6239 6240 /* Clear the status bits. ~0x8D5 (or ~0x8FD) can't be AND immediate, so use idxTmpReg for constant. */ 6241 off = iemNativeEmitLoadGpr32ImmEx(pCodeBuf, off, idxTmpReg, ~X86_EFL_STATUS_BITS); 6242 off = iemNativeEmitAndGpr32ByGpr32Ex(pCodeBuf, off, idxRegEfl, idxTmpReg); 6243 6244 /* Calculate zero: mov tmp, zf; cmp result,zero; csel.eq tmp,tmp,wxr */ 6245 if (cOpBits > 32) 6246 off = iemNativeEmitCmpGprWithGprEx(pCodeBuf, off, idxRegResult, ARMV8_A64_REG_XZR); 6247 else 6248 off = iemNativeEmitCmpGpr32WithGprEx(pCodeBuf, off, idxRegResult, ARMV8_A64_REG_XZR); 6249 # if 0 6250 off = iemNativeEmitLoadGpr32ImmEx(pCodeBuf, off, idxTmpReg, X86_EFL_ZF); 6251 pCodeBuf[off++] = Armv8A64MkInstrCSel(idxTmpReg, idxTmpReg, ARMV8_A64_REG_XZR, kArmv8InstrCond_Eq, false /*f64Bit*/); 6252 pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegEfl, idxRegEfl, idxTmpReg, false /*f64Bit*/); 6253 # else 6254 pCodeBuf[off++] = Armv8A64MkInstrCSet(idxTmpReg, kArmv8InstrCond_Eq, false /*f64Bit*/); 6255 pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegEfl, idxRegEfl, idxTmpReg, false /*f64Bit*/, X86_EFL_ZF_BIT); 6256 # endif 6257 6258 /* Calculate signed: We could use the native SF flag, but it's just as simple to calculate it by shifting. */ 6259 pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxTmpReg, idxRegResult, cOpBits - 1, cOpBits > 32 /*f64Bit*/); 6260 pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegEfl, idxRegEfl, idxTmpReg, false /*f64Bit*/, X86_EFL_SF_BIT); 6261 6262 /* Calculate 8-bit parity of the result. */ 6263 pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxRegResult, idxRegResult, false /*f64Bit*/, 6264 4 /*offShift6*/, kArmv8A64InstrShift_Lsr); 6265 pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxTmpReg, idxTmpReg, false /*f64Bit*/, 6266 2 /*offShift6*/, kArmv8A64InstrShift_Lsr); 6267 pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxTmpReg, idxTmpReg, false /*f64Bit*/, 6268 1 /*offShift6*/, kArmv8A64InstrShift_Lsr); 6269 Assert(Armv8A64ConvertImmRImmS2Mask32(0, 0) == 1); 6270 pCodeBuf[off++] = Armv8A64MkInstrEorImm(idxTmpReg, idxTmpReg, 0, 0, false /*f64Bit*/); 6271 pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_PF_BIT, 1, false /*f64Bit*/); 6272 6273 iemNativeVarRegisterRelease(pReNative, idxVarEfl); 6274 iemNativeRegFreeTmp(pReNative, idxTmpReg); 6275 #else 6276 # error "port me" 6277 #endif 6278 IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off); 6279 } 6280 return off; 6281 } 6282 6283 /** @todo move this somewhere else ... */ 6284 DECL_INLINE_THROW(uint32_t) 6285 iemNativeEmit_xor_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off, 6286 uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits) 6287 { 6288 /* 6289 * The XOR instruction will clear OF, CF and AF (latter is off undefined), 6290 * so we don't need the initial destination value. 6291 */ 6292 uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/); 6293 uint8_t const idxRegSrc = iemNativeVarRegisterAcquire(pReNative, idxVarSrc, &off, true /*fInitialized*/); 6294 //off = iemNativeEmitBrk(pReNative, off, 0x2222); 6295 if (cOpBits > 32) 6296 off = iemNativeEmitXorGprByGpr(pReNative, off, idxRegDst, idxRegSrc); 6297 else 6298 off = iemNativeEmitXorGpr32ByGpr32(pReNative, off, idxRegDst, idxRegSrc); 6299 iemNativeVarRegisterRelease(pReNative, idxVarSrc); 6300 6301 off = iemNativeEmitEFlagsForLogical(pReNative, off, idxVarEfl, cOpBits, idxRegDst); 6302 iemNativeVarRegisterRelease(pReNative, idxVarDst); 6303 return off; 6304 } 6149 6305 6150 6306 -
trunk/src/VBox/VMM/VMMAll/IEMAllThrdPython.py
r103560 r103613 956 956 }; 957 957 958 def analyzeMorphStmtForThreaded(self, aoStmts, dState, iParamRef = 0 ):958 def analyzeMorphStmtForThreaded(self, aoStmts, dState, iParamRef = 0, iLevel = 0): 959 959 """ 960 960 Transforms (copy) the statements into those for the threaded function. … … 1067 1067 aoThreadedStmts.insert(len(aoThreadedStmts) - 1, 1068 1068 iai.McStmtAssertEFlags(self.oParent.oMcBlock.oInstruction)); 1069 del dState['IEM_MC_ASSERT_EFLAGS']; 1069 1070 1070 1071 # ... and IEM_MC_*_GREG_U8 into *_THREADED w/ reworked index taking REX into account … … 1111 1112 # For IEM_MC_REF_EFLAGS we to emit an MC before the ..._FINISH 1112 1113 if oNewStmt.sName == 'IEM_MC_REF_EFLAGS_EX': 1113 dState['IEM_MC_ASSERT_EFLAGS'] = True;1114 dState['IEM_MC_ASSERT_EFLAGS'] = iLevel; 1114 1115 1115 1116 # Process branches of conditionals recursively. 1116 1117 if isinstance(oStmt, iai.McStmtCond): 1117 (oNewStmt.aoIfBranch, iParamRef) = self.analyzeMorphStmtForThreaded(oStmt.aoIfBranch, dState, iParamRef); 1118 (oNewStmt.aoIfBranch, iParamRef) = self.analyzeMorphStmtForThreaded(oStmt.aoIfBranch, dState, 1119 iParamRef, iLevel + 1); 1118 1120 if oStmt.aoElseBranch: 1119 1121 (oNewStmt.aoElseBranch, iParamRef) = self.analyzeMorphStmtForThreaded(oStmt.aoElseBranch, 1120 dState, iParamRef); 1122 dState, iParamRef, iLevel + 1); 1123 1124 # Insert an MC so we can assert the correctioness of modified flags annotations 1125 # on IEM_MC_REF_EFLAGS if it goes out of scope. 1126 if dState.get('IEM_MC_ASSERT_EFLAGS', -1) == iLevel: 1127 aoThreadedStmts.append(iai.McStmtAssertEFlags(self.oParent.oMcBlock.oInstruction)); 1128 del dState['IEM_MC_ASSERT_EFLAGS']; 1121 1129 1122 1130 return (aoThreadedStmts, iParamRef); … … 1289 1297 assert oStmt.idxFn == 2; 1290 1298 aiSkipParams[0] = True; 1299 1300 # Skip the function parameter (first) for IEM_MC_NATIVE_EMIT_X. 1301 if oStmt.sName.startswith('IEM_MC_NATIVE_EMIT_'): 1302 aiSkipParams[0] = True; 1291 1303 1292 1304 … … 1382 1394 or sRef.startswith('iemAImpl_') 1383 1395 or sRef.startswith('kIemNativeGstReg_') 1396 or sRef.startswith('RT_ARCH_VAL_') 1384 1397 or sRef in ( 'int8_t', 'int16_t', 'int32_t', 'int64_t', 1385 1398 'INT8_C', 'INT16_C', 'INT32_C', 'INT64_C', -
trunk/src/VBox/VMM/include/IEMMc.h
r103256 r103613 207 207 uint32_t a_Name; \ 208 208 uint32_t *a_pName = &a_Name 209 #define IEM_MC_LOCAL_EFLAGS(a_Name) uint32_t a_Name = pVCpu->cpum.GstCtx.eflags.u 209 210 #define IEM_MC_COMMIT_EFLAGS(a_EFlags) \ 210 211 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0) … … 2561 2562 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (a_bRm), (a_cbImmAndRspOffset))) 2562 2563 #endif 2564 2565 2566 /** The @a a_fSpportedHosts mask are ORed together RT_ARCH_VAL_XXX values. */ 2567 #define IEM_MC_NATIVE_IF(a_fSupportedHosts) if (false) { 2568 #define IEM_MC_NATIVE_ELSE() } else { 2569 #define IEM_MC_NATIVE_ENDIF() } ((void)0) 2570 2571 #define IEM_MC_NATIVE_EMIT_0(a_fnEmitter) 2572 #define IEM_MC_NATIVE_EMIT_1(a_fnEmitter, a0) (void)(a0) 2573 #define IEM_MC_NATIVE_EMIT_2(a_fnEmitter, a0, a1) (void)(a0), (void)(a1) 2574 #define IEM_MC_NATIVE_EMIT_3(a_fnEmitter, a0, a1, a2) (void)(a0), (void)(a1), (void)(a2) 2575 #define IEM_MC_NATIVE_EMIT_4(a_fnEmitter, a0, a1, a2, a3) (void)(a0), (void)(a1), (void)(a2), (void)(a3) 2576 #define IEM_MC_NATIVE_EMIT_5(a_fnEmitter, a0, a1, a2, a3, a4) (void)(a0), (void)(a1), (void)(a2), (void)(a3), (void)(a4) 2577 #define IEM_MC_NATIVE_EMIT_6(a_fnEmitter, a0, a1, a2, a3, a4, a5) (void)(a0), (void)(a1), (void)(a2), (void)(a3), (void)(a4), (void)(a5) 2578 #define IEM_MC_NATIVE_EMIT_7(a_fnEmitter, a0, a1, a2, a3, a4, a5, a6) (void)(a0), (void)(a1), (void)(a2), (void)(a3), (void)(a4), (void)(a5), (void)(a6) 2579 #define IEM_MC_NATIVE_EMIT_8(a_fnEmitter, a0, a1, a2, a3, a4, a5, a6, a7) (void)(a0), (void)(a1), (void)(a2), (void)(a3), (void)(a4), (void)(a5), (void)(a6), (void)(a7) 2580 2563 2581 2564 2582 #define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)() -
trunk/src/VBox/VMM/include/IEMN8veRecompilerEmit.h
r103585 r103613 4561 4561 */ 4562 4562 DECL_INLINE_THROW(uint32_t) 4563 iemNativeEmitXorGprByGpr (PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGprDst, uint8_t iGprSrc)4563 iemNativeEmitXorGprByGprEx(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t iGprDst, uint8_t iGprSrc) 4564 4564 { 4565 4565 #if defined(RT_ARCH_AMD64) 4566 4566 /* and Gv, Ev */ 4567 uint8_t *pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 3); 4568 pbCodeBuf[off++] = X86_OP_REX_W | (iGprDst < 8 ? 0 : X86_OP_REX_R) | (iGprSrc < 8 ? 0 : X86_OP_REX_B); 4569 pbCodeBuf[off++] = 0x33; 4570 pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iGprDst & 7, iGprSrc & 7); 4571 4572 #elif defined(RT_ARCH_ARM64) 4573 uint32_t *pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1); 4574 pu32CodeBuf[off++] = Armv8A64MkInstrEor(iGprDst, iGprDst, iGprSrc); 4567 pCodeBuf[off++] = X86_OP_REX_W | (iGprDst < 8 ? 0 : X86_OP_REX_R) | (iGprSrc < 8 ? 0 : X86_OP_REX_B); 4568 pCodeBuf[off++] = 0x33; 4569 pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iGprDst & 7, iGprSrc & 7); 4570 4571 #elif defined(RT_ARCH_ARM64) 4572 pCodeBuf[off++] = Armv8A64MkInstrEor(iGprDst, iGprDst, iGprSrc); 4575 4573 4576 4574 #else 4577 4575 # error "Port me" 4578 4576 #endif 4577 return off; 4578 } 4579 4580 4581 /** 4582 * Emits code for XOR'ing two 64-bit GPRs. 4583 */ 4584 DECL_INLINE_THROW(uint32_t) 4585 iemNativeEmitXorGprByGpr(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGprDst, uint8_t iGprSrc) 4586 { 4587 #if defined(RT_ARCH_AMD64) 4588 off = iemNativeEmitXorGprByGprEx(iemNativeInstrBufEnsure(pReNative, off, 3), off, iGprDst, iGprSrc); 4589 #elif defined(RT_ARCH_ARM64) 4590 off = iemNativeEmitXorGprByGprEx(iemNativeInstrBufEnsure(pReNative, off, 1), off, iGprDst, iGprSrc); 4591 #else 4592 # error "Port me" 4593 #endif 4579 4594 IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off); 4580 4595 return off; … … 4586 4601 */ 4587 4602 DECL_INLINE_THROW(uint32_t) 4588 iemNativeEmitXorGpr32ByGpr32 (PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGprDst, uint8_t iGprSrc)4603 iemNativeEmitXorGpr32ByGpr32Ex(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t iGprDst, uint8_t iGprSrc) 4589 4604 { 4590 4605 #if defined(RT_ARCH_AMD64) 4591 4606 /* and Gv, Ev */ 4592 uint8_t *pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 3);4593 4607 if (iGprDst >= 8 || iGprSrc >= 8) 4594 pbCodeBuf[off++] = (iGprDst < 8 ? 0 : X86_OP_REX_R) | (iGprSrc < 8 ? 0 : X86_OP_REX_B); 4595 pbCodeBuf[off++] = 0x33; 4596 pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iGprDst & 7, iGprSrc & 7); 4597 4598 #elif defined(RT_ARCH_ARM64) 4599 uint32_t *pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1); 4600 pu32CodeBuf[off++] = Armv8A64MkInstrEor(iGprDst, iGprDst, iGprSrc, false /*f64Bit*/); 4601 4608 pCodeBuf[off++] = (iGprDst < 8 ? 0 : X86_OP_REX_R) | (iGprSrc < 8 ? 0 : X86_OP_REX_B); 4609 pCodeBuf[off++] = 0x33; 4610 pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iGprDst & 7, iGprSrc & 7); 4611 4612 #elif defined(RT_ARCH_ARM64) 4613 pCodeBuf[off++] = Armv8A64MkInstrEor(iGprDst, iGprDst, iGprSrc, false /*f64Bit*/); 4614 4615 #else 4616 # error "Port me" 4617 #endif 4618 return off; 4619 } 4620 4621 4622 /** 4623 * Emits code for XOR'ing two 32-bit GPRs. 4624 */ 4625 DECL_INLINE_THROW(uint32_t) 4626 iemNativeEmitXorGpr32ByGpr32(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGprDst, uint8_t iGprSrc) 4627 { 4628 #if defined(RT_ARCH_AMD64) 4629 off = iemNativeEmitXorGpr32ByGpr32Ex(iemNativeInstrBufEnsure(pReNative, off, 3), off, iGprDst, iGprSrc); 4630 #elif defined(RT_ARCH_ARM64) 4631 off = iemNativeEmitXorGpr32ByGpr32Ex(iemNativeInstrBufEnsure(pReNative, off, 1), off, iGprDst, iGprSrc); 4602 4632 #else 4603 4633 # error "Port me" -
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r103256 r103613 574 574 #define IEM_MC_END() \ 575 575 } 576 577 #define IEM_MC_NATIVE_IF(a_fSupportedHosts) \ 578 (void)fMcBegin; \ 579 AssertCompile( (a_fSupportedHosts) == 0 \ 580 || (a_fSupportedHosts) == RT_ARCH_VAL_AMD64 \ 581 || (a_fSupportedHosts) == RT_ARCH_VAL_ARM64 \ 582 || (a_fSupportedHosts) == (RT_ARCH_VAL_ARM64 | RT_ARCH_VAL_AMD64) ); \ 583 if (g_fRandom) { 584 #define IEM_MC_NATIVE_ELSE() } else { 585 #define IEM_MC_NATIVE_ENDIF() } do { (void)fMcBegin; } while (0) 586 587 #define IEM_MC_NATIVE_EMIT_0(a_fnEmitter) do { (void)fMcBegin; } while (0) 588 #define IEM_MC_NATIVE_EMIT_1(a_fnEmitter, a0) do { (void)fMcBegin; (void)(a0); } while (0) 589 #define IEM_MC_NATIVE_EMIT_2(a_fnEmitter, a0, a1) do { (void)fMcBegin; (void)(a0), (void)(a1); } while (0) 590 #define IEM_MC_NATIVE_EMIT_3(a_fnEmitter, a0, a1, a2) do { (void)fMcBegin; (void)(a0), (void)(a1), (void)(a2); } while (0) 591 #define IEM_MC_NATIVE_EMIT_4(a_fnEmitter, a0, a1, a2, a3) do { (void)fMcBegin; (void)(a0), (void)(a1), (void)(a2), (void)(a3); } while (0) 592 #define IEM_MC_NATIVE_EMIT_5(a_fnEmitter, a0, a1, a2, a3, a4) do { (void)fMcBegin; (void)(a0), (void)(a1), (void)(a2), (void)(a3), (void)(a4); } while (0) 593 #define IEM_MC_NATIVE_EMIT_6(a_fnEmitter, a0, a1, a2, a3, a4, a5) do { (void)fMcBegin; (void)(a0), (void)(a1), (void)(a2), (void)(a3), (void)(a4), (void)(a5); } while (0) 594 #define IEM_MC_NATIVE_EMIT_7(a_fnEmitter, a0, a1, a2, a3, a4, a5, a6) do { (void)fMcBegin; (void)(a0), (void)(a1), (void)(a2), (void)(a3), (void)(a4), (void)(a5), (void)(a6); } while (0) 595 #define IEM_MC_NATIVE_EMIT_8(a_fnEmitter, a0, a1, a2, a3, a4, a5, a6, a7) do { (void)fMcBegin; (void)(a0), (void)(a1), (void)(a2), (void)(a3), (void)(a4), (void)(a5), (void)(a6), (void)(a7); } while (0) 596 576 597 #define IEM_MC_NO_NATIVE_RECOMPILE() ((void)0) 577 598
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