- Timestamp:
- Feb 27, 2024 4:41:11 PM (7 months ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 5 edited
-
VMMAll/IEMAllInstOneByte.cpp.h (modified) (4 diffs)
-
VMMAll/IEMAllInstPython.py (modified) (1 diff)
-
VMMAll/IEMAllInstTwoByte0f.cpp.h (modified) (2 diffs)
-
VMMAll/IEMAllN8veRecompiler.cpp (modified) (2 diffs)
-
include/IEMN8veRecompiler.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h
r103589 r103590 10396 10396 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, /*=*/ pVCpu->iem.s.enmEffOpSize, 0); 10397 10397 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 1); 10398 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, 0, iemCImpl_fnstenv, enmEffOpSize, iEffSeg, GCPtrEffDst); 10398 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, RT_BIT_64(kIemNativeGstReg_FpuFcw) | RT_BIT_64(kIemNativeGstReg_FpuFsw), 10399 iemCImpl_fnstenv, enmEffOpSize, iEffSeg, GCPtrEffDst); 10399 10400 IEM_MC_END(); 10400 10401 } … … 11725 11726 IEMOP_MNEMONIC(fninit, "fninit"); 11726 11727 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11727 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_FPU, RT_BIT_64(kIemNativeGstReg_FpuFcw) ,11728 IEM_MC_DEFER_TO_CIMPL_1_RET(IEM_CIMPL_F_FPU, RT_BIT_64(kIemNativeGstReg_FpuFcw) | RT_BIT_64(kIemNativeGstReg_FpuFsw), 11728 11729 iemCImpl_finit, false /*fCheckXcpts*/); 11729 11730 } … … 12267 12268 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, /*=*/ pVCpu->iem.s.enmEffOpSize, 0); 12268 12269 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 1); 12269 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, RT_BIT_64(kIemNativeGstReg_FpuFcw) ,12270 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, RT_BIT_64(kIemNativeGstReg_FpuFcw) | RT_BIT_64(kIemNativeGstReg_FpuFsw), 12270 12271 iemCImpl_frstor, enmEffOpSize, iEffSeg, GCPtrEffSrc); 12271 12272 IEM_MC_END(); … … 12287 12288 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, /*=*/ pVCpu->iem.s.enmEffOpSize, 0); 12288 12289 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 1); 12289 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, RT_BIT_64(kIemNativeGstReg_FpuFcw) ,12290 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, RT_BIT_64(kIemNativeGstReg_FpuFcw) | RT_BIT_64(kIemNativeGstReg_FpuFsw), 12290 12291 iemCImpl_fnsave, enmEffOpSize, iEffSeg, GCPtrEffDst); 12291 12292 IEM_MC_END(); -
trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py
r103589 r103590 2963 2963 'IEM_MC_FETCH_EFLAGS_U8': (McBlock.parseMcGeneric, False, False, False, ), 2964 2964 'IEM_MC_FETCH_FCW': (McBlock.parseMcGeneric, False, False, True, ), 2965 'IEM_MC_FETCH_FSW': (McBlock.parseMcGeneric, False, False, False,),2965 'IEM_MC_FETCH_FSW': (McBlock.parseMcGeneric, False, False, True, ), 2966 2966 'IEM_MC_FETCH_GREG_U16': (McBlock.parseMcGeneric, False, False, True, ), 2967 2967 'IEM_MC_FETCH_GREG_U16_SX_U32': (McBlock.parseMcGeneric, False, False, True, ), -
trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h
r103589 r103590 10029 10029 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0); 10030 10030 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, /*=*/pVCpu->iem.s.enmEffOpSize, 2); 10031 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, RT_BIT_64(kIemNativeGstReg_FpuFcw) ,10031 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, RT_BIT_64(kIemNativeGstReg_FpuFcw) | RT_BIT_64(kIemNativeGstReg_FpuFsw), 10032 10032 iemCImpl_fxrstor, iEffSeg, GCPtrEff, enmEffOpSize); 10033 10033 IEM_MC_END(); … … 10153 10153 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0); 10154 10154 IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize, /*=*/ pVCpu->iem.s.enmEffOpSize, 2); 10155 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, RT_BIT_64(kIemNativeGstReg_FpuFcw) ,10155 IEM_MC_CALL_CIMPL_3(IEM_CIMPL_F_FPU, RT_BIT_64(kIemNativeGstReg_FpuFcw) | RT_BIT_64(kIemNativeGstReg_FpuFsw), 10156 10156 iemCImpl_xrstor, iEffSeg, GCPtrEff, enmEffOpSize); 10157 10157 IEM_MC_END(); -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp
r103589 r103590 3500 3500 /* [kIemNativeGstReg_Cr0] = */ { CPUMCTX_OFF_AND_SIZE(cr0), "cr0", }, 3501 3501 /* [kIemNativeGstReg_FpuFcw] = */ { CPUMCTX_OFF_AND_SIZE(XState.x87.FCW), "fcw", }, 3502 /* [kIemNativeGstReg_ LivenessPadding19] = */ { UINT32_MAX / 4, 0, "pad19", },3502 /* [kIemNativeGstReg_FpuFsw] = */ { CPUMCTX_OFF_AND_SIZE(XState.x87.FSW), "fsw", }, 3503 3503 /* [kIemNativeGstReg_SegBaseFirst + 0] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[0].u64Base), "es_base", }, 3504 3504 /* [kIemNativeGstReg_SegBaseFirst + 1] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[1].u64Base), "cs_base", }, … … 13283 13283 /* Free but don't flush the FCW register. */ 13284 13284 iemNativeRegFreeTmp(pReNative, idxFcwReg); 13285 13286 return off; 13287 } 13288 13289 13290 #define IEM_MC_FETCH_FSW(a_u16Fsw) \ 13291 off = iemNativeEmitFetchFpuFsw(pReNative, off, a_u16Fsw) 13292 13293 /** Emits code for IEM_MC_FETCH_FSW. */ 13294 DECL_INLINE_THROW(uint32_t) 13295 iemNativeEmitFetchFpuFsw(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxDstVar) 13296 { 13297 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxDstVar); 13298 Assert(pReNative->Core.aVars[idxDstVar].cbVar == sizeof(uint16_t)); 13299 13300 /* Allocate a temporary FSW register. */ 13301 uint8_t const idxFswReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_FpuFsw, kIemNativeGstRegUse_ReadOnly); 13302 13303 off = iemNativeEmitLoadGprFromGpr16(pReNative, off, idxDstVar, idxFswReg); 13304 13305 /* Free but don't flush the FSW register. */ 13306 iemNativeRegFreeTmp(pReNative, idxFswReg); 13285 13307 13286 13308 return off; -
trunk/src/VBox/VMM/include/IEMN8veRecompiler.h
r103589 r103590 689 689 kIemNativeGstReg_Cr0, 690 690 kIemNativeGstReg_FpuFcw, 691 kIemNativeGstReg_ LivenessPadding19,691 kIemNativeGstReg_FpuFsw, 692 692 kIemNativeGstReg_SegBaseFirst, 693 693 kIemNativeGstReg_SegBaseLast = kIemNativeGstReg_SegBaseFirst + 5,
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